diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2022-09-29 12:24:53 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-30 23:12:15 +0000 |
| commit | cdf99a9b3e2550d2be9dd7c2940ac081ac8eb8e8 (patch) | |
| tree | 6777041759462b5bb565c3abe793f3b3678844aa /src/soc | |
| parent | fb0a751c76e4276728c9317a161d4a8016d5c704 (diff) | |
soc/rockchip/rk3288/clock.c: Remove trailing semicolon
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I0d03bd43b33570ee50f145ea6fd716c4072a11d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/rockchip/rk3288/clock.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index 1576a6a2bf..c2f93f5854 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -53,7 +53,7 @@ static struct rk3288_cru_reg * const cru_ptr = (void *)CRU_BASE; .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\ _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\ (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\ - "divisors on line " STRINGIFY(__LINE__)); + "divisors on line " STRINGIFY(__LINE__)) /* Keep divisors as low as possible to reduce jitter and power usage. */ static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); |