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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-01-19 20:36:38 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-01-20 22:01:31 +0000 |
| commit | cb9773443d8a7cc8b7670e0446d820ab95943196 (patch) | |
| tree | a92af2dc0af4af5792fb049bb4bb917a896ca234 /src/soc | |
| parent | 740d62c9fd4d90cb4a13931550d8f4c6b38adc37 (diff) | |
soc/amd/cezanne/Kconfig: select IDT_IN_EVERY_STAGE
This adds interrupt handlers that end up calling x86_exception().
Change-Id: I3dce539b6f1ef300cf16f20224744a75100f60b8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 50b8777bfb..1a38c77b67 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -14,6 +14,7 @@ config SOC_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select HAVE_CF9_RESET + select IDT_IN_EVERY_STAGE select IOAPIC select RESET_VECTOR_IN_RAM select SOC_AMD_COMMON |