diff options
| author | Shaunak Saha <shaunak.saha@intel.com> | 2017-11-07 09:07:30 -0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-11-17 18:46:24 +0000 |
| commit | c6518b27120dcf45af537ca31098b53f3b8e2ecb (patch) | |
| tree | 14920a691293e4157197fee138467bd5ea4acafb /src/soc | |
| parent | 91b80416b700bbc40f282ba090b1f43d822f36fc (diff) | |
soc/intel/cannonlake: Add cpu.asl file
This patch adds the cpu.asl file in cnl. We are only defining
the PNOT method here in this patch as this is needed by the
ec/google/chromeec/acpi/ec.asl file for the AC methods.
TEST= code compiles and boots when we include the ec.asl file.
Change-Id: Id93012833fac116d4d7514aa2d0b8493d2f666a9
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/cpu.asl | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/acpi/cpu.asl b/src/soc/intel/cannonlake/acpi/cpu.asl new file mode 100644 index 0000000000..79314e6a88 --- /dev/null +++ b/src/soc/intel/cannonlake/acpi/cpu.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* These devices are created at runtime */ +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) +External (\_PR.CP04, DeviceObj) +External (\_PR.CP05, DeviceObj) +External (\_PR.CP06, DeviceObj) +External (\_PR.CP07, DeviceObj) + +/* Notify OS to re-read CPU tables, assuming ^2 CPU count */ +Method (PNOT) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (\_PR.CP00, 0x81) // _CST + Notify (\_PR.CP01, 0x81) // _CST + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (\_PR.CP02, 0x81) // _CST + Notify (\_PR.CP03, 0x81) // _CST + } + If (LGreaterEqual (\PCNT, 8)) { + Notify (\_PR.CP04, 0x81) // _CST + Notify (\_PR.CP05, 0x81) // _CST + Notify (\_PR.CP06, 0x81) // _CST + Notify (\_PR.CP07, 0x81) // _CST + } +} |