soc/intel/xeon_sp: Move get_cxl_mode out of soc/util.h

get_cxl_mode() is the interface for CXL mode config check used by
SoC codes. It could be implemented by mechanisms outside of the
SoC codes, e.g. board codes or OCP VPD driver.

Move the interface declaration out of soc/util.h to a dedicated
header, a.k.a., soc/config.h, so that the implementation codes do
not need to include soc/util.h where there are lots of irrelevant
definitions. Future SoC config check interfaces could be added
to soc/config.h as well.

The default weak implementation is moved out of util.c to
config.c as well.

TEST=Build and boot on intel/archercity CRB

Change-Id: Ia0302b0d3fd93c49e1d6f64e8159f59d50f33e20
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82293
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

8 files changed, 26 insertions, 13 deletions

diff --git a/src/soc/intel/xeon_sp/Makefile.mk b/src/soc/intel/xeon_sp/Makefile.mk
index 3ebc6e0c4a..35b998c850 100644
--- a/src/soc/intel/xeon_sp/Makefile.mk
+++ b/src/soc/intel/xeon_sp/Makefile.mk
@@ -10,10 +10,12 @@ subdirs-$(CONFIG_SOC_INTEL_GRANITERAPIDS) += gnr ebg
 
 bootblock-y += bootblock.c spi.c lpc.c pch.c report_platform.c
 romstage-y += romstage.c reset.c util.c spi.c pmutil.c memmap.c ddr.c
+romstage-y += config.c
 romstage-y += ../../../cpu/intel/car/romstage.c
 ramstage-y += uncore.c reset.c util.c lpc.c spi.c ramstage.c chip_common.c
 ramstage-y += memmap.c pch.c lockdown.c finalize.c
 ramstage-y += numa.c
+ramstage-y += config.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c pmutil.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += uncore_acpi.c acpi.c
 ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c
diff --git a/src/soc/intel/xeon_sp/config.c b/src/soc/intel/xeon_sp/config.c
new file mode 100644
index 0000000000..c2a908c984
--- /dev/null
+++ b/src/soc/intel/xeon_sp/config.c
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/config.h>
+
+__weak enum xeonsp_cxl_mode get_cxl_mode(void)
+{
+	return XEONSP_CXL_DISABLED;
+}
diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h
index 5bdc87fbf5..5fd5dc6f18 100644
--- a/src/soc/intel/xeon_sp/include/soc/chip_common.h
+++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h
@@ -33,12 +33,6 @@ static inline void init_xeon_domain_path(struct device_path *path, int socket,
 	path->domain.domain = dp.domain_path;
 };
 
-enum xeonsp_cxl_mode {
-	XEONSP_CXL_DISABLED = 0,
-	XEONSP_CXL_SYS_MEM,
-	XEONSP_CXL_SP_MEM,
-};
-
 /*
  * Every STACK can have multiple PCI domains with an unique domain type.
  * This is only of cosmetic nature and generates more readable ACPI code,
diff --git a/src/soc/intel/xeon_sp/include/soc/config.h b/src/soc/intel/xeon_sp/include/soc/config.h
new file mode 100644
index 0000000000..6d5f3d587d
--- /dev/null
+++ b/src/soc/intel/xeon_sp/include/soc/config.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _XEON_SP_SOC_CONFIG_H_
+#define _XEON_SP_SOC_CONFIG_H_
+
+enum xeonsp_cxl_mode {
+	XEONSP_CXL_DISABLED = 0,
+	XEONSP_CXL_SYS_MEM,
+	XEONSP_CXL_SP_MEM,
+};
+
+enum xeonsp_cxl_mode get_cxl_mode(void);
+
+#endif
diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h
index af749023b5..e694af3e3c 100644
--- a/src/soc/intel/xeon_sp/include/soc/util.h
+++ b/src/soc/intel/xeon_sp/include/soc/util.h
@@ -31,6 +31,4 @@ void bios_done_msr(void *unused);
 union p2sb_bdf soc_get_hpet_bdf(void);
 union p2sb_bdf soc_get_ioapic_bdf(void);
 
-enum xeonsp_cxl_mode get_cxl_mode(void);
-
 #endif
diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c
index c339506573..26bb3081a1 100644
--- a/src/soc/intel/xeon_sp/spr/romstage.c
+++ b/src/soc/intel/xeon_sp/spr/romstage.c
@@ -20,6 +20,7 @@
 #include <soc/soc_pch.h>
 #include <soc/intel/common/smbios.h>
 #include <string.h>
+#include <soc/config.h>
 #include <soc/soc_util.h>
 #include <soc/util.h>
 #include <soc/ddr.h>
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index 4c226854aa..a6ac7c8be7 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -15,6 +15,7 @@
 #include <fsp/util.h>
 #include <security/intel/txt/txt_platform.h>
 #include <security/intel/txt/txt.h>
+#include <soc/config.h>
 #include <soc/numa.h>
 #include <soc/soc_util.h>
 #include <stdint.h>
diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c
index 2fdf45e04f..4dbe7a4cd7 100644
--- a/src/soc/intel/xeon_sp/util.c
+++ b/src/soc/intel/xeon_sp/util.c
@@ -265,8 +265,3 @@ void set_bios_init_completion(void)
 	set_bios_init_completion_for_package(sbsp_socket_id);
 }
 #endif
-
-__weak enum xeonsp_cxl_mode get_cxl_mode(void)
-{
-	return XEONSP_CXL_DISABLED;
-}