diff options
| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2021-11-18 12:28:31 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-03 15:28:47 +0000 |
| commit | bef5c405821527a0d686a541578c8fe449f1fffa (patch) | |
| tree | 2a92d9315e41f46a36931114f3e54628dc6137e6 /src/soc | |
| parent | 4fcf13a51d2d0343a4930d6e01a7b6d941749e8e (diff) | |
soc/amd/cezanne: Enable secure counters
Guybrush uses secure counters to protect against High Definition (HD)
protected content rollback. These secure counters are hosted in TPM
NVRAM. Enable secure counters so that they are defined in PSP verstage.
BUG=b:205261728
TEST=Build and boot to OS in Guybrush. Ensure that the secure counters
are defined successfully in TPM NVRAM.
Change-Id: I6818c6f7905aa2eb815059e23c4f79437593f8ca
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index b4e808dc47..df37a82ddd 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -72,6 +72,7 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_FSP_PCI select SSE2 select UDK_2017_BINDING + select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK select X86_AMD_FIXED_MTRRS select X86_INIT_NEED_1_SIPI |