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authorPatrick Georgi <pgeorgi@chromium.org>2015-04-30 11:38:13 +0200
committerPatrick Georgi <pgeorgi@google.com>2015-05-07 13:53:15 +0200
commitb4a6ca96c01e1312784a4c9b6961697e846b7b00 (patch)
tree90cae16a4eeae95ac86c0f2dc41d32b3e3e4c009 /src/soc
parentc6e1f8aa12c73635fa4889b6c29b9f91bf4a23d5 (diff)
imgtec/pistachio: Add comment on the unusual memory layout
To avoid having to dig up the constraints again, document the memory layout right in memlayout.ld. Change-Id: I298cc880ae462f5b197ab2f64beb2f0e0d9f5a7d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10039 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/imgtec/pistachio/include/soc/memlayout.ld5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index e9f6c592fe..bc6744741d 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -42,7 +42,10 @@ SECTIONS
PRERAM_CBFS_CACHE(0x1a00e000, 72K)
SRAM_END(0x1a020000)
- /* Bootblock executes out of KSEG0 and sets up the identity mapping. */
+ /* Bootblock executes out of KSEG0 and sets up the identity mapping.
+ * This is identical to SRAM above, and thus also limited 64K and
+ * needs to avoid conflicts with items set up above.
+ */
BOOTBLOCK(0x9a000000, 20K)
/*