diff options
| author | Edward O'Callaghan <quasisec@google.com> | 2019-12-15 13:30:38 +1100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-16 21:32:39 +0000 |
| commit | b4a68a5a28684b99657ae94b9bcb745ae2023863 (patch) | |
| tree | d1c1a8b9b06a6c13f2f12ebe9813a07908779cd3 /src/soc | |
| parent | fc749b23ef41f6bb63370d1377bcdaac250848f6 (diff) | |
src/soc/intel/cannonlake: Bump MAX_CPU from 8->12
This impacts boards:
hatch (&variants) and drallion.
Some variants like Puff can have up to 12 cores. coreboot should take
the min() where MAX_CPU is the upper bound.
Further to that, boards themseleves shouldn't be setting the MAX_CPUS,
the chipset should be and so do that.
BRANCH=none
BUG=b:146255011
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I284d027886f662ebb8414ea92540916ed19bc797
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 6d635ade3d..8820508259 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -108,6 +108,10 @@ config CPU_SPECIFIC_OPTIONS select FSP_T_XIP if FSP_CAR select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE +config MAX_CPUS + int + default 12 + config DCACHE_RAM_BASE default 0xfef00000 |