diff options
| author | CK Hu <ck.hu@mediatek.com> | 2020-08-25 14:46:23 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-08 05:38:36 +0000 |
| commit | af0b00fa4d0429ae45460a81dbb3265c174cf4cc (patch) | |
| tree | 52b1a68170d70aa3ec40d2fe587e4645494ed098 /src/soc | |
| parent | 60296aec76e29acd62b999b2cd72bcea1592f1ed (diff) | |
soc/mediatek/mt8192: Add SPI flash controller dual read function
Support SPI flash dual read funciton which change spi mode (1-1-1)
to dual mode (1-1-2).
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Iabd3668fc4bc42137b7743144fc1cced4fe72737
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44852
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/mediatek/mt8192/flash_controller.c | 3 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/flash_controller.h | 5 |
2 files changed, 7 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8192/flash_controller.c b/src/soc/mediatek/mt8192/flash_controller.c index b2528809bc..aa43af6e0d 100644 --- a/src/soc/mediatek/mt8192/flash_controller.c +++ b/src/soc/mediatek/mt8192/flash_controller.c @@ -132,6 +132,9 @@ static int nor_read(const struct spi_flash *flash, u32 addr, size_t len, u32 done, read_len, copy_len; uint8_t *dest = (uint8_t *)buf; + setbits8(&mt8192_nor->read_dual, SFLASH_READ_DUAL_EN); + write8(&mt8192_nor->prgdata[3], SFLASH_1_1_2_READ); + /* DMA: start [ skip | len | drop ] = total end */ for (done = 0; done < total; dest += copy_len) { read_len = MIN(dma_buf_len, total - done); diff --git a/src/soc/mediatek/mt8192/include/soc/flash_controller.h b/src/soc/mediatek/mt8192/include/soc/flash_controller.h index 5655a9c001..5373a87ef3 100644 --- a/src/soc/mediatek/mt8192/include/soc/flash_controller.h +++ b/src/soc/mediatek/mt8192/include/soc/flash_controller.h @@ -29,7 +29,10 @@ enum { /* DMA commands */ SFLASH_DMA_TRIGGER = 1 << 0, SFLASH_DMA_SW_RESET = 1 << 1, - SFLASH_DMA_WDLE_EN = 1 << 2 + SFLASH_DMA_WDLE_EN = 1 << 2, + /* Dual mode */ + SFLASH_READ_DUAL_EN = 0x1, + SFLASH_1_1_2_READ = 0x3b }; /* register Offset */ |