diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2021-10-25 11:23:54 +0530 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-10-25 17:14:35 +0000 |
| commit | ac1bba8e34ea7b2c9112b19c4d7e63e74949a899 (patch) | |
| tree | d4e1dfef6e305930f6ff2dc9a79b027207e0fd5f /src/soc | |
| parent | 66b2f2015688033a0d46d8fcc5d3f08aea1fb8b2 (diff) | |
soc/intel/common: Skip CSE post hook when CSE is disabled
This patch fixes regression introduced by commit bee4bb5f0
(soc/intel/common/cse: Late sending EOP msg if !HECI_DISABLE_USING_SMM)
FAFT test case fail when doing `firmware_DevMode` test.
If CSE is already hidden then accessing CSE registers would be wrong
and will receive junk, hence, return as CSE is already disabled.
BUG=b:203061531
TEST=Brya system can boot to OS with recovery mode.
Change-Id: I2046eb19716c397a066c2c41e1b027a256bd6cf9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/common/block/cse/cse_eop.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index 1f544694b6..e47eb510fb 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -175,6 +175,15 @@ static void handle_cse_eop_result(enum cse_eop_result result) static void set_cse_end_of_post(void *unused) { + /* + * If CSE is already hidden then accessing CSE registers would be wrong and will + * receive junk, hence, return as CSE is already disabled. + */ + if (!is_cse_enabled()) { + printk(BIOS_DEBUG, "CSE is disabled, cannot send End-of-Post (EOP) message\n"); + return; + } + set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE); timestamp_add_now(TS_ME_BEFORE_END_OF_POST); |