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authorzhaojohn <john.zhao@intel.com>2022-09-20 08:12:47 -0700
committerSubrata Banik <subratabanik@google.com>2022-11-17 06:32:47 +0000
commit9f5fea993ab0a9b9d59c00132c6ee58630b2481f (patch)
tree368b5f65cbf81fd4050d0ac38fabcb14320e34d9 /src/soc
parent992883ad0ca6732b96dfb6411ac2fbbc517da803 (diff)
soc/intel/meteorlake: Enable FSP multiphase
This patch changes the UPD EnableMultiPhaseSiliconInit to enable the Meteor Lake FSP multiphase flow. BUG=b:247670186 TEST=Able to build and boot Google, Rex with MultiPhaseSiInit Enable. [SPEW ] Executing Phase 1 of FspMultiPhaseSiInit [DEBUG] FSP MultiPhaseSiInit src/soc/intel/meteorlake/ fsp_params.c/platform_fsp_multi_phase_init_cb called [DEBUG] port C0 DISC req: usage 1 usb3 1 usb2 2 [DEBUG] Raw Buffer output 0 00000211 [DEBUG] Raw Buffer output 1 00000000 [DEBUG] pmc_send_ipc_cmd succeeded [DEBUG] port C1 DISC req: usage 1 usb3 3 usb2 4 [DEBUG] Raw Buffer output 0 00000431 [DEBUG] Raw Buffer output 1 00000000 [DEBUG] pmc_send_ipc_cmd succeeded Change-Id: I759c0ecee29c07bae4abe6b56d015e7253bd49fe Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67741 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/meteorlake/fsp_params.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c
index 4fe2f63ddf..4429dc0bf1 100644
--- a/src/soc/intel/meteorlake/fsp_params.c
+++ b/src/soc/intel/meteorlake/fsp_params.c
@@ -394,10 +394,10 @@ static void fill_fsps_ai_params(FSP_S_CONFIG *s_cfg,
static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg)
{
- /* UPDATEME: Disable for VP
+ /*
* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit
*/
- s_arch_cfg->EnableMultiPhaseSiliconInit = 0;
+ s_arch_cfg->EnableMultiPhaseSiliconInit = 1;
/* Assign FspEventHandler arch Upd to use coreboot debug event handler */
if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(CONSOLE_SERIAL) &&