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authorKrishna Prasad Bhat <krishna.p.bhat.d@intel.com>2021-12-02 10:30:26 +0530
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-12-03 21:48:39 +0000
commit9eb7070bc46c8ce38f3356ec60562c66b576e274 (patch)
tree41d530e4b5fecf18b95b7299cab091d21973673f /src/soc
parent333edcc7c60bee7412773c33a715b83063b4eb25 (diff)
soc/intel/adl: Add override skip_cse_sub_part_update() for alderlake
Check the Alderlake CPU ID to determine if cse sub-paritition update is required or not. BUG=b:202143532 Change-Id: Icae21dad56ed4a1edea1f641b3d5bccc3943f831 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/alderlake/romstage/romstage.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index d33d21f1aa..b9d08c8386 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -15,6 +15,7 @@
#include <soc/pm.h>
#include <soc/romstage.h>
#include <soc/soc_chip.h>
+#include <cpu/intel/cpu_ids.h>
#include <string.h>
#define FSP_SMBIOS_MEMORY_INFO_GUID \
@@ -23,6 +24,11 @@
0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \
}
+bool skip_cse_sub_part_update(void)
+{
+ return cpu_get_cpuid() != CPUID_ALDERLAKE_A2;
+}
+
/* Save the DIMM information for SMBIOS table 17 */
static void save_dimm_info(void)
{