diff options
| author | Michał Kopeć <michal.kopec@3mdeb.com> | 2022-10-29 18:00:18 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-06 15:18:45 +0000 |
| commit | 9c4ae9131ce5f391c97f9ce4f78fce0e1697d9b1 (patch) | |
| tree | 7562fe384912f0cd7a019d101279ae480865341a /src/soc | |
| parent | 34a7e66faa46ec3ddf3d2346b00c91e3c0547012 (diff) | |
soc/intel/alderlake: make SOC_INTEL_CSE_SEND_EOP_EARLY per-board configurable
SOC_INTEL_CSE_SEND_EOP_EARLY breaks soft ME disable, which works using
a HECI message that needs to be sent before EOP. Make the option
configurable to allow soft ME disable on alderlake.
Change-Id: I7febf7c029e7eac94052cc3a8142949d6813c1bc
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cse/Kconfig | 2 |
2 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 08d4132f61..5b624d8ae1 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -117,7 +117,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET - select SOC_INTEL_CSE_SEND_EOP_EARLY select SOC_INTEL_CSE_SET_EOP select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select HAVE_INTEL_COMPLIANCE_TEST_MODE @@ -459,6 +458,9 @@ config USE_COREBOOT_MP_INIT endchoice +config SOC_INTEL_CSE_SEND_EOP_EARLY + default y + if STITCH_ME_BIN config CSE_BPDT_VERSION diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 2962a1472e..82022b190b 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -46,7 +46,7 @@ config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR to make `HECI1` device disable using private configuration register (PCR) write. config SOC_INTEL_CSE_SEND_EOP_EARLY - bool + bool "CSE send EOP early" depends on SOC_INTEL_COMMON_BLOCK_CSE help Use this config to send End Of Post (EOP) earlier through SoC code in order to |