soc/amd/cezanne/chip: use common data fabric domain resource code

Use the new common AMD code that gets the usable non-fixed MMIO windows
from the data fabric MMIO decode registers and generate the PCI0 _CRS
ACPI code based on those regions. For a more detailed description see
the corresponding patch that changes the Picasso code to use this new
code. In contrast to the Picasso code, this change will drop the
unneeded _STA method inside the PCI0 scope which wasn't present in
Picasso's ACPI code before it got replaced by the SSDT that gets
generated by amd_pci_domain_fill_ssdt.

TEST=None

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7b14ee0682ae1f2212ab43977c076687706434ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75557
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

4 files changed, 4 insertions, 63 deletions

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 2975dda48e..e96169b9cc 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -41,6 +41,7 @@ config SOC_AMD_CEZANNE
 	select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
 	select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
 	select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
+	select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN
 	select SOC_AMD_COMMON_BLOCK_EMMC
 	select SOC_AMD_COMMON_BLOCK_GRAPHICS
 	select SOC_AMD_COMMON_BLOCK_HAS_ESPI
diff --git a/src/soc/amd/cezanne/acpi/pci0.asl b/src/soc/amd/cezanne/acpi/pci0.asl
index fb02a02c3b..c778578823 100644
--- a/src/soc/amd/cezanne/acpi/pci0.asl
+++ b/src/soc/amd/cezanne/acpi/pci0.asl
@@ -3,15 +3,6 @@
 Device(PCI0) {
 	Name(_HID, EISAID("PNP0A08"))	/* PCI Express Root Bridge */
 	Name(_CID, EISAID("PNP0A03"))	/* PCI Root Bridge */
-	External(TOM1, IntObj)		/* Generated by root_complex.c */
-
-	Method(_BBN, 0, NotSerialized) {
-		Return(0) /* Bus number = 0 */
-	}
-
-	Method(_STA, 0, NotSerialized) {
-		Return(0x0f)	/* Status is visible */
-	}
 
 	/* Operating System Capabilities Method */
 	Method(_OSC, 4) {
@@ -26,57 +17,6 @@ Device(PCI0) {
 			Return (Arg3)
 		}
 	}
-	Name(CRES, ResourceTemplate() {
-		WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
-			0x0000,		/* address granularity */
-			0x0000,		/* range minimum */
-			0x00ff,		/* range maximum */
-			0x0000,		/* translation */
-			0x0100,		/* length */
-			,, PSB0)	/* ResourceSourceIndex, ResourceSource, DescriptorName */
-
-		IO(Decode16, 0x0cf8, 0x0cf8, 1,	8)
-
-		WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-			0x0000,		/* address granularity */
-			0x0000,		/* range minimum */
-			0x0cf7,		/* range maximum */
-			0x0000,		/* translation */
-			0x0cf8		/* length */
-		)
-
-		WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-			0x0000,		/* address granularity */
-			0x0d00,		/* range minimum */
-			0xffff,		/* range maximum */
-			0x0000,		/* translation */
-			0xf300		/* length */
-		)
-
-		Memory32Fixed(READONLY, 0x000a0000, 0x00020000, VGAM)	/* VGA memory space */
-		Memory32Fixed(READONLY, 0x000c0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
-
-		/* memory space for PCI BARs below 4GB */
-		Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
-	})
-
-	Method(_CRS, 0) {
-		CreateDWordField(CRES, ^MMIO._BAS, MM1B)
-		CreateDWordField(CRES, ^MMIO._LEN, MM1L)
-
-		/* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */
-		MM1B = TOM1
-		Local0 = CONFIG_ECAM_MMCONF_BASE_ADDRESS
-		Local0 -= TOM1
-		MM1L = Local0
-
-		CreateWordField(CRES, ^PSB0._MAX, BMAX)
-		CreateWordField(CRES, ^PSB0._LEN, BLEN)
-		BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1
-		BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER
-
-		Return(CRES) /* note to change the Name buffer */
-	} /* end of Method(_SB.PCI0._CRS) */
 
 	/* 0:14.3 - LPC */
 	#include <soc/amd/common/acpi/lpc.asl>
diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c
index d480cc563b..9fd687b56b 100644
--- a/src/soc/amd/cezanne/chip.c
+++ b/src/soc/amd/cezanne/chip.c
@@ -26,10 +26,11 @@ static const char *soc_acpi_name(const struct device *dev)
 };
 
 struct device_operations cezanne_pci_domain_ops = {
-	.read_resources	= pci_domain_read_resources,
+	.read_resources	= amd_pci_domain_read_resources,
 	.set_resources	= pci_domain_set_resources,
-	.scan_bus	= pci_domain_scan_bus,
+	.scan_bus	= amd_pci_domain_scan_bus,
 	.acpi_name	= soc_acpi_name,
+	.acpi_fill_ssdt	= amd_pci_domain_fill_ssdt,
 };
 
 static void soc_init(void *chip_info)
diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c
index a4134ef699..cb35662af7 100644
--- a/src/soc/amd/cezanne/root_complex.c
+++ b/src/soc/amd/cezanne/root_complex.c
@@ -190,7 +190,6 @@ static void acipgen_dptci(void)
 
 static void root_complex_fill_ssdt(const struct device *device)
 {
-	acpi_fill_root_complex_tom(device);
 	if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC))
 		acipgen_dptci();
 }