diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-04-26 22:22:38 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-04-28 20:14:02 +0000 |
| commit | 932cd22487e248306e43a5742176258eabdfc314 (patch) | |
| tree | 175b5a7ab0b8d8909ea6d29db5d776082267c398 /src/soc | |
| parent | 0de53be394deefe093b79c3b85f453023173fa98 (diff) | |
soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct PCI MMIO BAR window
This ports back commit d75ee46d3ce6 ("soc/amd/picasso/acpi: Change PCI0
BAR window") to Stoneyridge so that the correct end of the non-fixed
MMIO region gets reported in PCI0's _CRS method.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I19153947cbb1b1b684291765eb1902caac65b9ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl | 11 |
1 files changed, 2 insertions, 9 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index dad8aaa2cf..a4903e9b60 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -98,16 +98,9 @@ Method(_CRS, 0) { CreateDWordField(CRES, ^MMIO._BAS, MM1B) CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ + /* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */ MM1B = TOM1 - Local0 = 0x10000000 << 4 + Local0 = CONFIG_ECAM_MMCONF_BASE_ADDRESS Local0 -= TOM1 MM1L = Local0 |