rockchip: rk3399: add gpio driver

Reuse the common gpio driver and implement some stubs
in gpio.h.

RK3288 has one pmu gpio while RK3399 have two.

Please refer to TRM V0.3 Part2 Chapter 11 for GPIO section.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=emerge-kevin coreboot

Change-Id: I041865ce269b0ae1f6a07e6c37d53d565a37c5ef
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d416ba0ce6a1ff2cf52f6b83ade601d93b40ffeb
Original-Change-Id: I1d213a91ea508997b876441250743671204d7c53
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/332560
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14713
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

2 files changed, 51 insertions, 0 deletions

diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc
index bdd9d3eb26..bd6200f30a 100644
--- a/src/soc/rockchip/rk3399/Makefile.inc
+++ b/src/soc/rockchip/rk3399/Makefile.inc
@@ -51,6 +51,8 @@ ramstage-y += sdram.c
 ramstage-y += ../common/spi.c
 ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
 ramstage-y += clock.c
+ramstage-y += ../common/gpio.c
+ramstage-y += gpio.c
 ramstage-y += ../common/i2c.c
 ramstage-y += soc.c
 ramstage-y += timer.c
diff --git a/src/soc/rockchip/rk3399/gpio.c b/src/soc/rockchip/rk3399/gpio.c
new file mode 100644
index 0000000000..18e0b70931
--- /dev/null
+++ b/src/soc/rockchip/rk3399/gpio.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <gpio.h>
+#include <soc/addressmap.h>
+#include <soc/gpio.h>
+#include <soc/grf.h>
+#include <soc/soc.h>
+#include <stdlib.h>
+
+struct rockchip_gpio_regs *gpio_port[] = {
+	(struct rockchip_gpio_regs *)GPIO0_BASE,
+	(struct rockchip_gpio_regs *)GPIO1_BASE,
+	(struct rockchip_gpio_regs *)GPIO2_BASE,
+	(struct rockchip_gpio_regs *)GPIO3_BASE,
+	(struct rockchip_gpio_regs *)GPIO4_BASE,
+};
+
+#define PMU_GPIO_PORT0 0
+#define PMU_GPIO_PORT1 1
+
+int is_pmu_gpio(gpio_t gpio)
+{
+	if (gpio.port == PMU_GPIO_PORT0 || gpio.port == PMU_GPIO_PORT1)
+		return 1;
+	return 0;
+}
+
+void *gpio_grf_reg(gpio_t gpio)
+{
+	if (is_pmu_gpio(gpio))
+		return &rk3399_pmugrf->gpio0_p[gpio.port][gpio.bank];
+	/* There are two pmu gpio, 0 and 1, so " - 2" */
+	return &rk3399_grf->gpio2_p[(gpio.port - 2)][gpio.bank];
+}