diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-06-01 22:01:40 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-07 18:53:57 +0000 |
| commit | 90044bd6d14e1a11a056db34e38ab4f150351990 (patch) | |
| tree | 61100faeb85d063cb8c41261890bb5ef9627c19c /src/soc | |
| parent | 15aa0a56ce751f7c36402fe74b6bc3c636c26307 (diff) | |
soc/amd/cezanne/acpi: use ROOT_BRIDGE macro
Use the ROOT_BRIDGE macro in soc.asl to replace the pci0.asl file. The
soc/amd/common/acpi/lpc.asl file which was included in the now removed
pci0.asl file now gets included in the correct scope in the soc.asl
file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia8f0f1619a71f4ab2051714a9d8c7eb200845390
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75592
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/cezanne/acpi/pci0.asl | 24 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/acpi/soc.asl | 7 |
2 files changed, 6 insertions, 25 deletions
diff --git a/src/soc/amd/cezanne/acpi/pci0.asl b/src/soc/amd/cezanne/acpi/pci0.asl deleted file mode 100644 index c778578823..0000000000 --- a/src/soc/amd/cezanne/acpi/pci0.asl +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Device(PCI0) { - Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ - Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ - - /* Operating System Capabilities Method */ - Method(_OSC, 4) { - CreateDWordField(Arg3, 0, CDW1) /* Capabilities dword 1 */ - - /* Check for proper PCI/PCIe UUID */ - If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { - /* Let OS control everything */ - Return (Arg3) - } Else { - CDW1 |= 4 /* Unrecognized UUID */ - Return (Arg3) - } - } - - /* 0:14.3 - LPC */ - #include <soc/amd/common/acpi/lpc.asl> - -} /* End PCI0 scope */ diff --git a/src/soc/amd/cezanne/acpi/soc.asl b/src/soc/amd/cezanne/acpi/soc.asl index f8f7a8a7a8..4ab03d0f36 100644 --- a/src/soc/amd/cezanne/acpi/soc.asl +++ b/src/soc/amd/cezanne/acpi/soc.asl @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <soc/amd/common/acpi/pci_root.asl> #include "globalnvs.asl" Scope(\_SB) { @@ -16,7 +17,11 @@ Scope(\_SB) { #include "mmio.asl" - #include "pci0.asl" + ROOT_BRIDGE(PCI0) + + Scope(PCI0) { + #include <soc/amd/common/acpi/lpc.asl> + } /* End PCI0 scope */ } /* End \_SB scope */ #include <soc/amd/common/acpi/alib.asl> |