diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-01-03 19:17:34 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-25 16:12:33 +0000 |
| commit | 7f8ab005ca20bdd70368de1c4f4dcfea5a42ff86 (patch) | |
| tree | a9593eb1efb597c2d82a705ab0e7a89e6ac9182c /src/soc | |
| parent | ff99f1246fb427edbd2741a05ba3155c3ba7b3c4 (diff) | |
soc/intel/adl: Replace dt `HeciEnabled` by `HECI1 disable` config
Since Tiger Lake platform, the HECI1 device can be disabled on
Alder Lake platform using two different mechanism:
A. Using PMC IPC command 0xA9.
B. Sending SBI message under SMM.
In current scope of Alder Lake the default implementation is using
(B) sending sbi message under SMM. A follow up patch to add the
possible options and let platform to choose the applicable one.
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
3. Default enable HECI1 device in `chipset.cb` to ensure the HECI1
device can undergo the PCI enumeration and later based on the
mainboard policy the HECI1 device can be disabled.
Mainboards that choose to make HECI1 enable during boot don't override
`DISABLE_HECI1_AT_PRE_BOOT` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie673e634fbc0bdece419c379d417b08dfb4819e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/alderlake/chip.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/chipset.cb | 2 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/smihandler.c | 7 |
3 files changed, 4 insertions, 9 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index e997e78541..a5543d6364 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -314,10 +314,6 @@ struct soc_intel_alderlake_config { } IgdDvmt50PreAlloc; uint8_t SkipExtGfxScan; - /* HeciEnabled decides the state of Heci1 at end of boot - * Setting to 0 (default) disables Heci1 and hides the device from OS */ - uint8_t HeciEnabled; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 7de8f09ab1..09dc970298 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -175,7 +175,7 @@ chip soc/intel/alderlake device pci 15.1 alias i2c1 off end device pci 15.2 alias i2c2 off end device pci 15.3 alias i2c3 off end - device pci 16.0 alias heci1 off end + device pci 16.0 alias heci1 on end device pci 16.1 alias heci2 off end device pci 16.2 alias ide_r off end device pci 16.3 alias kt off end diff --git a/src/soc/intel/alderlake/smihandler.c b/src/soc/intel/alderlake/smihandler.c index 5b53038834..d9ea96a3da 100644 --- a/src/soc/intel/alderlake/smihandler.c +++ b/src/soc/intel/alderlake/smihandler.c @@ -16,11 +16,10 @@ */ void smihandler_soc_at_finalize(void) { - const struct soc_intel_alderlake_config *config; + if (!CONFIG(HECI_DISABLE_USING_SMM)) + return; - config = config_of_soc(); - - if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) + if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) heci_disable(); } |