diff options
| author | Subrata Banik <subratabanik@google.com> | 2023-11-09 14:42:04 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-12-11 05:09:38 +0000 |
| commit | 7ae510093c97ffbc7886503c7d6b839e9ee3b9ce (patch) | |
| tree | f9d16d3dfafb49ec2ed962c2da1a271ded10afe8 /src/soc | |
| parent | 79c09ba3b6a16aebc72a528fd82d70cd8b2fec41 (diff) | |
soc/intel/meteorlake: Add entries to eventLog on invocation of early SOL
This patch records early signs of user activity during CSE firmware
synchronization or MRC (re)training events in the event
log (ELOG_TYPE_FW_EARLY_SOL).
These can be used to ensure persistence across global reset (e.g. after
CSE sync) so that they can be later retrieved in order to build things
such as test automation ensuring that we went through the SOL
path/display initialized.
BUG=b:279173035
TEST=Verified on google/rex, event shows in eventlog after CSE sync
and/or MRC.
Scenario #1: While performing MRC update
1 | 2023-11-08 | Early Sign of Life | MRC Early SOL Screen Shown
2 | 2023-11-08 | Memory Cache Update | Normal | Success
3 | 2023-11-08 | System boot | 9
4 | 2023-11-08 | ACPI Wake | S5
Scenario #2: While performing CSE update/downgrade
11 | 2023-11-08 | Early Sign of Life | CSE Sync Early SOL Screen Shown
12 | 2023-11-08 | System boot | 13
Scenario #2: While performing both MRC and CSE upgrade
16 | 2023-11-08 | Early Sign of Life | MRC Early SOL Screen Shown
17 | 2023-11-08 | Early Sign of Life | CSE Sync Early SOL Screen Shown
18 | 2023-11-08 | Memory Cache Update | Normal | Success
19 | 2023-11-08 | System boot | 16
20 | 2023-11-08 | ACPI Wake | S5
Change-Id: Idfa6f216194fd311bb1a57dd7c86fe7446a3597c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78983
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/meteorlake/romstage/fsp_params.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 704cb54dbf..a45f23f46b 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -9,6 +9,7 @@ #include <device/device.h> #include <device/pci.h> #include <drivers/wifi/generic/wifi.h> +#include <elog.h> #include <fsp/fsp_debug_event.h> #include <fsp/util.h> #include <intelbasecode/ramtop.h> @@ -435,14 +436,19 @@ static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg, void *vbt; size_t vbt_size; uint32_t vga_init_control = 0; + uint8_t sol_type; /* Memory training. */ - if (!arch_upd->NvsBufferPtr) + if (!arch_upd->NvsBufferPtr) { vga_init_control = VGA_INIT_CONTROL_ENABLE | VGA_INIT_CONTROL_TEAR_DOWN; + sol_type = ELOG_FW_EARLY_SOL_MRC; + } - if (is_cse_fw_update_required()) + if (is_cse_fw_update_required()) { vga_init_control = VGA_INIT_CONTROL_ENABLE; + sol_type = ELOG_FW_EARLY_SOL_CSE_SYNC; + } if (!vga_init_control) return; @@ -461,6 +467,7 @@ static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg, } printk(BIOS_INFO, "Enabling FSP-M Sign-of-Life\n"); + elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, sol_type); m_cfg->VgaInitControl = vga_init_control; m_cfg->VbtPtr = (UINT32)vbt; |