diff options
| author | Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> | 2023-09-22 00:38:53 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-10-04 05:48:15 +0000 |
| commit | 7542fa19a969dcd13a1fd23d23f91ad7898e5f65 (patch) | |
| tree | 785a96817f89843e6c1fa3d3da6696d224f2523c /src/soc | |
| parent | 4f062ec34b6e344e88ceaf7460675a860f10a2b6 (diff) | |
soc/intel/mtl: Call cse_fill_bp_info early in romstage
Intel Platform Service Record(PSR) will be enabled on Meteor Lake
platforms. cse_fw_sync actions happen in ramstage when PSR is enabled.
To avoid the boot time penalty of sending the cse_get_bp_info in
ramstage, call cse_fill_bp_info to get cse_bp_info response early in
romstage and store in cbmem. This data can be later used in ramstage.
BUG=b:273207144
TEST=Verify cse_bp_info is filled in romstage in rex.
Change-Id: Ic0e8fb34f21ff07e182a7b848d38e9d329010028
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/meteorlake/romstage/romstage.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c index 3df480c3f5..1f1cfd6138 100644 --- a/src/soc/intel/meteorlake/romstage/romstage.c +++ b/src/soc/intel/meteorlake/romstage/romstage.c @@ -129,8 +129,11 @@ void mainboard_romstage_entry(void) /* Initialize HECI interface */ cse_init(HECI1_BASE_ADDRESS); - if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU)) - cse_fw_sync(); + if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU)) { + cse_fill_bp_info(); + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE)) + cse_fw_sync(); + } /* Update coreboot timestamp table with CSE timestamps */ if (CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY)) |