drivers/uart: Use uart_platform_refclk for all UART models

Allow the platform to override the input clock for the UART by
implementing the routine uart_platform_refclk and setting the Kconfig
value UART_OVERRIDE_REFCLK.  Provide a default uart_platform_refclk
routine which is disabled when UART_OVERRIDE_REFCLK is selected.  This
works around ROMCC not supporting weak routines.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file:
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
   CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
   UEFIPAYLOAD.fd
*  Testing is successful when CorebootPayloadPkg is able to properly
   initialize the serial port without using built-in values.

Change-Id: If4afc45a828e5ba935fecb6d95b239625e912d14
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14612
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

8 files changed, 6 insertions, 17 deletions

diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig
index 5ea6b95107..da33cc5c96 100644
--- a/src/soc/imgtec/pistachio/Kconfig
+++ b/src/soc/imgtec/pistachio/Kconfig
@@ -25,6 +25,7 @@ config CPU_IMGTEC_PISTACHIO
 	select SPI_ATOMIC_SEQUENCING
 	select GENERIC_GPIO_LIB
 	select HAVE_HARD_RESET
+	select UART_OVERRIDE_REFCLK
 	bool
 
 if CPU_IMGTEC_PISTACHIO
diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c
index e8dfeda565..0e530609bd 100644
--- a/src/soc/intel/apollolake/uart_early.c
+++ b/src/soc/intel/apollolake/uart_early.c
@@ -68,12 +68,6 @@ uintptr_t uart_platform_base(int idx)
 	return (CONFIG_CONSOLE_UART_BASE_ADDRESS);
 }
 
-unsigned int uart_platform_refclk(void)
-{
-	/* That's within 0.5% of the actual value we've set earlier */
-	return 115200 * 16;
-}
-
 static const struct pad_config uart_gpios[] = {
 	PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1),		/* UART1 RX */
 	PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1),		/* UART1 TX */
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index ae25c328c6..6a2349fb8d 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -30,6 +30,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON
 	select SOC_SETS_MTRRS
 	select TSC_CONSTANT_RATE
+	select UART_OVERRIDE_REFCLK
 	select UDELAY_TSC
 	select UNCOMPRESSED_RAMSTAGE
 	select USE_MARCH_586
diff --git a/src/soc/intel/skylake/uart_debug.c b/src/soc/intel/skylake/uart_debug.c
index c463bea145..f3d576b3aa 100644
--- a/src/soc/intel/skylake/uart_debug.c
+++ b/src/soc/intel/skylake/uart_debug.c
@@ -18,17 +18,6 @@
 #include <soc/iomap.h>
 #include <soc/serialio.h>
 
-unsigned int uart_platform_refclk(void)
-{
-	/*
-	 * Set M and N divisor inputs and enable clock.
-	 * Main reference frequency to UART is:
-	 *  120MHz * M / N = 120MHz * 48 / 3125 = 1843200Hz
-	 * The different order below is to handle integer math overflow.
-	 */
-	return 120 * MHz / SIO_REG_PPR_CLOCK_N_DIV * SIO_REG_PPR_CLOCK_M_DIV;
-}
-
 uintptr_t uart_platform_base(int idx)
 {
 	/* Same base address for all debug port usage. In reality UART2
diff --git a/src/soc/marvell/armada38x/Kconfig b/src/soc/marvell/armada38x/Kconfig
index 6754a0f1f6..ed8cbe8100 100644
--- a/src/soc/marvell/armada38x/Kconfig
+++ b/src/soc/marvell/armada38x/Kconfig
@@ -10,6 +10,7 @@ config SOC_MARVELL_ARMADA38X
 	select RETURN_FROM_VERSTAGE
 	select BOOTBLOCK_CUSTOM
 	select GENERIC_UDELAY
+	select UART_OVERRIDE_REFCLK
 
 if SOC_MARVELL_ARMADA38X
 
diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig
index 502e7c4c72..08ed47567b 100644
--- a/src/soc/nvidia/tegra132/Kconfig
+++ b/src/soc/nvidia/tegra132/Kconfig
@@ -13,6 +13,7 @@ config SOC_NVIDIA_TEGRA132
 	select HAVE_HARD_RESET
 	select HAVE_UART_SPECIAL
 	select GENERIC_GPIO_LIB
+	select UART_OVERRIDE_REFCLK
 
 if SOC_NVIDIA_TEGRA132
 
diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig
index 8b15d3dc45..0f394b18b4 100644
--- a/src/soc/rockchip/rk3288/Kconfig
+++ b/src/soc/rockchip/rk3288/Kconfig
@@ -27,6 +27,7 @@ config SOC_ROCKCHIP_RK3288
 	select UNCOMPRESSED_RAMSTAGE
 	select GENERIC_GPIO_LIB
 	select RTC
+	select UART_OVERRIDE_REFCLK
 
 if SOC_ROCKCHIP_RK3288
 
diff --git a/src/soc/rockchip/rk3399/Kconfig b/src/soc/rockchip/rk3399/Kconfig
index 43bb03bd4e..38d0f00413 100644
--- a/src/soc/rockchip/rk3399/Kconfig
+++ b/src/soc/rockchip/rk3399/Kconfig
@@ -12,6 +12,7 @@ config SOC_ROCKCHIP_RK3399
 	select GENERIC_UDELAY
 	select HAVE_MONOTONIC_TIMER
 	select UNCOMPRESSED_RAMSTAGE
+	select UART_OVERRIDE_REFCLK
 
 if SOC_ROCKCHIP_RK3399