diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2019-03-28 10:07:15 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-03-29 02:33:14 +0000 |
| commit | 6a9d2f989975a63f569750113aa3b88255fb2bea (patch) | |
| tree | 528a3736927059fd38a0bf21c059db5496e60852 /src/soc | |
| parent | 0f57a2bb9779647905c00fc46f5b5eddc8ee3c5b (diff) | |
soc/intel/icelake: Fix chipset_power_state structure
This patch ports CB:30717 changes from CNL to ICL.
This structure is declared as a static CAR_GLOBAL in the common
PMC library code and in the SOC specific code. Remove the SOC
specific version and instead get the chipset_power_state pointer
from the PMC library.
This fixes events that were recorded in chipset_power_state at
boot but were reading as all zero when it was time to parse the
structure when logging events to flash.
Change-Id: I1152d0e882e1acf475072d1553b74f9161e2f485
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32095
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/icelake/romstage/romstage.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 92fb1e4647..a61370a1ee 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -31,8 +31,6 @@ #include <string.h> #include <timestamp.h> -static struct chipset_power_state power_state; - #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ @@ -111,7 +109,7 @@ asmlinkage void car_stage_entry(void) bool s3wake; struct postcar_frame pcf; uintptr_t top_of_ram; - struct chipset_power_state *ps = &power_state; + struct chipset_power_state *ps = pmc_get_power_state(); console_init(); |