diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-12-06 13:55:01 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-12-10 07:59:57 +0000 |
| commit | 64dd9d000e369761e2da9d7b53e60c3296bd1890 (patch) | |
| tree | c72da2b394502203e35ec65f4a4c54bd94cdfd93 /src/soc | |
| parent | 3eac04982abb17dbd69e2303183cc2603df09630 (diff) | |
soc/intel/meteorlake: Skip duplicate PCIe RP CLKSRC programming
When an enabled root port without pcie_rp clock being specified, the
empty structure provides invalid info, which indicates '0' is the
clock source and request. If a root port does not use clock source, it
should still need to provide pcie_rp clock structure with flags set to
PCIE_RP_CLK_SRC_UNUSED. If flags, clk_src, and clk_req are all '0', it
is considered that pcie_rp clock structure is not provided for that
root port.
Add check and skip PCIe CLKSRC programming without a clock structure.
In addition, a root port can not use a free running clock or clock set
to LAN.
Note that ClockUsage is either free running clock, LAN clock, or the
root port number which consumes the clock.
This patch is backported from
commit edf71a08b4cb7bd8683344aa4ad301f1526289c2 (soc/intel/alderlake:
Skip PCIe source clock assignment if incorrect)
Change-Id: Ie9179880a57796d8595874325203280590d7ee9d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70415
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/meteorlake/romstage/fsp_params.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 89f6aaf191..7453eb0222 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -35,9 +35,10 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, continue; if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED) continue; - /* flags 0 means, RP config is not specify from devicetree */ - if (cfg[i].flags == 0) + if (!cfg[i].flags && cfg[i].clk_src == 0 && cfg[i].clk_req == 0) { + printk(BIOS_WARNING, "Missing root port clock structure definition\n"); continue; + } if (clk_req_mapping & (1 << cfg[i].clk_req)) printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n" , cfg[i].clk_req); |