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authorJeremy Compostella <jeremy.compostella@intel.com>2024-02-01 14:30:48 -0800
committerFelix Held <felix-coreboot@felixheld.de>2024-02-05 14:07:08 +0000
commit63d5fc61349b923ffa51502804792d27833c3b64 (patch)
tree42adfb986f3f43172dce36dd75a7fe40181b19c0 /src/soc
parentb1c50be5665c876ba0302dfcd3e1a420a008bbba (diff)
soc/intel/xeon_sp/bootblock: Fix out of order header files
Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec96 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80301 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/xeon_sp/bootblock.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c
index cc839efc57..62ca48f7c2 100644
--- a/src/soc/intel/xeon_sp/bootblock.c
+++ b/src/soc/intel/xeon_sp/bootblock.c
@@ -1,18 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <bootblock_common.h>
+#include <console/console.h>
+#include <cpu/x86/mtrr.h>
#include <device/pci.h>
+#include <fsp/util.h>
#include <FsptUpd.h>
#include <intelblocks/fast_spi.h>
-#include <intelblocks/tco.h>
-#include <soc/iomap.h>
-#include <console/console.h>
-#include <cpu/x86/mtrr.h>
#include <intelblocks/lpc_lib.h>
+#include <intelblocks/tco.h>
#include <security/intel/cbnt/cbnt.h>
-#include <soc/pci_devs.h>
#include <soc/bootblock.h>
-#include <fsp/util.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
const FSPT_UPD temp_ram_init_params = {
.FspUpdHeader = {