tegra132: implement platform_prog_run()

The tegra132 SoC is currently booting up on the AVP cpu which
bootstraps the rest of the SoC. Upon exiting romstage it
runs ramstage from its faster armv8 core. Instead of hard
coding the stage loading operations use run_ramstage().

Change-Id: Ib9b3eecf376ae022f910295920a085bde6e17f9f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8848
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

1 files changed, 7 insertions, 30 deletions

diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c
index 9051a81e6f..94fd845e65 100644
--- a/src/soc/nvidia/tegra132/romstage.c
+++ b/src/soc/nvidia/tegra132/romstage.c
@@ -24,6 +24,7 @@
 #include <console/console.h>
 #include <timer.h>
 #include <arch/exception.h>
+#include <program_loading.h>
 
 #include <soc/addressmap.h>
 #include <soc/sdram_configs.h>
@@ -38,30 +39,8 @@ void __attribute__((weak)) romstage_mainboard_init(void)
 	/* Default empty implementation. */
 }
 
-static void *load_ramstage(void)
-{
-	void *entry;
-	struct stopwatch sw;
-
-	stopwatch_init(&sw);
-	/*
-	 * This platform does not need to cache a loaded ramstage nor do we
-	 * go down this path on resume. Therefore, no romstage_handoff is
-	 * required.
-	 */
-	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
-				CONFIG_CBFS_PREFIX "/ramstage");
-
-	printk(BIOS_DEBUG, "Ramstage load time: %ld usecs.\n",
-		stopwatch_duration_usecs(&sw));
-
-	return entry;
-}
-
 void romstage(void)
 {
-	void *entry;
-
 	console_init();
 	exception_init();
 
@@ -99,16 +78,14 @@ void romstage(void)
 
 	romstage_mainboard_init();
 
-	entry = load_ramstage();
-
-	if (entry == NULL) {
-		printk(BIOS_INFO, "T132 romstage: error loading ramstage\n");
-		clock_halt_avp();
-	}
-
 	cbmemc_reinit();
 
-	ccplex_cpu_start(entry);
+	run_ramstage();
+}
+
+void platform_prog_run(struct prog *prog)
+{
+	ccplex_cpu_start(prog_entry(prog));
 
 	clock_halt_avp();
 }