soc/intel/{apl,cnl}: Remove FSP CAR option

One of the reason FSP-T support had to be kept in place was for
Intel Bootguard. This now works with native CAR code, so there is no
reason to keep FSP-T as an option for these platforms.

APL did not even build with FSP_CAR and finding FSP-T using walkcbfs
was only recently fixed using FMAP, so there can be no doubt that this
option was never used with coreboot master.

Change-Id: I0d5844b5a6fd291a13e5f467f4fc682b17eafa63
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

5 files changed, 5 insertions, 126 deletions

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 45414a4c88..0505de9865 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -1,5 +1,6 @@
 config SOC_INTEL_APOLLOLAKE
 	bool
+	select INTEL_CAR_CQOS
 	help
 	  Intel Apollolake support
 
@@ -13,6 +14,7 @@ config SOC_INTEL_GEMINILAKE
 	select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
 	select IDT_IN_EVERY_STAGE
 	select PAGING_IN_CACHE_AS_RAM
+	select INTEL_CAR_NEM
 	help
 	  Intel GLK support
 
@@ -60,6 +62,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK
 	select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
 	select SOC_INTEL_COMMON_BLOCK_ACPI
+	select SOC_INTEL_COMMON_BLOCK_CAR
 	select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
 	select SOC_INTEL_COMMON_BLOCK_CPU
 	select SOC_INTEL_COMMON_BLOCK_DSP
@@ -295,40 +298,6 @@ config NHLT_RT5682
 	default n
 	help
 	  Include DSP firmware settings for headset codec.
-
-choice
-	prompt "Cache-as-ram implementation"
-	default CAR_CQOS if !SOC_INTEL_GEMINILAKE
-	default CAR_NEM
-	help
-	  This option allows you to select how cache-as-ram (CAR) is set up.
-
-config CAR_NEM
-	bool "Non-evict mode"
-	select SOC_INTEL_COMMON_BLOCK_CAR
-	select INTEL_CAR_NEM
-	help
-	  Traditionally, CAR is set up by using Non-Evict mode. This method
-	  does not allow CAR and cache to co-exist, because cache fills are
-	  block in NEM mode.
-
-config CAR_CQOS
-	bool "Cache Quality of Service"
-	select SOC_INTEL_COMMON_BLOCK_CAR
-	select INTEL_CAR_CQOS
-	help
-	  Cache Quality of Service allows more fine-grained control of cache
-	  usage. As result, it is possible to set up portion of L2 cache for
-	  CAR and use remainder for actual caching.
-
-config USE_APOLLOLAKE_FSP_CAR
-	bool "Use FSP CAR"
-	select FSP_CAR
-	help
-	  Use FSP APIs to initialize & tear down the Cache-As-Ram.
-
-endchoice
-
 #
 # Each bit in QOS mask controls this many bytes. This is calculated as:
 # (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index fc4dad7bb8..778811e5de 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -10,7 +10,6 @@ subdirs-y += ../../../cpu/x86/cache
 
 bootblock-y += bootblock/bootblock.c
 bootblock-y += ../common/block/cpu/pm_timer_emulation.c
-bootblock-$(CONFIG_FSP_CAR) += fspcar.c
 bootblock-y += car.c
 bootblock-y += heci.c
 bootblock-y += gspi.c
diff --git a/src/soc/intel/apollolake/fspcar.c b/src/soc/intel/apollolake/fspcar.c
deleted file mode 100644
index 931b418fa7..0000000000
--- a/src/soc/intel/apollolake/fspcar.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <FsptUpd.h>
-
-const FSPT_UPD temp_ram_init_params = {
-	.FspUpdHeader = {
-		.Signature = 0x545F4450554C5041ULL,	/* 'APLUPD_T' */
-		.Revision = 1,
-		.Reserved = {0},
-	},
-	.FsptCommonUpd = {
-		.Revision = 0,
-		.Reserved = {0},
-		/*
-		 * It is a requirement for firmware to have Firmware Interface Table
-		 * (FIT), which contains pointers to each microcode update.
-		 * The microcode update is loaded for all logical processors before
-		 * cpu reset vector.
-		 *
-		 * All SoC since Gen-4 has above mechanism in place to load microcode
-		 * even before hitting CPU reset vector. Hence skipping FSP-T loading
-		 * microcode after CPU reset by passing '0' value to
-		 * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength.
-		 */
-		.MicrocodeRegionBase = 0,
-		.MicrocodeRegionLength = 0,
-		.CodeRegionBase =
-			(uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE),
-		.CodeRegionLength = (uint32_t)CONFIG_ROM_SIZE,
-		.Reserved1 = {0},
-	},
-};
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index aa5e5e9cca..dfb1be4879 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -57,12 +57,12 @@ config CPU_SPECIFIC_OPTIONS
 	select FSP_COMPRESS_FSP_S_LZMA
 	select FSP_M_XIP
 	select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
-	select FSP_T_XIP if FSP_CAR
 	select GENERIC_GPIO_LIB
 	select HAVE_FSP_GOP
 	select HAVE_FSP_LOGO_SUPPORT
 	select HAVE_SMI_HANDLER
 	select IDT_IN_EVERY_STAGE
+	select INTEL_CAR_NEM_ENHANCED
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select INTEL_GMA_ACPI
 	select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
@@ -80,6 +80,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
 	select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
 	select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
+	select SOC_INTEL_COMMON_BLOCK_CAR
 	select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
 	select SOC_INTEL_COMMON_BLOCK_CNVI
 	select SOC_INTEL_COMMON_BLOCK_CPU
@@ -276,32 +277,6 @@ config MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE
 	  This will enable a workaround in ASL _PS3 and _PS0 methods to force
 	  SD_PWR_ENABLE to stay low in D3.
 
-choice
-	prompt "Cache-as-ram implementation"
-	default USE_CANNONLAKE_CAR_NEM_ENHANCED
-	help
-	  This option allows you to select how cache-as-ram (CAR) is set up.
-
-config USE_CANNONLAKE_CAR_NEM_ENHANCED
-	bool "Enhanced Non-evict mode"
-	select SOC_INTEL_COMMON_BLOCK_CAR
-	select INTEL_CAR_NEM_ENHANCED
-	help
-	  A current limitation of NEM (Non-Evict mode) is that code and data
-	  sizes are derived from the requirement to not write out any modified
-	  cache line. With NEM, if there is no physical memory behind the
-	  cached area, the modified data will be lost and NEM results will be
-	  inconsistent. ENHANCED NEM guarantees that modified data is always
-	  kept in cache while clean data is replaced.
-
-config USE_CANNONLAKE_FSP_CAR
-	bool "Use FSP CAR"
-	select FSP_CAR
-	help
-	  Use FSP APIs to initialize and tear down the Cache-As-Ram.
-
-endchoice
-
 config FSP_HEADER_PATH
 	default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE
 	default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/" if SOC_INTEL_COMETLAKE_1
diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c
index 01329bf9b1..222193976a 100644
--- a/src/soc/intel/cannonlake/bootblock/bootblock.c
+++ b/src/soc/intel/cannonlake/bootblock/bootblock.c
@@ -12,38 +12,6 @@
 #include <soc/iomap.h>
 #include <soc/pch.h>
 
-#if CONFIG(FSP_CAR)
-#include <FsptUpd.h>
-
-const FSPT_UPD temp_ram_init_params = {
-	.FspUpdHeader = {
-		.Signature = 0x545F4450554C4643ULL,	/* 'CFLUPD_T' */
-		.Revision = 1,
-		.Reserved = {0},
-	},
-	.FsptCoreUpd = {
-		/*
-		 * It is a requirement for firmware to have Firmware Interface Table
-		 * (FIT), which contains pointers to each microcode update.
-		 * The microcode update is loaded for all logical processors before
-		 * cpu reset vector.
-		 *
-		 * All SoC since Gen-4 has above mechanism in place to load microcode
-		 * even before hitting CPU reset vector. Hence skipping FSP-T loading
-		 * microcode after CPU reset by passing '0' value to
-		 * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionSize.
-		 *
-		 * Note: CodeRegionSize must be smaller than or equal to 16MiB to not
-		 * overlap with LAPIC or the CAR area at 0xfef00000.
-		 */
-		.MicrocodeRegionBase = 0,
-		.MicrocodeRegionSize = 0,
-		.CodeRegionBase = (uint32_t)0x100000000ULL - CACHE_ROM_SIZE,
-		.CodeRegionSize = (uint32_t)CACHE_ROM_SIZE,
-	},
-};
-#endif
-
 asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 {
 	/* Call lib/bootblock.c main */