diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-12-06 14:54:55 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-08 20:25:33 +0000 |
| commit | 59d64f06be8eb5f80acfb0b53e7accaf05c1bec8 (patch) | |
| tree | df57fe50cd1b096a9dca70b4b8e3166ef4137f72 /src/soc | |
| parent | 105495f37e0a5e063b4ca414e84f344b13cc28d4 (diff) | |
soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resume
According to https://uefi.org/specs/ACPI/6.4/04_ACPI_Hardware_Specification/ACPI_Hardware_Specification.html#pm1-event-grouping
> For ACPI/legacy systems, when transitioning from the legacy to the G0
> working state this register is cleared by platform firmware prior to
> setting the SCI_EN bit (and thus passing control to OSPM). For ACPI
> only platforms (where SCI_EN is always set), when transitioning from
> either the mechanical off (G3) or soft-off state to the G0 working
> state this register is cleared prior to entering the G0 working state.
This means we don't want to clear the PM1 register on resume. By
clearing it the linux kernel can't correctly increment the wake count
when the power button is pressed. The AMD platforms implement the _SWS
ACPI methods, but the linux kernel doesn't actually use these methods.
BUG=b:172021431
TEST=suspend zork and push power button and verify power button
wake_count increments. Verified other wake sources still work.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iaa886540d90f4751d14837c1485ef50ceca48561
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/cezanne/fch.c | 1 | ||||
| -rw-r--r-- | src/soc/amd/common/block/cpu/smm/finalize.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/picasso/fch.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/romstage.c | 1 |
4 files changed, 2 insertions, 4 deletions
diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index dd19c310bc..8cd1212420 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -199,7 +199,6 @@ void fch_init(void *chip_info) acpi_pm_gpe_add_events_print_events(); gpio_add_events(); - acpi_clear_pm_gpe_status(); gpp_clk_setup(); fch_clk_output_48Mhz(); diff --git a/src/soc/amd/common/block/cpu/smm/finalize.c b/src/soc/amd/common/block/cpu/smm/finalize.c index ec975bea27..73b21216f5 100644 --- a/src/soc/amd/common/block/cpu/smm/finalize.c +++ b/src/soc/amd/common/block/cpu/smm/finalize.c @@ -41,6 +41,8 @@ static void soc_finalize(void *unused) finalize_cores(); if (!acpi_is_wakeup_s3()) { + acpi_clear_pm_gpe_status(); + if (CONFIG(HAVE_SMI_HANDLER)) acpi_disable_sci(); else diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index 44acc817ef..03ba914c81 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -225,8 +225,6 @@ void fch_init(void *chip_info) acpi_pm_gpe_add_events_print_events(); gpio_add_events(); - acpi_clear_pm_gpe_status(); - al2ahb_clock_gate(); gpp_clk_setup(); diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index e316d2166a..c732f7546e 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -214,6 +214,5 @@ static void migrate_power_state(int is_recovery) acpi_fill_pm_gpe_state(&state->gpe_state); acpi_pm_gpe_add_events_print_events(); } - acpi_clear_pm_gpe_status(); } ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) |