diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2024-05-09 19:26:32 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-05-22 15:45:01 +0000 |
| commit | 59d1796d668470d99aee80922b12e3f95550ffff (patch) | |
| tree | 37a933e3475bb87f375d9fcd029ec7db07da474e /src/soc | |
| parent | f2ac23fb13d4c694658b4bb23ab3736cec77c4fa (diff) | |
soc/amd/phoenix/chipset_*.cb: remove TODO
Remove the TODO to update the chipset devicetree for Phoenix, since this
has already been done.
When re-checking the chipset devicetree, I found conflicting information
about the existence of the PCI bridge to an external PCIe port on bus 0
device 1 function 5, but after looking into this, I'm reasonably certain
that it either doesn't exist or at least wouldn't be usable, so I won't
add that one to the chipset devicetree.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8f0e1540ed45408e86186253d3982a7ba0065ac6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/phoenix/chipset_fsp.cb | 2 | ||||
| -rw-r--r-- | src/soc/amd/phoenix/chipset_opensil.cb | 2 |
2 files changed, 0 insertions, 4 deletions
diff --git a/src/soc/amd/phoenix/chipset_fsp.cb b/src/soc/amd/phoenix/chipset_fsp.cb index 08ee8c20cf..2d1e17080a 100644 --- a/src/soc/amd/phoenix/chipset_fsp.cb +++ b/src/soc/amd/phoenix/chipset_fsp.cb @@ -1,5 +1,3 @@ -# TODO: Update for Phoenix - chip soc/amd/phoenix device cpu_cluster 0 on ops amd_cpu_bus_ops diff --git a/src/soc/amd/phoenix/chipset_opensil.cb b/src/soc/amd/phoenix/chipset_opensil.cb index c11975cfea..0c5cfbce55 100644 --- a/src/soc/amd/phoenix/chipset_opensil.cb +++ b/src/soc/amd/phoenix/chipset_opensil.cb @@ -1,5 +1,3 @@ -# TODO: Update for Phoenix - chip soc/amd/phoenix device cpu_cluster 0 on ops amd_cpu_bus_ops |