soc/intel/elkhartlake: Enable PCH GBE

Enable PCH GBE with following changes:
1. Configure PCH GBE related FSP UPD flags
2. Use EHL own GBE ACPI instead of common code version due to
   different B:D.F from the usual GBE
3. Add kconfig PMC_EPOC to use the PMC XTAL read function

Due to EHL GBE comes with time sensitive networking (TSN)
capability integrated, EHL FSP is using 'PchTsn' instead of the
usual 'PchLan' naming convention across the board.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I6b0108e892064e804693a34e360034ae7dbee68f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

5 files changed, 68 insertions, 3 deletions

diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
index 139161bcd7..f440d3313d 100644
--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
@@ -35,6 +35,7 @@ config CPU_SPECIFIC_OPTIONS
 	select REG_SCRIPT
 	select PMC_GLOBAL_RESET_ENABLE_LOCK
 	select PMC_LOW_POWER_MODE_PROGRAM
+	select PMC_EPOC
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_BLOCK
diff --git a/src/soc/intel/elkhartlake/acpi/southbridge.asl b/src/soc/intel/elkhartlake/acpi/southbridge.asl
index ccad7760a3..059f220c0c 100644
--- a/src/soc/intel/elkhartlake/acpi/southbridge.asl
+++ b/src/soc/intel/elkhartlake/acpi/southbridge.asl
@@ -44,5 +44,5 @@
 /* EMMC/SD card */
 #include "scs.asl"
 
-/* GbE 0:1f.6 */
-#include <soc/intel/common/block/acpi/acpi/pch_glan.asl>
+/* GbE 0:1e.4 */
+#include "tsn_glan.asl"
diff --git a/src/soc/intel/elkhartlake/acpi/tsn_glan.asl b/src/soc/intel/elkhartlake/acpi/tsn_glan.asl
new file mode 100644
index 0000000000..de4f0b66a4
--- /dev/null
+++ b/src/soc/intel/elkhartlake/acpi/tsn_glan.asl
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Intel PCH TSN Ethernet Controller 0:1e.4 */
+
+Device(GTSN) {
+	Name(_ADR, 0x001E0004)
+	OperationRegion(TSRT,PCI_Config,0x00,0x100)
+	Field(TSRT,AnyAcc,NoLock,Preserve)
+	{
+		DVID, 16,
+		Offset(0x10),
+		TADL,  32,
+		TADH,  32,
+	}
+}
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index e4c8e38fef..dbce712174 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -42,6 +42,12 @@ struct ehl_ibecc_config {
 	uint16_t region_mask[MAX_IBECC_REGIONS];
 };
 
+/* TSN GBE Link Speed: 0: 2.5Gbps, 1: 1Gbps */
+enum tsn_gbe_link_speed {
+	Tsn_2_5_Gbps,
+	Tsn_1_Gbps,
+};
+
 struct soc_intel_elkhartlake_config {
 
 	/* Common struct containing soc config data required by common code */
@@ -156,7 +162,7 @@ struct soc_intel_elkhartlake_config {
 	 * clksrc. */
 	uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_SRC];
 
-/* Enable PCIe Precision Time Measurement for Root Ports (disabled by default) */
+	/* Enable PCIe Precision Time Measurement for Root Ports (disabled by default) */
 	uint8_t PciePtm[CONFIG_MAX_ROOT_PORTS];
 
 	/* Probe CLKREQ# signal before enabling CLKREQ# based power management.
@@ -400,6 +406,14 @@ struct soc_intel_elkhartlake_config {
 	 * Values: 0x0 - 4s, 0x1 - 6s, 0x2 - 8s, 0x3 - 10s, 0x4 - 12s, 0x5 - 14s
 	 */
 	u8 PchPmPwrBtnOverridePeriod;
+
+	/* GBE related */
+	/* PCH TSN GBE Link Speed: 0: 2.5Gbps, 1: 1Gbps */
+	enum tsn_gbe_link_speed PchTsnGbeLinkSpeed;
+	/* PCH TSN GBE SGMII Support: Disable (0) / Enable (1) */
+	bool PchTsnGbeSgmiiEnable;
+	/* PCH TSN GBE Multiple Virtual Channel: Disable (0) / Enable (1) */
+	bool PchTsnGbeMultiVcEnable;
 };
 
 typedef struct soc_intel_elkhartlake_config config_t;
diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c
index c7ac16ee60..e738d1125a 100644
--- a/src/soc/intel/elkhartlake/fsp_params.c
+++ b/src/soc/intel/elkhartlake/fsp_params.c
@@ -7,6 +7,7 @@
 #include <fsp/util.h>
 #include <intelblocks/lpss.h>
 #include <intelblocks/mp_init.h>
+#include <intelblocks/pmclib.h>
 #include <intelblocks/xdci.h>
 #include <intelpch/lockdown.h>
 #include <soc/intel/common/vbt.h>
@@ -311,6 +312,40 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 		params->PsfFusaConfigEnable = 0;
 	}
 
+	/* PCH GBE config */
+	/*
+	 * Due to EHL GBE comes with time sensitive networking (TSN)
+	 * capability integrated, EHL FSP is using PchTsnEnable instead of
+	 * usual PchLanEnable flag for GBE control. Hence, force
+	 * PchLanEnable to disable to avoid it being used in the future.
+	 */
+	params->PchLanEnable = 0x0;
+	params->PchTsnEnable = is_devfn_enabled(PCH_DEVFN_GBE);
+	if (params->PchTsnEnable) {
+		params->PchTsnGbeSgmiiEnable = config->PchTsnGbeSgmiiEnable;
+		params->PchTsnGbeMultiVcEnable = config->PchTsnGbeMultiVcEnable;
+		/*
+		 * Currently EHL TSN GBE only supports link speed with 2 type of
+		 * PCH XTAL frequency: 24 MHz and 38.4 MHz.
+		 * These are the configs setup for PchTsnGbeLinkSpeed FSP-S UPD:
+		 * 0: 24MHz 2.5Gbps, 1: 24MHz 1Gbps, 2: 38.4MHz 2.5Gbps,
+		 * 3: 38.4MHz 1Gbps
+		 */
+		switch (pmc_get_xtal_freq()) {
+		case XTAL_24_MHZ:
+			params->PchTsnGbeLinkSpeed = (!!config->PchTsnGbeLinkSpeed);
+			break;
+		case XTAL_38_4_MHZ:
+			params->PchTsnGbeLinkSpeed = (!!config->PchTsnGbeLinkSpeed) + 0x2;
+			break;
+		case XTAL_19_2_MHZ:
+		default:
+			printk(BIOS_ERR, "XTAL not supported. Disabling PCH TSN GBE.\n");
+			params->PchTsnEnable = 0;
+			devfn_disable(pci_root_bus(), PCH_DEVFN_GBE);
+		}
+	}
+
 	/* Override/Fill FSP Silicon Param for mainboard */
 	mainboard_silicon_init_params(params);
 }