soc/mediatek/mt8192: initialize DRAM using vendor reference code

Mediatek has released the reference implementation for DRAM
initialization in vendorcode/mediatek/mt8192/dramc (CB:50294)
so we want to use it to replace the derived calibration code
in soc folder.

Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I2b2f41d774c6b85f106867144fb0b29a4a1bdfcf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

13 files changed, 4 insertions, 12631 deletions

diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig
index 9c7a9af9ab..aa4fb01e9e 100644
--- a/src/soc/mediatek/mt8192/Kconfig
+++ b/src/soc/mediatek/mt8192/Kconfig
@@ -6,6 +6,7 @@ config SOC_MEDIATEK_MT8192
 	select ARCH_ROMSTAGE_ARMV8_64
 	select ARCH_RAMSTAGE_ARMV8_64
 	select ARM64_USE_ARM_TRUSTED_FIRMWARE
+	select HAVE_DEBUG_RAM_SETUP
 	select HAVE_UART_SPECIAL
 	select SOC_MEDIATEK_COMMON
 
@@ -17,35 +18,6 @@ config VBOOT
 	select VBOOT_SEPARATE_VERSTAGE
 	select VBOOT_RETURN_FROM_VERSTAGE
 
-config DEBUG_DRAM
-	bool "Output verbose DRAM related debug messages"
-	default y
-	help
-	  This option enables additional DRAM related debug messages.
-
-config MT8192_DRAM_EMCP
-	bool
-	default y
-	help
-	  The eMCP platform should select this option to run at different DRAM
-	  frequencies.
-
-config MT8192_DRAM_DVFS
-	bool
-	default n
-	help
-	  This option enables DRAM calibration with multiple frequencies (low,
-	  medium and high frequency groups, with total 7 frequencies) for DVFS
-	  feature. All supported data rates are: 800, 1200, 1600, 1866, 2400,
-	  3200, 4266.
-
-config MEMORY_TEST
-	bool
-	default y
-	help
-	  This option enables memory basic compare test to verify the DRAM read
-	  or write is as expected.
-
 config DPM_DM_FIRMWARE
 	string
 	default "dpm.dm"
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index a872916763..2370c654c5 100644
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -29,14 +29,12 @@ verstage-y += ../common/uart.c
 romstage-y += ../common/auxadc.c
 romstage-y += ../common/cbmem.c
 romstage-y += ../common/dram_init.c
-romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_pi_calibration_api.c
-romstage-y += dramc_utility.c dramc_dvfs.c
-romstage-y += emi.c
+romstage-y += ../common/dramc_param.c
 romstage-y += ../common/flash_controller.c
 romstage-y += ../common/gpio.c gpio.c
 romstage-y += ../common/i2c.c i2c.c
+romstage-y += ../common/memory.c ../common/memory_test.c
 romstage-y += ../common/mmu_operations.c mmu_operations.c
-romstage-y += ../common/memory.c ../common/dramc_param.c ../common/memory_test.c
 romstage-y += ../common/pll.c pll.c
 romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 romstage-y += ../common/timer.c
@@ -53,7 +51,6 @@ ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c
 ramstage-y += ../common/flash_controller.c
 ramstage-y += ../common/gpio.c gpio.c
 ramstage-y += ../common/i2c.c i2c.c
-ramstage-y += emi.c
 ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 ramstage-y += ../common/mcu.c
 ramstage-y += mcupm.c
@@ -97,6 +94,7 @@ BL31_MAKEARGS += PLAT=mt8192
 
 CPPFLAGS_common += -Isrc/soc/mediatek/mt8192/include
 CPPFLAGS_common += -Isrc/soc/mediatek/common/include
+CPPFLAGS_common += -Isrc/vendorcode/mediatek/mt8192/include
 
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
 	./util/mtkheader/gen-bl-img.py mt8183 sf $< $@
diff --git a/src/soc/mediatek/mt8192/dramc_dvfs.c b/src/soc/mediatek/mt8192/dramc_dvfs.c
deleted file mode 100644
index 7fc8d28fd9..0000000000
--- a/src/soc/mediatek/mt8192/dramc_dvfs.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <soc/dramc_pi_api.h>
-#include <soc/dramc_register.h>
-
-void enable_dfs_hw_mode_clk(void)
-{
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl3,
-			MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI, 0x3,
-			MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE, 0x1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_clk_ctrl,
-			MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN, 0x1,
-			MISC_CLK_CTRL_DVFS_CLK_MEM_SEL, 0x1,
-			MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE, 0x0,
-			MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL, 0x1);
-	}
-}
-
-void dramc_dfs_direct_jump_rg_mode(const struct ddr_cali *cali, u8 shu_level)
-{
-	u8 shu_ack = 0;
-	u8 tmp_level;
-	u8 pll_mode = *(cali->pll_mode);
-	u32 *shu_ack_reg = &mtk_dpm->status_4;
-
-	if (pll_mode == PHYPLL_MODE) {
-		dramc_dbg("Disable CLRPLL\n");
-		for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
-			SET32_BITFIELDS(&ch[chn].phy_ao.clrpll0, CLRPLL0_RG_RCLRPLL_EN, 0);
-	} else {
-		dramc_dbg("Disable PHYPLL\n");
-		for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
-			SET32_BITFIELDS(&ch[chn].phy_ao.phypll0, PHYPLL0_RG_RPHYPLL_EN, 0);
-	}
-
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
-		shu_ack |= (0x1 << chn);
-
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl,
-			MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN, 1);
-
-	if (shu_level == DRAM_DFS_SHU0)
-		tmp_level = shu_level;
-	else
-		tmp_level = 1;
-
-	if (pll_mode == PHYPLL_MODE) {
-		for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-			SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl,
-				MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN, 0);
-			SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl,
-				MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL, tmp_level);
-			SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl,
-				MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN, 1);
-		}
-		dramc_dbg("Enable CLRPLL\n");
-	} else {
-		for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-			SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl,
-				MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN, 0);
-			SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl,
-				MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL, tmp_level);
-			SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl,
-				MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN, 1);
-		}
-		dramc_dbg("Enable PHYPLL\n");
-	}
-	udelay(1);
-
-	if (pll_mode == PHYPLL_MODE)
-		for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
-			SET32_BITFIELDS(&ch[chn].phy_ao.clrpll0, CLRPLL0_RG_RCLRPLL_EN, 1);
-	else
-		for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
-			SET32_BITFIELDS(&ch[chn].phy_ao.phypll0, PHYPLL0_RG_RPHYPLL_EN, 1);
-
-	udelay(20);
-
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl,
-			MISC_RG_DFS_CTRL_RG_DR_SHU_EN, 1);
-	while ((READ32_BITFIELD(shu_ack_reg, LPIF_STATUS_4_SHU_EN_ACK) & shu_ack) != shu_ack)
-		dramc_dbg("Waiting shu_en ack\n");
-
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl,
-			MISC_RG_DFS_CTRL_RG_DR_SHU_EN, 0);
-
-	if (pll_mode == PHYPLL_MODE)
-		for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
-			SET32_BITFIELDS(&ch[chn].phy_ao.phypll0, PHYPLL0_RG_RPHYPLL_EN, 0);
-	else
-		for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
-			SET32_BITFIELDS(&ch[chn].phy_ao.clrpll0, CLRPLL0_RG_RCLRPLL_EN, 0);
-
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl,
-			MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN, 0);
-
-	dramc_dbg("Shuffle flow completed\n");
-
-	pll_mode = !pll_mode;
-	*(cali->pll_mode) = pll_mode;
-}
-
-void dramc_save_result_to_shuffle(dram_dfs_shu src, dram_dfs_shu dst)
-{
-	u8 tmp;
-
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
-			MISC_SRAM_DMA0_SW_DMA_FIRE, 0);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
-			MISC_SRAM_DMA0_APB_SLV_SEL, 0);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
-			MISC_SRAM_DMA0_SW_MODE, 1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
-			MISC_SRAM_DMA0_SW_STEP_EN_MODE, 1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
-			MISC_SRAM_DMA0_SRAM_WR_MODE, 1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
-			MISC_SRAM_DMA0_APB_WR_MODE, 0);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
-			MISC_SRAM_DMA0_SW_SHU_LEVEL_APB, src);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
-			MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM, dst);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
-			MISC_SRAM_DMA0_SW_DMA_FIRE, 1);
-		do {
-			tmp = READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0,
-				MISC_DMA_DEBUG0_SRAM_DONE);
-			tmp |= (READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0,
-						MISC_DMA_DEBUG0_APB_DONE) << 1);
-			dramc_dbg("Waiting dramc to shuffle sram, tmp: %u\n", tmp);
-		} while (tmp != 0x3);
-
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
-			MISC_SRAM_DMA0_SW_DMA_FIRE, 0);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
-			MISC_SRAM_DMA0_SW_STEP_EN_MODE, 0);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
-			MISC_SRAM_DMA0_SW_MODE, 0);
-	}
-
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
-			MISC_SRAM_DMA0_SRAM_WR_MODE, 0);
-}
-
-void dramc_load_shuffle_to_dramc(dram_dfs_shu src, dram_dfs_shu dst)
-{
-	u8 tmp;
-
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
-			MISC_SRAM_DMA0_SW_DMA_FIRE, 0);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
-			MISC_SRAM_DMA0_APB_SLV_SEL, 0);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
-			MISC_SRAM_DMA0_SW_MODE, 1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
-			MISC_SRAM_DMA0_SW_STEP_EN_MODE, 1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
-			MISC_SRAM_DMA0_SRAM_WR_MODE, 0);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
-			MISC_SRAM_DMA0_APB_WR_MODE, 1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
-			MISC_SRAM_DMA0_SW_SHU_LEVEL_APB, dst);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
-			MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM, src);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
-			MISC_SRAM_DMA0_SW_DMA_FIRE, 1);
-		do {
-			tmp = READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0,
-				MISC_DMA_DEBUG0_SRAM_DONE);
-			tmp |= (READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0,
-				MISC_DMA_DEBUG0_APB_DONE) << 1);
-			dramc_dbg("Waiting shuffle sram to dramc, tmp: %u\n", tmp);
-		} while (tmp != 0x3);
-
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
-				MISC_SRAM_DMA0_SW_DMA_FIRE, 0);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
-				MISC_SRAM_DMA0_SW_STEP_EN_MODE, 0);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
-				MISC_SRAM_DMA0_SW_MODE, 0);
-	}
-}
diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c
deleted file mode 100644
index 996dff88ed..0000000000
--- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c
+++ /dev/null
@@ -1,4710 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <soc/dramc_ac_timing.h>
-#include <soc/dramc_pi_api.h>
-#include <soc/dramc_register.h>
-#include <soc/gpio.h>
-#include <timer.h>
-
-static const u8 mrr_o1_pinmux_mapping[PINMUX_MAX][CHANNEL_MAX][DQ_DATA_WIDTH] = {
-	[PINMUX_DSC] = {
-		[CHANNEL_A] = {0, 1, 7, 6, 4, 5, 2, 3, 9, 8, 11, 10, 14, 15, 13, 12},
-		[CHANNEL_B] = {1, 0, 5, 6, 3, 2, 7, 4, 8, 9, 11, 10, 12, 14, 13, 15},
-	},
-	[PINMUX_LPBK] = {
-	},
-	[PINMUX_EMCP] = {
-		[CHANNEL_A] = {1, 0, 3, 2, 4, 7, 6, 5, 8, 9, 10, 14, 11, 15, 13, 12},
-		[CHANNEL_B] = {0, 1, 4, 7, 3, 5, 6, 2, 9, 8, 10, 12, 11, 14, 13, 15}
-	},
-};
-
-static void set_rank_info_to_conf(const struct ddr_cali *cali)
-{
-	u8 value = ((cali->emi_config->cona_val >> 17) & 0x1) ? 0 : 1;
-
-	SET32_BITFIELDS(&ch[0].ao.sa_reserve,
-		SA_RESERVE_MODE_RK0, cali->cbt_mode[RANK_0],
-		SA_RESERVE_MODE_RK1, cali->cbt_mode[RANK_1],
-		SA_RESERVE_SINGLE_RANK, value);
-}
-
-static void get_dram_pinmux_sel(struct ddr_cali *cali)
-{
-	u32 value = (read32(&mtk_gpio->dram_pinmux_trapping) >> 19) & 0x1;
-
-	if (value)
-		cali->pinmux_type = PINMUX_DSC;
-	else
-		cali->pinmux_type = PINMUX_EMCP;
-}
-
-static void set_mrr_pinmux_mapping(const struct ddr_cali *cali)
-{
-	const u8 *map;
-	u32 bc_bak = dramc_get_broadcast();
-
-	dramc_set_broadcast(DRAMC_BROADCAST_OFF);
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-		map = mrr_o1_pinmux_mapping[get_pinmux_type(cali)][chn];
-		SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux1,
-			MRR_BIT_MUX1_MRR_BIT0_SEL, map[0],
-			MRR_BIT_MUX1_MRR_BIT1_SEL, map[1],
-			MRR_BIT_MUX1_MRR_BIT2_SEL, map[2],
-			MRR_BIT_MUX1_MRR_BIT3_SEL, map[3]);
-		SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux2,
-			MRR_BIT_MUX2_MRR_BIT4_SEL, map[4],
-			MRR_BIT_MUX2_MRR_BIT5_SEL, map[5],
-			MRR_BIT_MUX2_MRR_BIT6_SEL, map[6],
-			MRR_BIT_MUX2_MRR_BIT7_SEL, map[7]);
-		SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux3,
-			MRR_BIT_MUX3_MRR_BIT8_SEL, map[8],
-			MRR_BIT_MUX3_MRR_BIT9_SEL, map[9],
-			MRR_BIT_MUX3_MRR_BIT10_SEL, map[10],
-			MRR_BIT_MUX3_MRR_BIT11_SEL, map[11]);
-		SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux4,
-			MRR_BIT_MUX4_MRR_BIT12_SEL, map[12],
-			MRR_BIT_MUX4_MRR_BIT13_SEL, map[13],
-			MRR_BIT_MUX4_MRR_BIT14_SEL, map[14],
-			MRR_BIT_MUX4_MRR_BIT15_SEL, map[15]);
-	}
-	dramc_set_broadcast(bc_bak);
-}
-
-static void set_dqo1_pinmux_mapping(const struct ddr_cali *cali)
-{
-	const u8 *map;
-	u32 bc_bak = dramc_get_broadcast();
-
-	dramc_set_broadcast(DRAMC_BROADCAST_OFF);
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-		map = mrr_o1_pinmux_mapping[get_pinmux_type(cali)][chn];
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_dq_se_pinmux_ctrl0,
-			MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ0, map[0],
-			MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ1, map[1],
-			MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ2, map[2],
-			MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ3, map[3],
-			MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ4, map[4],
-			MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ5, map[5],
-			MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ6, map[6],
-			MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ7, map[7]);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_dq_se_pinmux_ctrl1,
-			MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ8, map[8],
-			MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ9, map[9],
-			MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ10, map[10],
-			MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ11, map[11],
-			MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ12, map[12],
-			MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ13, map[13],
-			MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ14, map[14],
-			MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ15, map[15]);
-	}
-
-	dramc_set_broadcast(bc_bak);
-}
-
-void global_option_init(struct ddr_cali *cali)
-{
-	set_rank_info_to_conf(cali);
-	get_dram_pinmux_sel(cali);
-	set_mrr_pinmux_mapping(cali);
-	set_dqo1_pinmux_mapping(cali);
-}
-
-static void dramc_init_default_mr_value(const struct ddr_cali *cali)
-{
-	struct mr_values *mr_value = cali->mr_value;
-	dram_freq_grp freq_group = cali->freq_group;
-	u8 highest_freq = get_highest_freq_group();
-
-	mr_value->mr01[FSP_0] = 0x26;
-	mr_value->mr01[FSP_1] = 0x56;
-	mr_value->mr02[FSP_0] = 0x1a;
-	mr_value->mr02[FSP_1] = 0x1a;
-
-	mr_value->mr03[FSP_0] = 0x30 | 0x4;
-	mr_value->mr03[FSP_1] = 0x30 | 0x4 | 0x2;
-
-	mr_value->mr04[RANK_0] = 0x3;
-	mr_value->mr04[RANK_1] = 0x3;
-
-	mr_value->mr21[FSP_0] = 0x0;
-	mr_value->mr21[FSP_1] = 0x0;
-	mr_value->mr51[FSP_0] = 0x0;
-	mr_value->mr51[FSP_1] = 0x0;
-
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
-		for (u8 rk = 0; rk < RANK_MAX; rk++) {
-			mr_value->mr23[chn][rk] = 0x3f;
-			for (u8 fsp = 0; fsp < FSP_MAX; fsp++) {
-				mr_value->mr14[chn][rk][fsp] = (fsp == FSP_0) ? 0x5d : 0x18;
-				mr_value->mr12[chn][rk][fsp] = (fsp == FSP_0) ? 0x5d : 0x1b;
-			}
-		}
-
-	mr_value->mr01[FSP_0] &= 0x8F;
-	mr_value->mr01[FSP_1] &= 0x8F;
-
-	if (highest_freq == DDRFREQ_2133) {
-		mr_value->mr01[FSP_0] |= (0x7 << 4);
-		mr_value->mr01[FSP_1] |= (0x7 << 4);
-	} else {
-		mr_value->mr01[FSP_0] |= (0x5 << 4);
-		mr_value->mr01[FSP_1] |= (0x5 << 4);
-	}
-
-	switch (freq_group) {
-	case DDRFREQ_400:
-		mr_value->mr02[FSP_0] = 0x12;
-		break;
-	case DDRFREQ_600:
-	case DDRFREQ_800:
-		mr_value->mr02[FSP_0] = 0x12;
-		break;
-	case DDRFREQ_933:
-		mr_value->mr02[FSP_0] = 0x1b;
-		break;
-	case DDRFREQ_1200:
-		mr_value->mr02[FSP_0] = 0x24;
-		break;
-	case DDRFREQ_1600:
-		mr_value->mr02[FSP_1] = 0x2d;
-		break;
-	case DDRFREQ_2133:
-		mr_value->mr02[FSP_1] = 0x3f;
-		break;
-	default:
-		die("Invalid DDR frequency group %u\n", freq_group);
-		return;
-	}
-}
-
-static void sv_algorithm_assistance_lp4_800(void)
-{
-	SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rdsel_track,
-		SHU_MISC_RDSEL_TRACK_DMDATLAT_I, 0x0e,
-		SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK, 0x1,
-		SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN, 0x0,
-		SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG, 0xff5,
-		SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS, 0x00b);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rdat,
-		MISC_SHU_RDAT_DATLAT, 0x0e,
-		MISC_SHU_RDAT_DATLAT_DSEL, 0x0e,
-		MISC_SHU_RDAT_DATLAT_DSEL_PHY, 0x0e);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_phy_rx_ctrl,
-		MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN, 0x1,
-		MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET, 0x2,
-		MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET, 0x1,
-		MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD, 0x0,
-		MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL, 0x1,
-		MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD, 0x0,
-		MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rankctl,
-		MISC_SHU_RANKCTL_RANKINCTL_RXDLY, 0x3,
-		MISC_SHU_RANKCTL_RANK_RXDLY_OPT, 0x1,
-		MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN, 0x1,
-		MISC_SHU_RANKCTL_RANKINCTL_STB, 0x4,
-		MISC_SHU_RANKCTL_RANKINCTL, 0x4,
-		MISC_SHU_RANKCTL_RANKINCTL_ROOT1, 0x4,
-		MISC_SHU_RANKCTL_RANKINCTL_PHY, 0x6);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rank_sel_lat,
-		MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0, 0x4,
-		MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1, 0x4,
-		MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA, 0x4);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqsctl,
-		MISC_SHU_RK_DQSCTL_DQSINCTL, 0x6);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqsctl,
-		MISC_SHU_RK_DQSCTL_DQSINCTL, 0x6);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_dqsien_mck_ui_dly,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x6,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0x8,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x0,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_dqsien_pi_dly,
-		SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x0b);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_dqsien_mck_ui_dly,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x7,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0x9,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x0,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_dqsien_pi_dly,
-		SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x1f);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_dqsien_mck_ui_dly,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x6,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0x8,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x0,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_dqsien_pi_dly,
-		SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x0b);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_dqsien_mck_ui_dly,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x7,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0x9,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x0,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_dqsien_pi_dly,
-		SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x1f);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_odtctrl,
-		MISC_SHU_ODTCTRL_RODTEN, 0x1,
-		MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG, 0x0,
-		MISC_SHU_ODTCTRL_RODT_LAT, 0x4,
-		MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN, 0x0,
-		MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT, 0x0,
-		MISC_SHU_ODTCTRL_FIXRODT, 0x0,
-		MISC_SHU_ODTCTRL_RODTEN_OPT, 0x1,
-		MISC_SHU_ODTCTRL_RODTE2, 0x1,
-		MISC_SHU_ODTCTRL_RODTE, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7,
-		SHU_B0_DQ7_R_DMRANKRXDVS_B0, 0x0,
-		SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0, 0x0,
-		SHU_B0_DQ7_R_DMDQMDBI_SHU_B0, 0x0,
-		SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0, 0x0,
-		SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0, 0x0,
-		SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0, 0x0,
-		SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7,
-		SHU_B0_DQ7_R_DMRODTEN_B0, 0x1,
-		SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0, 0x0,
-		SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0x0,
-		SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0x0,
-		SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0x0,
-		SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0, 0x0,
-		SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0, 0x1,
-		SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0, 0x1,
-		SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0, 0x1,
-		SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7,
-		SHU_B1_DQ7_R_DMRANKRXDVS_B1, 0x0,
-		SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1, 0x0,
-		SHU_B1_DQ7_R_DMDQMDBI_SHU_B1, 0x0,
-		SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1, 0x0,
-		SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1, 0x0,
-		SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1, 0x0,
-		SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7,
-		SHU_B1_DQ7_R_DMRODTEN_B1, 0x1,
-		SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1, 0x0,
-		SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0x0,
-		SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0x0,
-		SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0x0,
-		SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1, 0x0,
-		SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1, 0x1,
-		SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1, 0x1,
-		SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1, 0x1,
-		SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rx_pipe_ctrl,
-		SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_rodten_mck_ui_dly,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x1,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x1,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x0,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_rodten_mck_ui_dly,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x2,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x2,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x0,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_rodten_mck_ui_dly,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x1,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x1,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x0,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_rodten_mck_ui_dly,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x2,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x2,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x0,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_rx_cg_set0,
-		SHU_RX_CG_SET0_DLE_LAST_EXTEND3, 0x0,
-		SHU_RX_CG_SET0_READ_START_EXTEND3, 0x0,
-		SHU_RX_CG_SET0_DLE_LAST_EXTEND2, 0x1,
-		SHU_RX_CG_SET0_READ_START_EXTEND2, 0x1,
-		SHU_RX_CG_SET0_DLE_LAST_EXTEND1, 0x1,
-		SHU_RX_CG_SET0_READ_START_EXTEND1, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rank_sel_stb,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN, 0x1,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23, 0x0,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE, 0x0,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK, 0x1,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK, 0x0,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN, 0x0,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, 0x5,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS, 0x0,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS, 0x0,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS, 0x0,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqscal,
-		MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60,
-		MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1,
-		MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f,
-		MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqscal,
-		MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60,
-		MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1,
-		MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f,
-		MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_ini_uipi,
-		SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x0b,
-		SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x06);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_ini_uipi,
-		SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x0b,
-		SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x06);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_ini_uipi,
-		SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x1f,
-		SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x07);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_ini_uipi,
-		SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x1f,
-		SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x07);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_next_ini_uipi,
-		SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x0b,
-		SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x06,
-		SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x08);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_next_ini_uipi,
-		SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x0b,
-		SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x06,
-		SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x08);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_next_ini_uipi,
-		SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x1f,
-		SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x07,
-		SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x09);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_next_ini_uipi,
-		SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x1f,
-		SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x07,
-		SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x09);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_dq0,
-		SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0,
-		SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0,
-		SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x18,
-		SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x18,
-		SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00,
-		SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0,
-		SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_dq0,
-		SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0,
-		SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0,
-		SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x18,
-		SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x18,
-		SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00,
-		SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0,
-		SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_dq0,
-		SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0,
-		SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0,
-		SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x18,
-		SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x18,
-		SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00,
-		SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0,
-		SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_dq0,
-		SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0,
-		SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0,
-		SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x18,
-		SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x18,
-		SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00,
-		SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0,
-		SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_dcm_ctrl0,
-		SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT, 0x1,
-		SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT, 0x3,
-		SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL, 0x6,
-		SHU_DCM_CTRL0_APHYPI_CKCGL_CNT, 0x2,
-		SHU_DCM_CTRL0_APHYPI_CKCGH_CNT, 0x5,
-		SHU_DCM_CTRL0_FASTWAKE2, 0x0,
-		SHU_DCM_CTRL0_FASTWAKE, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_aphy_tx_picg_ctrl,
-		SHU_APHY_TX_PICG_CTRL_TX_PICG_CNT, 0x3,
-		SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P1, 0x0,
-		SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P0, 0x3,
-		SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT, 0x2,
-		SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_aphy_tx_picg_ctrl,
-		SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x0,
-		SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x3);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_aphy_tx_picg_ctrl,
-		SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x0,
-		SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x3);
-	SET32_BITFIELDS(&ch[0].ao.shu_new_xrw2w_ctrl,
-		SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0, 0x2,
-		SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1, 0x2,
-		SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs0,
-		SHU_SELPH_DQS0_TXDLY_DQS0, 0x4,
-		SHU_SELPH_DQS0_TXDLY_DQS1, 0x4,
-		SHU_SELPH_DQS0_TXDLY_DQS2, 0x1,
-		SHU_SELPH_DQS0_TXDLY_DQS3, 0x1,
-		SHU_SELPH_DQS0_TXDLY_OEN_DQS0, 0x3,
-		SHU_SELPH_DQS0_TXDLY_OEN_DQS1, 0x3,
-		SHU_SELPH_DQS0_TXDLY_OEN_DQS2, 0x1,
-		SHU_SELPH_DQS0_TXDLY_OEN_DQS3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq0,
-		SHURK_SELPH_DQ0_TXDLY_DQ0, 0x4,
-		SHURK_SELPH_DQ0_TXDLY_DQ1, 0x4,
-		SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x3,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x3,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq1,
-		SHURK_SELPH_DQ1_TXDLY_DQM0, 0x4,
-		SHURK_SELPH_DQ1_TXDLY_DQM1, 0x4,
-		SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x3,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x3,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq2,
-		SHURK_SELPH_DQ2_DLY_DQ0, 0x1,
-		SHURK_SELPH_DQ2_DLY_DQ1, 0x1,
-		SHURK_SELPH_DQ2_DLY_DQ2, 0x1,
-		SHURK_SELPH_DQ2_DLY_DQ3, 0x1,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x2,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x2,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq3,
-		SHURK_SELPH_DQ3_DLY_DQM0, 0x1,
-		SHURK_SELPH_DQ3_DLY_DQM1, 0x1,
-		SHURK_SELPH_DQ3_DLY_DQM2, 0x1,
-		SHURK_SELPH_DQ3_DLY_DQM3, 0x1,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x2,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x2,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq0,
-		SHURK_SELPH_DQ0_TXDLY_DQ0, 0x4,
-		SHURK_SELPH_DQ0_TXDLY_DQ1, 0x4,
-		SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x3,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x3,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq1,
-		SHURK_SELPH_DQ1_TXDLY_DQM0, 0x4,
-		SHURK_SELPH_DQ1_TXDLY_DQM1, 0x4,
-		SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x3,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x3,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq2,
-		SHURK_SELPH_DQ2_DLY_DQ0, 0x1,
-		SHURK_SELPH_DQ2_DLY_DQ1, 0x1,
-		SHURK_SELPH_DQ2_DLY_DQ2, 0x1,
-		SHURK_SELPH_DQ2_DLY_DQ3, 0x1,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x2,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x2,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq3,
-		SHURK_SELPH_DQ3_DLY_DQM0, 0x1,
-		SHURK_SELPH_DQ3_DLY_DQM1, 0x1,
-		SHURK_SELPH_DQ3_DLY_DQM2, 0x1,
-		SHURK_SELPH_DQ3_DLY_DQM3, 0x1,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x2,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x2,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal1,
-		SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x018,
-		SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x018);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal2,
-		SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x018,
-		SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x018);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal5,
-		SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x018,
-		SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x018);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal1,
-		SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x018,
-		SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x018);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal2,
-		SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x018,
-		SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x018);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal5,
-		SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x018,
-		SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x018);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_pi,
-		SHURK_PI_RK0_ARPI_DQ_B1, 0x18,
-		SHURK_PI_RK0_ARPI_DQ_B0, 0x18,
-		SHURK_PI_RK0_ARPI_DQM_B1, 0x18,
-		SHURK_PI_RK0_ARPI_DQM_B0, 0x18);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_pi,
-		SHURK_PI_RK0_ARPI_DQ_B1, 0x18,
-		SHURK_PI_RK0_ARPI_DQ_B0, 0x18,
-		SHURK_PI_RK0_ARPI_DQM_B1, 0x18,
-		SHURK_PI_RK0_ARPI_DQM_B0, 0x18);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly0,
-		SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x30,
-		SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x30,
-		SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x30,
-		SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x30);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly1,
-		SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x30,
-		SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x30,
-		SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x30,
-		SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x30);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly3,
-		SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x30,
-		SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00,
-		SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly0,
-		SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x0c,
-		SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x0c,
-		SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x0c,
-		SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x0c);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly1,
-		SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x0c,
-		SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x0c,
-		SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x0c,
-		SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x0c);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly3,
-		SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x0c,
-		SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00,
-		SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly0,
-		SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x10,
-		SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x10,
-		SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x10,
-		SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x10);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly1,
-		SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x10,
-		SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x10,
-		SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x10,
-		SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x10);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly3,
-		SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x10,
-		SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00,
-		SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly0,
-		SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x20,
-		SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x20,
-		SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x20,
-		SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x20);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly1,
-		SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x20,
-		SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x20,
-		SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x20,
-		SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x20);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly3,
-		SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x20,
-		SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00,
-		SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00);
-	SET32_BITFIELDS(&ch[0].ao.shu_tx_rankctl,
-		SHU_TX_RANKCTL_TXRANKINCTL_TXDLY, 0x1,
-		SHU_TX_RANKCTL_TXRANKINCTL, 0x1,
-		SHU_TX_RANKCTL_TXRANKINCTL_ROOT, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_ac_derating0,
-		SHU_AC_DERATING0_ACDERATEEN, 0x1,
-		SHU_AC_DERATING0_TRRD_DERATE, 0x2,
-		SHU_AC_DERATING0_TRCD_DERATE, 0x4);
-	SET32_BITFIELDS(&ch[0].ao.shu_ac_derating1,
-		SHU_AC_DERATING1_TRPAB_DERATE, 0x3,
-		SHU_AC_DERATING1_TRP_DERATE, 0x2,
-		SHU_AC_DERATING1_TRAS_DERATE, 0x01,
-		SHU_AC_DERATING1_TRC_DERATE, 0x00);
-	SET32_BITFIELDS(&ch[0].ao.shu_sref_ctrl,
-		SHU_SREF_CTRL_CKEHCMD, 0x3,
-		SHU_SREF_CTRL_SREF_CK_DLY, 0x3);
-	SET32_BITFIELDS(&ch[0].ao.shu_hmr4_dvfs_ctrl0,
-		SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT, 0x32,
-		SHU_HMR4_DVFS_CTRL0_REFRCNT, 0x000);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim_xrt,
-		SHU_ACTIM_XRT_XRTR2R, 0x05,
-		SHU_ACTIM_XRT_XRTR2W, 0x0a,
-		SHU_ACTIM_XRT_XRTW2R, 0x6,
-		SHU_ACTIM_XRT_XRTW2W, 0x09);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim0,
-		SHU_ACTIM0_TWTR, 0x0a,
-		SHU_ACTIM0_TWR, 0x0c,
-		SHU_ACTIM0_TRRD, 0x1,
-		SHU_ACTIM0_TRCD, 0x4,
-		SHU_ACTIM0_CKELCKCNT, 0x3);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim1,
-		SHU_ACTIM1_TRPAB, 0x3,
-		SHU_ACTIM1_TMRWCKEL, 0x7,
-		SHU_ACTIM1_TRP, 0x2,
-		SHU_ACTIM1_TRAS, 0x01,
-		SHU_ACTIM1_TRC, 0x00);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim2,
-		SHU_ACTIM2_TXP, 0x0,
-		SHU_ACTIM2_TMRRI, 0x07,
-		SHU_ACTIM2_TRTP, 0x3,
-		SHU_ACTIM2_TR2W, 0x0a,
-		SHU_ACTIM2_TFAW, 0x00);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim3,
-		SHU_ACTIM3_TRFCPB, 0x1a,
-		SHU_ACTIM3_MANTMRR, 0x8,
-		SHU_ACTIM3_TR2MRR, 0x8,
-		SHU_ACTIM3_TRFC, 0x40,
-		SHU_ACTIM3_TWTR_L, 0x25);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim4,
-		SHU_ACTIM4_TXREFCNT, 0x04e,
-		SHU_ACTIM4_TMRR2MRW, 0x0f,
-		SHU_ACTIM4_TMRR2W, 0x0c,
-		SHU_ACTIM4_TZQCS, 0x10);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim5,
-		SHU_ACTIM5_TR2PD, 0x10,
-		SHU_ACTIM5_TWTPD, 0x0f,
-		SHU_ACTIM5_TPBR2PBR, 0x15,
-		SHU_ACTIM5_TPBR2ACT, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim6,
-		SHU_ACTIM6_TZQLAT2, 0x06,
-		SHU_ACTIM6_TMRD, 0x6,
-		SHU_ACTIM6_TMRW, 0x5,
-		SHU_ACTIM6_TW2MRW, 0x0d,
-		SHU_ACTIM6_TR2MRW, 0x11);
-	SET32_BITFIELDS(&ch[0].ao.shu_ckectrl,
-		SHU_CKECTRL_TPDE_05T, 0x0,
-		SHU_CKECTRL_TPDX_05T, 0x0,
-		SHU_CKECTRL_TPDE, 0x3,
-		SHU_CKECTRL_TPDX, 0x3,
-		SHU_CKECTRL_TCKEPRD, 0x2,
-		SHU_CKECTRL_TCKESRX, 0x3);
-	SET32_BITFIELDS(&ch[0].ao.shu_misc,
-		SHU_MISC_REQQUE_MAXCNT, 0x2,
-		SHU_MISC_DCMDLYREF, 0x7,
-		SHU_MISC_DAREFEN, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq8,
-		SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0, 0x0031,
-		SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0, 0x0,
-		SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 0x1,
-		SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 0x1,
-		SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq8,
-		SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1, 0x0031,
-		SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1, 0x0,
-		SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 0x1,
-		SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 0x1,
-		SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq5,
-		SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0, 0x0e,
-		SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0, 0x0,
-		SHU_B0_DQ5_RG_ARPI_FB_B0, 0x00,
-		SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0, 0x0,
-		SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0, 0x0,
-		SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0, 0x7,
-		SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq5,
-		SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1, 0x0e,
-		SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1, 0x0,
-		SHU_B1_DQ5_RG_ARPI_FB_B1, 0x00,
-		SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1, 0x0,
-		SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1, 0x0,
-		SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1, 0x7,
-		SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly0,
-		SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x75,
-		SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x75,
-		SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x75,
-		SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x75);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly1,
-		SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x75,
-		SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x75,
-		SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x75,
-		SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x75);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly2,
-		SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x75,
-		SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x75,
-		SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x75,
-		SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x75);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly3,
-		SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x75,
-		SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x75,
-		SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x75,
-		SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x75);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly4,
-		SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x75,
-		SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x75);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly5,
-		SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x17e,
-		SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x17e);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly0,
-		SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x74,
-		SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x74,
-		SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x74,
-		SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x74);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly1,
-		SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x74,
-		SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x74,
-		SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x74,
-		SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x74);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly2,
-		SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x74,
-		SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x74,
-		SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x74,
-		SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x74);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly3,
-		SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x74,
-		SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x74,
-		SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x74,
-		SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x74);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly4,
-		SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x74,
-		SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x74);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly5,
-		SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x17d,
-		SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x17d);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly0,
-		SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0x75,
-		SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0x75,
-		SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0x75,
-		SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0x75);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly1,
-		SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0x75,
-		SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0x75,
-		SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0x75,
-		SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0x75);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly2,
-		SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0x75,
-		SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0x75,
-		SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0x75,
-		SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0x75);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly3,
-		SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0x75,
-		SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0x75,
-		SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0x75,
-		SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0x75);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly4,
-		SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0x75,
-		SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0x75);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly5,
-		SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x17e,
-		SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x17e);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly0,
-		SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0x74,
-		SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0x74,
-		SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0x74,
-		SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0x74);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly1,
-		SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0x74,
-		SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0x74,
-		SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0x74,
-		SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0x74);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly2,
-		SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0x74,
-		SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0x74,
-		SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0x74,
-		SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0x74);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly3,
-		SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0x74,
-		SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0x74,
-		SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0x74,
-		SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0x74);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly4,
-		SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0x74,
-		SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0x74);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly5,
-		SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x17d,
-		SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x17d);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9,
-		B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 0x1,
-		B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 0x0,
-		B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0, 0x0,
-		B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0, 0x1,
-		B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0, 0x0,
-		B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0, 0x00,
-		B0_DQ9_R_DMDQSIEN_VALID_LAT_B0, 0x0,
-		B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0, 0x0,
-		B0_DQ9_R_DMRXDVS_VALID_LAT_B0, 0x0,
-		B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9,
-		B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 0x1,
-		B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 0x0,
-		B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1, 0x0,
-		B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1, 0x1,
-		B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1, 0x0,
-		B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1, 0x00,
-		B1_DQ9_R_DMDQSIEN_VALID_LAT_B1, 0x0,
-		B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1, 0x0,
-		B1_DQ9_R_DMRXDVS_VALID_LAT_B1, 0x0,
-		B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq4,
-		B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0, 0x03,
-		B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0, 0x03,
-		B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0, 0x35,
-		B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0, 0x35);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq4,
-		B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1, 0x03,
-		B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1, 0x03,
-		B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1, 0x35,
-		B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1, 0x35);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5,
-		B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0, 0x0e,
-		B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 0x0,
-		B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0, 0x0,
-		B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0, 0x0,
-		B0_DQ5_RG_RX_ARDQ_EYE_EN_B0, 0x0,
-		B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0, 0x1,
-		B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5,
-		B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1, 0x0e,
-		B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 0x0,
-		B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1, 0x0,
-		B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1, 0x0,
-		B1_DQ5_RG_RX_ARDQ_EYE_EN_B1, 0x0,
-		B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1, 0x1,
-		B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1, 0x0);
-}
-
-static void sv_algorithm_assistance_lp4_1600(void)
-{
-	SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rdsel_track,
-		SHU_MISC_RDSEL_TRACK_DMDATLAT_I, 0x09,
-		SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK, 0x1,
-		SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN, 0x0,
-		SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG, 0xfeb,
-		SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS, 0x015);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rdat,
-		MISC_SHU_RDAT_DATLAT, 0x09,
-		MISC_SHU_RDAT_DATLAT_DSEL, 0x09,
-		MISC_SHU_RDAT_DATLAT_DSEL_PHY, 0x09);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_phy_rx_ctrl,
-		MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN, 0x1,
-		MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET, 0x2,
-		MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET, 0x2,
-		MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD, 0x0,
-		MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL, 0x1,
-		MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD, 0x0,
-		MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rankctl,
-		MISC_SHU_RANKCTL_RANKINCTL_RXDLY, 0x0,
-		MISC_SHU_RANKCTL_RANK_RXDLY_OPT, 0x1,
-		MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN, 0x1,
-		MISC_SHU_RANKCTL_RANKINCTL_STB, 0x1,
-		MISC_SHU_RANKCTL_RANKINCTL, 0x0,
-		MISC_SHU_RANKCTL_RANKINCTL_ROOT1, 0x0,
-		MISC_SHU_RANKCTL_RANKINCTL_PHY, 0x3);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rank_sel_lat,
-		MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0, 0x2,
-		MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1, 0x2,
-		MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA, 0x2);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqsctl,
-		MISC_SHU_RK_DQSCTL_DQSINCTL, 0x2);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqsctl,
-		MISC_SHU_RK_DQSCTL_DQSINCTL, 0x2);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_dqsien_mck_ui_dly,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x9,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0xd,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x0,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_dqsien_pi_dly,
-		SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x0b);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_dqsien_mck_ui_dly,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0xc,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0x0,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x0,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_dqsien_pi_dly,
-		SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x11);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_dqsien_mck_ui_dly,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x9,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0xd,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x0,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_dqsien_pi_dly,
-		SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x0b);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_dqsien_mck_ui_dly,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0xc,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0x0,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x0,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_dqsien_pi_dly,
-		SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x11);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_odtctrl,
-		MISC_SHU_ODTCTRL_RODTEN, 0x1,
-		MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG, 0x0,
-		MISC_SHU_ODTCTRL_RODT_LAT, 0x1,
-		MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN, 0x0,
-		MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT, 0x0,
-		MISC_SHU_ODTCTRL_FIXRODT, 0x0,
-		MISC_SHU_ODTCTRL_RODTEN_OPT, 0x1,
-		MISC_SHU_ODTCTRL_RODTE2, 0x1,
-		MISC_SHU_ODTCTRL_RODTE, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7,
-		SHU_B0_DQ7_R_DMRANKRXDVS_B0, 0x0,
-		SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0, 0x0,
-		SHU_B0_DQ7_R_DMDQMDBI_SHU_B0, 0x0,
-		SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0, 0x0,
-		SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0, 0x0,
-		SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0, 0x0,
-		SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0, 0x0,
-		SHU_B0_DQ7_R_DMRODTEN_B0, 0x1,
-		SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7,
-		SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0x0,
-		SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0x0,
-		SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0x0,
-		SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0, 0x0,
-		SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0, 0x1,
-		SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0, 0x1,
-		SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0, 0x1,
-		SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7,
-		SHU_B1_DQ7_R_DMRANKRXDVS_B1, 0x0,
-		SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1, 0x0,
-		SHU_B1_DQ7_R_DMDQMDBI_SHU_B1, 0x0,
-		SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1, 0x0,
-		SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1, 0x0,
-		SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1, 0x0,
-		SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7,
-		SHU_B1_DQ7_R_DMRODTEN_B1, 0x1,
-		SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1, 0x0,
-		SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0x0,
-		SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0x0,
-		SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0x0,
-		SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1, 0x0,
-		SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1, 0x1,
-		SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1, 0x1,
-		SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1, 0x1,
-		SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rx_pipe_ctrl,
-		SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_rodten_mck_ui_dly,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x4,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x4,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x0,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_rodten_mck_ui_dly,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x7,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x7,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x0,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_rodten_mck_ui_dly,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x4,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x4,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x0,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_rodten_mck_ui_dly,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x7,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x7,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x0,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_rx_cg_set0,
-		SHU_RX_CG_SET0_DLE_LAST_EXTEND3, 0x0,
-		SHU_RX_CG_SET0_READ_START_EXTEND3, 0x0,
-		SHU_RX_CG_SET0_DLE_LAST_EXTEND2, 0x0,
-		SHU_RX_CG_SET0_READ_START_EXTEND2, 0x0,
-		SHU_RX_CG_SET0_DLE_LAST_EXTEND1, 0x1,
-		SHU_RX_CG_SET0_READ_START_EXTEND1, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rank_sel_stb,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN, 0x1,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23, 0x0,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE, 0x0,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK, 0x1,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK, 0x0,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN, 0x0,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, 0x1,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS, 0x0,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS, 0x0,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS, 0x0,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqscal,
-		MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60,
-		MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1,
-		MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f,
-		MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqscal,
-		MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60,
-		MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1,
-		MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f,
-		MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_ini_uipi,
-		SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x0b,
-		SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x09);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_ini_uipi,
-		SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x0b,
-		SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x09);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_ini_uipi,
-		SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x11,
-		SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x0c);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_ini_uipi,
-		SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x11,
-		SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x0c);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_next_ini_uipi,
-		SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x0b,
-		SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x09,
-		SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x0d);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_next_ini_uipi,
-		SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x0b,
-		SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x09,
-		SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x0d);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_next_ini_uipi,
-		SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x11,
-		SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x0c,
-		SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x10);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_next_ini_uipi,
-		SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x11,
-		SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x0c,
-		SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x10);
-	SET32_BITFIELDS(&ch[0].phy_ao.ca_rk[0].shu_r0_ca_cmd0,
-		SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY, 0x0,
-		SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY, 0x0,
-		SHU_R0_CA_CMD0_RG_ARPI_CS, 0x00,
-		SHU_R0_CA_CMD0_RG_ARPI_CMD, 0x20,
-		SHU_R0_CA_CMD0_RG_ARPI_CLK, 0x00,
-		SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA, 0x0,
-		SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_dq0,
-		SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0,
-		SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0,
-		SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x19,
-		SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x19,
-		SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00,
-		SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0,
-		SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_dq0,
-		SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0,
-		SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0,
-		SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x1f,
-		SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x1f,
-		SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00,
-		SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0,
-		SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.ca_rk[1].shu_r0_ca_cmd0,
-		SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY, 0x0,
-		SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY, 0x0,
-		SHU_R0_CA_CMD0_RG_ARPI_CS, 0x00,
-		SHU_R0_CA_CMD0_RG_ARPI_CMD, 0x20,
-		SHU_R0_CA_CMD0_RG_ARPI_CLK, 0x00,
-		SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA, 0x0,
-		SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_dq0,
-		SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0,
-		SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0,
-		SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x13,
-		SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x13,
-		SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00,
-		SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0,
-		SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_dq0,
-		SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0,
-		SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0,
-		SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x12,
-		SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x12,
-		SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00,
-		SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0,
-		SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_dcm_ctrl0,
-		SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT, 0x1,
-		SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT, 0x3,
-		SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL, 0x5,
-		SHU_DCM_CTRL0_APHYPI_CKCGL_CNT, 0x2,
-		SHU_DCM_CTRL0_APHYPI_CKCGH_CNT, 0x4,
-		SHU_DCM_CTRL0_FASTWAKE2, 0x0,
-		SHU_DCM_CTRL0_FASTWAKE, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_aphy_tx_picg_ctrl,
-		SHU_APHY_TX_PICG_CTRL_TX_PICG_CNT, 0x3,
-		SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P1, 0x1,
-		SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P0, 0x0,
-		SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT, 0x2,
-		SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_aphy_tx_picg_ctrl,
-		SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x1,
-		SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_aphy_tx_picg_ctrl,
-		SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x1,
-		SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_new_xrw2w_ctrl,
-		SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0, 0x0,
-		SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1, 0x0,
-		SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs0,
-		SHU_SELPH_DQS0_TXDLY_DQS0, 0x2,
-		SHU_SELPH_DQS0_TXDLY_DQS1, 0x2,
-		SHU_SELPH_DQS0_TXDLY_DQS2, 0x1,
-		SHU_SELPH_DQS0_TXDLY_DQS3, 0x1,
-		SHU_SELPH_DQS0_TXDLY_OEN_DQS0, 0x1,
-		SHU_SELPH_DQS0_TXDLY_OEN_DQS1, 0x1,
-		SHU_SELPH_DQS0_TXDLY_OEN_DQS2, 0x1,
-		SHU_SELPH_DQS0_TXDLY_OEN_DQS3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs1,
-		SHU_SELPH_DQS1_DLY_DQS0, 0x1,
-		SHU_SELPH_DQS1_DLY_DQS1, 0x1,
-		SHU_SELPH_DQS1_DLY_DQS2, 0x1,
-		SHU_SELPH_DQS1_DLY_DQS3, 0x1,
-		SHU_SELPH_DQS1_DLY_OEN_DQS0, 0x6,
-		SHU_SELPH_DQS1_DLY_OEN_DQS1, 0x6,
-		SHU_SELPH_DQS1_DLY_OEN_DQS2, 0x1,
-		SHU_SELPH_DQS1_DLY_OEN_DQS3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq0,
-		SHURK_SELPH_DQ0_TXDLY_DQ0, 0x2,
-		SHURK_SELPH_DQ0_TXDLY_DQ1, 0x2,
-		SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq1,
-		SHURK_SELPH_DQ1_TXDLY_DQM0, 0x2,
-		SHURK_SELPH_DQ1_TXDLY_DQM1, 0x2,
-		SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq2,
-		SHURK_SELPH_DQ2_DLY_DQ0, 0x1,
-		SHURK_SELPH_DQ2_DLY_DQ1, 0x1,
-		SHURK_SELPH_DQ2_DLY_DQ2, 0x1,
-		SHURK_SELPH_DQ2_DLY_DQ3, 0x1,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x6,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x6,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq3,
-		SHURK_SELPH_DQ3_DLY_DQM0, 0x1,
-		SHURK_SELPH_DQ3_DLY_DQM1, 0x1,
-		SHURK_SELPH_DQ3_DLY_DQM2, 0x1,
-		SHURK_SELPH_DQ3_DLY_DQM3, 0x1,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x6,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x6,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq0,
-		SHURK_SELPH_DQ0_TXDLY_DQ0, 0x2,
-		SHURK_SELPH_DQ0_TXDLY_DQ1, 0x2,
-		SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq1,
-		SHURK_SELPH_DQ1_TXDLY_DQM0, 0x2,
-		SHURK_SELPH_DQ1_TXDLY_DQM1, 0x2,
-		SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq2,
-		SHURK_SELPH_DQ2_DLY_DQ0, 0x2,
-		SHURK_SELPH_DQ2_DLY_DQ1, 0x2,
-		SHURK_SELPH_DQ2_DLY_DQ2, 0x1,
-		SHURK_SELPH_DQ2_DLY_DQ3, 0x1,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x7,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x7,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq3,
-		SHURK_SELPH_DQ3_DLY_DQM0, 0x2,
-		SHURK_SELPH_DQ3_DLY_DQM1, 0x2,
-		SHURK_SELPH_DQ3_DLY_DQM2, 0x1,
-		SHURK_SELPH_DQ3_DLY_DQM3, 0x1,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x7,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x7,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal1,
-		SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x019,
-		SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x01f);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal2,
-		SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x019,
-		SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x01f);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal5,
-		SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x019,
-		SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x01f);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal1,
-		SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x013,
-		SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x012);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal2,
-		SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x013,
-		SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x012);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal5,
-		SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x013,
-		SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x012);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_pi,
-		SHURK_PI_RK0_ARPI_DQ_B1, 0x1f,
-		SHURK_PI_RK0_ARPI_DQ_B0, 0x19,
-		SHURK_PI_RK0_ARPI_DQM_B1, 0x1f,
-		SHURK_PI_RK0_ARPI_DQM_B0, 0x19);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_pi,
-		SHURK_PI_RK0_ARPI_DQ_B1, 0x12,
-		SHURK_PI_RK0_ARPI_DQ_B0, 0x13,
-		SHURK_PI_RK0_ARPI_DQM_B1, 0x12,
-		SHURK_PI_RK0_ARPI_DQM_B0, 0x13);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly0,
-		SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x3c,
-		SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x3c,
-		SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x3c,
-		SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x3c);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly1,
-		SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x3c,
-		SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x3c,
-		SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x3c,
-		SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x3c);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly3,
-		SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x3c,
-		SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00,
-		SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly0,
-		SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x08,
-		SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x08,
-		SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x08,
-		SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x08);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly1,
-		SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x08,
-		SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x08,
-		SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x08,
-		SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x08);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly3,
-		SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x08,
-		SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00,
-		SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00);
-	SET32_BITFIELDS(&ch[0].ao.shu_ac_derating0,
-		SHU_AC_DERATING0_ACDERATEEN, 0x0,
-		SHU_AC_DERATING0_TRRD_DERATE, 0x1,
-		SHU_AC_DERATING0_TRCD_DERATE, 0x4);
-	SET32_BITFIELDS(&ch[0].ao.shu_ac_derating1,
-		SHU_AC_DERATING1_TRPAB_DERATE, 0x3,
-		SHU_AC_DERATING1_TRP_DERATE, 0x2,
-		SHU_AC_DERATING1_TRAS_DERATE, 0x00,
-		SHU_AC_DERATING1_TRC_DERATE, 0x00);
-	SET32_BITFIELDS(&ch[0].ao.shu_ac_derating_05t,
-		SHU_AC_DERATING_05T_TRC_05T_DERATE, 0x0,
-		SHU_AC_DERATING_05T_TRCD_05T_DERATE, 0x0,
-		SHU_AC_DERATING_05T_TRP_05T_DERATE, 0x1,
-		SHU_AC_DERATING_05T_TRPAB_05T_DERATE, 0x1,
-		SHU_AC_DERATING_05T_TRAS_05T_DERATE, 0x1,
-		SHU_AC_DERATING_05T_TRRD_05T_DERATE, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_sref_ctrl,
-		SHU_SREF_CTRL_CKEHCMD, 0x3,
-		SHU_SREF_CTRL_SREF_CK_DLY, 0x3);
-	SET32_BITFIELDS(&ch[0].ao.shu_hmr4_dvfs_ctrl0,
-		SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT, 0x32,
-		SHU_HMR4_DVFS_CTRL0_REFRCNT, 0x000);
-	SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t,
-		SHU_AC_TIME_05T_TRC_05T, 0x0,
-		SHU_AC_TIME_05T_TRFCPB_05T, 0x0,
-		SHU_AC_TIME_05T_TRFC_05T, 0x0,
-		SHU_AC_TIME_05T_TPBR2PBR_05T, 0x0,
-		SHU_AC_TIME_05T_TXP_05T, 0x0,
-		SHU_AC_TIME_05T_TRTP_05T, 0x1,
-		SHU_AC_TIME_05T_TRCD_05T, 0x0,
-		SHU_AC_TIME_05T_TRP_05T, 0x1,
-		SHU_AC_TIME_05T_TRPAB_05T, 0x0,
-		SHU_AC_TIME_05T_TRAS_05T, 0x0,
-		SHU_AC_TIME_05T_TWR_M05T, 0x1,
-		SHU_AC_TIME_05T_TRRD_05T, 0x0,
-		SHU_AC_TIME_05T_TFAW_05T, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t,
-		SHU_AC_TIME_05T_TCKEPRD_05T, 0x0,
-		SHU_AC_TIME_05T_TR2PD_05T, 0x0,
-		SHU_AC_TIME_05T_TWTPD_M05T, 0x1,
-		SHU_AC_TIME_05T_TMRRI_05T, 0x1,
-		SHU_AC_TIME_05T_TMRWCKEL_05T, 0x0,
-		SHU_AC_TIME_05T_BGTRRD_05T, 0x0,
-		SHU_AC_TIME_05T_BGTCCD_05T, 0x0,
-		SHU_AC_TIME_05T_BGTWTR_M05T, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t,
-		SHU_AC_TIME_05T_TR2W_05T, 0x0,
-		SHU_AC_TIME_05T_TWTR_M05T, 0x1,
-		SHU_AC_TIME_05T_XRTR2W_05T, 0x0,
-		SHU_AC_TIME_05T_TMRD_05T, 0x1,
-		SHU_AC_TIME_05T_TMRW_05T, 0x1,
-		SHU_AC_TIME_05T_TMRR2MRW_05T, 0x1,
-		SHU_AC_TIME_05T_TW2MRW_05T, 0x1,
-		SHU_AC_TIME_05T_TR2MRW_05T, 0x0,
-		SHU_AC_TIME_05T_TPBR2ACT_05T, 0x1,
-		SHU_AC_TIME_05T_XRTW2R_M05T, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim_xrt,
-		SHU_ACTIM_XRT_XRTR2R, 0x03,
-		SHU_ACTIM_XRT_XRTR2W, 0x03,
-		SHU_ACTIM_XRT_XRTW2R, 0x3,
-		SHU_ACTIM_XRT_XRTW2W, 0x04);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim0,
-		SHU_ACTIM0_TWTR, 0x04,
-		SHU_ACTIM0_TWR, 0x07,
-		SHU_ACTIM0_TRRD, 0x1,
-		SHU_ACTIM0_TRCD, 0x4,
-		SHU_ACTIM0_CKELCKCNT, 0x2);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim1,
-		SHU_ACTIM1_TRPAB, 0x3,
-		SHU_ACTIM1_TMRWCKEL, 0x4,
-		SHU_ACTIM1_TRP, 0x2,
-		SHU_ACTIM1_TRAS, 0x00,
-		SHU_ACTIM1_TRC, 0x00);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim2,
-		SHU_ACTIM2_TXP, 0x0,
-		SHU_ACTIM2_TMRRI, 0x05,
-		SHU_ACTIM2_TRTP, 0x0,
-		SHU_ACTIM2_TR2W, 0x03,
-		SHU_ACTIM2_TFAW, 0x00);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim3,
-		SHU_ACTIM3_TRFCPB, 0x1a,
-		SHU_ACTIM3_MANTMRR, 0x4,
-		SHU_ACTIM3_TR2MRR, 0x4,
-		SHU_ACTIM3_TRFC, 0x40,
-		SHU_ACTIM3_TWTR_L, 0x00);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim4,
-		SHU_ACTIM4_TXREFCNT, 0x04e,
-		SHU_ACTIM4_TMRR2MRW, 0x07,
-		SHU_ACTIM4_TMRR2W, 0x05,
-		SHU_ACTIM4_TZQCS, 0x10);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim5,
-		SHU_ACTIM5_TR2PD, 0x08,
-		SHU_ACTIM5_TWTPD, 0x09,
-		SHU_ACTIM5_TPBR2PBR, 0x0b,
-		SHU_ACTIM5_TPBR2ACT, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim6,
-		SHU_ACTIM6_TZQLAT2, 0x06,
-		SHU_ACTIM6_TMRD, 0x3,
-		SHU_ACTIM6_TMRW, 0x2,
-		SHU_ACTIM6_TW2MRW, 0x06,
-		SHU_ACTIM6_TR2MRW, 0x09);
-	SET32_BITFIELDS(&ch[0].ao.shu_ckectrl,
-		SHU_CKECTRL_TPDE_05T, 0x1,
-		SHU_CKECTRL_TPDX_05T, 0x0,
-		SHU_CKECTRL_TPDE, 0x1,
-		SHU_CKECTRL_TPDX, 0x1,
-		SHU_CKECTRL_TCKEPRD, 0x1,
-		SHU_CKECTRL_TCKESRX, 0x3);
-	SET32_BITFIELDS(&ch[0].ao.shu_misc,
-		SHU_MISC_REQQUE_MAXCNT, 0x2,
-		SHU_MISC_DCMDLYREF, 0x7,
-		SHU_MISC_DAREFEN, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq8,
-		SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0, 0x0063,
-		SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0, 0x0,
-		SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 0x1,
-		SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 0x1,
-		SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq8,
-		SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1, 0x0063,
-		SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1, 0x0,
-		SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 0x1,
-		SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 0x1,
-		SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq5,
-		SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0, 0x0e,
-		SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0, 0x0,
-		SHU_B0_DQ5_RG_ARPI_FB_B0, 0x00,
-		SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0, 0x0,
-		SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0, 0x0,
-		SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0, 0x5,
-		SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq5,
-		SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1, 0x0e,
-		SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1, 0x0,
-		SHU_B1_DQ5_RG_ARPI_FB_B1, 0x00,
-		SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1, 0x0,
-		SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1, 0x0,
-		SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1, 0x5,
-		SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly0,
-		SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x64,
-		SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x64,
-		SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x64,
-		SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x64);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly1,
-		SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x64,
-		SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x64,
-		SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x64,
-		SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x64);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly2,
-		SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x64,
-		SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x64,
-		SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x64,
-		SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x64);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly3,
-		SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x64,
-		SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x64,
-		SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x64,
-		SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x64);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly4,
-		SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x64,
-		SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x64);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly5,
-		SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x0da,
-		SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x0da);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly0,
-		SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x63,
-		SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x63,
-		SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x63,
-		SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x63);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly1,
-		SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x63,
-		SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x63,
-		SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x63,
-		SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x63);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly2,
-		SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x63,
-		SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x63,
-		SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x63,
-		SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x63);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly3,
-		SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x63,
-		SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x63,
-		SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x63,
-		SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x63);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly4,
-		SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x63,
-		SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x63);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly5,
-		SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x0d9,
-		SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x0d9);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly0,
-		SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0x64,
-		SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0x64,
-		SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0x64,
-		SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0x64);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly1,
-		SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0x64,
-		SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0x64,
-		SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0x64,
-		SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0x64);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly2,
-		SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0x64,
-		SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0x64,
-		SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0x64,
-		SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0x64);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly3,
-		SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0x64,
-		SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0x64,
-		SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0x64,
-		SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0x64);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly4,
-		SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0x64,
-		SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0x64);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly5,
-		SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x0da,
-		SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x0da);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly0,
-		SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0x63,
-		SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0x63,
-		SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0x63,
-		SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0x63);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly1,
-		SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0x63,
-		SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0x63,
-		SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0x63,
-		SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0x63);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly2,
-		SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0x63,
-		SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0x63,
-		SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0x63,
-		SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0x63);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly3,
-		SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0x63,
-		SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0x63,
-		SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0x63,
-		SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0x63);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly4,
-		SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0x63,
-		SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0x63);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly5,
-		SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x0d9,
-		SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x0d9);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9,
-		B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 0x1,
-		B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 0x0,
-		B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0, 0x0,
-		B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0, 0x1,
-		B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0, 0x0,
-		B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0, 0x00,
-		B0_DQ9_R_DMDQSIEN_VALID_LAT_B0, 0x0,
-		B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0, 0x0,
-		B0_DQ9_R_DMRXDVS_VALID_LAT_B0, 0x0,
-		B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9,
-		B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 0x1,
-		B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 0x0,
-		B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1, 0x0,
-		B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1, 0x1,
-		B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1, 0x0,
-		B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1, 0x00,
-		B1_DQ9_R_DMDQSIEN_VALID_LAT_B1, 0x0,
-		B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1, 0x0,
-		B1_DQ9_R_DMRXDVS_VALID_LAT_B1, 0x0,
-		B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq4,
-		B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0, 0x6e,
-		B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0, 0x6e,
-		B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0, 0x24,
-		B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0, 0x24);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq4,
-		B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1, 0x6e,
-		B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1, 0x6e,
-		B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1, 0x24,
-		B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1, 0x24);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5,
-		B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0, 0x0e,
-		B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 0x0,
-		B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0, 0x0,
-		B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0, 0x0,
-		B0_DQ5_RG_RX_ARDQ_EYE_EN_B0, 0x0,
-		B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0, 0x1,
-		B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5,
-		B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1, 0x0e,
-		B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 0x0,
-		B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1, 0x0,
-		B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1, 0x0,
-		B1_DQ5_RG_RX_ARDQ_EYE_EN_B1, 0x0,
-		B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1, 0x1,
-		B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1, 0x0);
-}
-
-static void sv_algorithm_assistance_lp4_3733(void)
-{
-	SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rdsel_track,
-		SHU_MISC_RDSEL_TRACK_DMDATLAT_I, 0x0f,
-		SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK, 0x1,
-		SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN, 0x0,
-		SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG, 0xfd0,
-		SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS, 0x030);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rdat,
-		MISC_SHU_RDAT_DATLAT, 0x0f,
-		MISC_SHU_RDAT_DATLAT_DSEL, 0x0f,
-		MISC_SHU_RDAT_DATLAT_DSEL_PHY, 0x0f);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_phy_rx_ctrl,
-		MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN, 0x1,
-		MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET, 0x2,
-		MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET, 0x2,
-		MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD, 0x1,
-		MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL, 0x1,
-		MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD, 0x2,
-		MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rankctl,
-		MISC_SHU_RANKCTL_RANKINCTL_RXDLY, 0x4,
-		MISC_SHU_RANKCTL_RANK_RXDLY_OPT, 0x1,
-		MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN, 0x1,
-		MISC_SHU_RANKCTL_RANKINCTL_STB, 0x6,
-		MISC_SHU_RANKCTL_RANKINCTL, 0x5,
-		MISC_SHU_RANKCTL_RANKINCTL_ROOT1, 0x5,
-		MISC_SHU_RANKCTL_RANKINCTL_PHY, 0x8);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rank_sel_lat,
-		MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0, 0x2,
-		MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1, 0x2,
-		MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA, 0x2);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqsctl,
-		MISC_SHU_RK_DQSCTL_DQSINCTL, 0x7);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqsctl,
-		MISC_SHU_RK_DQSCTL_DQSINCTL, 0x7);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_dqsien_mck_ui_dly,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x0,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0x4,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x1,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_dqsien_pi_dly,
-		SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x0f);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_dqsien_mck_ui_dly,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x7,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0xb,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x1,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_dqsien_pi_dly,
-		SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x1c);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_dqsien_mck_ui_dly,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x0,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0x4,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x1,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_dqsien_pi_dly,
-		SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x0f);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_dqsien_mck_ui_dly,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x7,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0xb,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x1,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_dqsien_pi_dly,
-		SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x1c);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_odtctrl,
-		MISC_SHU_ODTCTRL_RODTEN, 0x1,
-		MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG, 0x0,
-		MISC_SHU_ODTCTRL_RODT_LAT, 0x7,
-		MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN, 0x0,
-		MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT, 0x0,
-		MISC_SHU_ODTCTRL_FIXRODT, 0x0,
-		MISC_SHU_ODTCTRL_RODTEN_OPT, 0x1,
-		MISC_SHU_ODTCTRL_RODTE2, 0x1,
-		MISC_SHU_ODTCTRL_RODTE, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7,
-		SHU_B0_DQ7_R_DMRANKRXDVS_B0, 0x0,
-		SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0, 0x0,
-		SHU_B0_DQ7_R_DMDQMDBI_SHU_B0, 0x0,
-		SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0, 0x0,
-		SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0, 0x0,
-		SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0, 0x0,
-		SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7,
-		SHU_B0_DQ7_R_DMRODTEN_B0, 0x1,
-		SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0, 0x0,
-		SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0x0,
-		SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0x0,
-		SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0x0,
-		SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0, 0x0,
-		SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0, 0x1,
-		SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0, 0x1,
-		SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0, 0x1,
-		SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7,
-		SHU_B1_DQ7_R_DMRANKRXDVS_B1, 0x0,
-		SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1, 0x0,
-		SHU_B1_DQ7_R_DMDQMDBI_SHU_B1, 0x0,
-		SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1, 0x0,
-		SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1, 0x0,
-		SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1, 0x0,
-		SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7,
-		SHU_B1_DQ7_R_DMRODTEN_B1, 0x1,
-		SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1, 0x0,
-		SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0x0,
-		SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0x0,
-		SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0x0,
-		SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1, 0x0,
-		SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1, 0x1,
-		SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1, 0x1,
-		SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1, 0x1,
-		SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rx_pipe_ctrl,
-		SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_rodten_mck_ui_dly,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x3,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x3,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x0,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_rodten_mck_ui_dly,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x2,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x2,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x1,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_rodten_mck_ui_dly,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x3,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x3,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x0,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_rodten_mck_ui_dly,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x2,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x2,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x1,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_rx_cg_set0,
-		SHU_RX_CG_SET0_DLE_LAST_EXTEND3, 0x0,
-		SHU_RX_CG_SET0_READ_START_EXTEND3, 0x0,
-		SHU_RX_CG_SET0_DLE_LAST_EXTEND2, 0x1,
-		SHU_RX_CG_SET0_READ_START_EXTEND2, 0x1,
-		SHU_RX_CG_SET0_DLE_LAST_EXTEND1, 0x1,
-		SHU_RX_CG_SET0_READ_START_EXTEND1, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rank_sel_stb,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN, 0x1,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23, 0x0,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE, 0x0,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK, 0x1,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK, 0x0,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN, 0x0,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, 0x6,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS, 0x0,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS, 0x0,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS, 0x2,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqscal,
-		MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60,
-		MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1,
-		MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f,
-		MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqscal,
-		MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60,
-		MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1,
-		MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f,
-		MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_ini_uipi,
-		SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x0f,
-		SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x10);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_ini_uipi,
-		SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x0f,
-		SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x10);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_ini_uipi,
-		SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x1c,
-		SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x17);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_ini_uipi,
-		SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x1c,
-		SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x17);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_next_ini_uipi,
-		SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x0f,
-		SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x10,
-		SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x14);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_next_ini_uipi,
-		SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x0f,
-		SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x10,
-		SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x14);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_next_ini_uipi,
-		SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x1c,
-		SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x17,
-		SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x1b);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_next_ini_uipi,
-		SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x1c,
-		SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x17,
-		SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x1b);
-	SET32_BITFIELDS(&ch[0].phy_ao.ca_rk[0].shu_r0_ca_cmd0,
-		SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY, 0x0,
-		SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY, 0x0,
-		SHU_R0_CA_CMD0_RG_ARPI_CS, 0x00,
-		SHU_R0_CA_CMD0_RG_ARPI_CMD, 0x20,
-		SHU_R0_CA_CMD0_RG_ARPI_CLK, 0x00,
-		SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA, 0x0,
-		SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_dq0,
-		SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0,
-		SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0,
-		SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x11,
-		SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x11,
-		SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00,
-		SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0,
-		SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_dq0,
-		SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0,
-		SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0,
-		SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x12,
-		SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x12,
-		SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00,
-		SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0,
-		SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.ca_rk[1].shu_r0_ca_cmd0,
-		SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY, 0x0,
-		SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY, 0x0,
-		SHU_R0_CA_CMD0_RG_ARPI_CS, 0x00,
-		SHU_R0_CA_CMD0_RG_ARPI_CMD, 0x20,
-		SHU_R0_CA_CMD0_RG_ARPI_CLK, 0x00,
-		SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA, 0x0,
-		SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_dq0,
-		SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0,
-		SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0,
-		SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x16,
-		SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x16,
-		SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00,
-		SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0,
-		SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_dq0,
-		SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0,
-		SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0,
-		SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x21,
-		SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x21,
-		SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00,
-		SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0,
-		SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_dcm_ctrl0,
-		SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT, 0x1,
-		SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT, 0x3,
-		SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL, 0x5,
-		SHU_DCM_CTRL0_APHYPI_CKCGL_CNT, 0x2,
-		SHU_DCM_CTRL0_APHYPI_CKCGH_CNT, 0x4,
-		SHU_DCM_CTRL0_FASTWAKE2, 0x0,
-		SHU_DCM_CTRL0_FASTWAKE, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_aphy_tx_picg_ctrl,
-		SHU_APHY_TX_PICG_CTRL_TX_PICG_CNT, 0x3,
-		SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P1, 0x3,
-		SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P0, 0x2,
-		SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT, 0x2,
-		SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_aphy_tx_picg_ctrl,
-		SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x3,
-		SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x3);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_aphy_tx_picg_ctrl,
-		SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x3,
-		SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x3);
-	SET32_BITFIELDS(&ch[0].ao.shu_new_xrw2w_ctrl,
-		SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0, 0x3,
-		SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1, 0x3,
-		SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs0,
-		SHU_SELPH_DQS0_TXDLY_DQS0, 0x4,
-		SHU_SELPH_DQS0_TXDLY_DQS1, 0x4,
-		SHU_SELPH_DQS0_TXDLY_DQS2, 0x1,
-		SHU_SELPH_DQS0_TXDLY_DQS3, 0x1,
-		SHU_SELPH_DQS0_TXDLY_OEN_DQS0, 0x3,
-		SHU_SELPH_DQS0_TXDLY_OEN_DQS1, 0x3,
-		SHU_SELPH_DQS0_TXDLY_OEN_DQS2, 0x1,
-		SHU_SELPH_DQS0_TXDLY_OEN_DQS3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs1,
-		SHU_SELPH_DQS1_DLY_DQS0, 0x1,
-		SHU_SELPH_DQS1_DLY_DQS1, 0x1,
-		SHU_SELPH_DQS1_DLY_DQS2, 0x1,
-		SHU_SELPH_DQS1_DLY_DQS3, 0x1,
-		SHU_SELPH_DQS1_DLY_OEN_DQS0, 0x6,
-		SHU_SELPH_DQS1_DLY_OEN_DQS1, 0x6,
-		SHU_SELPH_DQS1_DLY_OEN_DQS2, 0x1,
-		SHU_SELPH_DQS1_DLY_OEN_DQS3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq0,
-		SHURK_SELPH_DQ0_TXDLY_DQ0, 0x4,
-		SHURK_SELPH_DQ0_TXDLY_DQ1, 0x4,
-		SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x3,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x3,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq1,
-		SHURK_SELPH_DQ1_TXDLY_DQM0, 0x4,
-		SHURK_SELPH_DQ1_TXDLY_DQM1, 0x4,
-		SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x3,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x3,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq2,
-		SHURK_SELPH_DQ2_DLY_DQ0, 0x2,
-		SHURK_SELPH_DQ2_DLY_DQ1, 0x2,
-		SHURK_SELPH_DQ2_DLY_DQ2, 0x1,
-		SHURK_SELPH_DQ2_DLY_DQ3, 0x1,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x7,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x7,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq3,
-		SHURK_SELPH_DQ3_DLY_DQM0, 0x2,
-		SHURK_SELPH_DQ3_DLY_DQM1, 0x2,
-		SHURK_SELPH_DQ3_DLY_DQM2, 0x1,
-		SHURK_SELPH_DQ3_DLY_DQM3, 0x1,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x7,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x7,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq0,
-		SHURK_SELPH_DQ0_TXDLY_DQ0, 0x4,
-		SHURK_SELPH_DQ0_TXDLY_DQ1, 0x4,
-		SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x4,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x4,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq1,
-		SHURK_SELPH_DQ1_TXDLY_DQM0, 0x4,
-		SHURK_SELPH_DQ1_TXDLY_DQM1, 0x4,
-		SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x4,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x4,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq2,
-		SHURK_SELPH_DQ2_DLY_DQ0, 0x3,
-		SHURK_SELPH_DQ2_DLY_DQ1, 0x3,
-		SHURK_SELPH_DQ2_DLY_DQ2, 0x1,
-		SHURK_SELPH_DQ2_DLY_DQ3, 0x1,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x0,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x0,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq3,
-		SHURK_SELPH_DQ3_DLY_DQM0, 0x3,
-		SHURK_SELPH_DQ3_DLY_DQM1, 0x3,
-		SHURK_SELPH_DQ3_DLY_DQM2, 0x1,
-		SHURK_SELPH_DQ3_DLY_DQM3, 0x1,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x0,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x0,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal1,
-		SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x011,
-		SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x012);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal2,
-		SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x011,
-		SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x012);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal5,
-		SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x011,
-		SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x012);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal1,
-		SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x016,
-		SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x021);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal2,
-		SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x016,
-		SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x021);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal5,
-		SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x016,
-		SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x021);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_pi,
-		SHURK_PI_RK0_ARPI_DQ_B1, 0x12,
-		SHURK_PI_RK0_ARPI_DQ_B0, 0x11,
-		SHURK_PI_RK0_ARPI_DQM_B1, 0x12,
-		SHURK_PI_RK0_ARPI_DQM_B0, 0x11);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_pi,
-		SHURK_PI_RK0_ARPI_DQ_B1, 0x21,
-		SHURK_PI_RK0_ARPI_DQ_B0, 0x16,
-		SHURK_PI_RK0_ARPI_DQM_B1, 0x21,
-		SHURK_PI_RK0_ARPI_DQM_B0, 0x16);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly0,
-		SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x08,
-		SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x08,
-		SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x08,
-		SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x08);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly1,
-		SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x08,
-		SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x08,
-		SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x08,
-		SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x08);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly3,
-		SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x08,
-		SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00,
-		SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly0,
-		SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x04,
-		SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x04,
-		SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x04,
-		SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x04);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly1,
-		SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x04,
-		SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x04,
-		SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x04,
-		SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x04);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly3,
-		SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x04,
-		SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00,
-		SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly0,
-		SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x34,
-		SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x34,
-		SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x34,
-		SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x34);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly1,
-		SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x34,
-		SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x34,
-		SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x34,
-		SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x34);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly3,
-		SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x34,
-		SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00,
-		SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly0,
-		SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x08,
-		SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x08,
-		SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x08,
-		SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x08);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly1,
-		SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x08,
-		SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x08,
-		SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x08,
-		SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x08);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly3,
-		SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x08,
-		SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00,
-		SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00);
-	SET32_BITFIELDS(&ch[0].ao.shu_tx_rankctl,
-		SHU_TX_RANKCTL_TXRANKINCTL_TXDLY, 0x2,
-		SHU_TX_RANKCTL_TXRANKINCTL, 0x2,
-		SHU_TX_RANKCTL_TXRANKINCTL_ROOT, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_ac_derating0,
-		SHU_AC_DERATING0_ACDERATEEN, 0x0,
-		SHU_AC_DERATING0_TRRD_DERATE, 0x5,
-		SHU_AC_DERATING0_TRCD_DERATE, 0x9);
-	SET32_BITFIELDS(&ch[0].ao.shu_ac_derating1,
-		SHU_AC_DERATING1_TRPAB_DERATE, 0x9,
-		SHU_AC_DERATING1_TRP_DERATE, 0x8,
-		SHU_AC_DERATING1_TRAS_DERATE, 0x0c,
-		SHU_AC_DERATING1_TRC_DERATE, 0x00);
-	SET32_BITFIELDS(&ch[0].ao.shu_ac_derating_05t,
-		SHU_AC_DERATING_05T_TRC_05T_DERATE, 0x0,
-		SHU_AC_DERATING_05T_TRCD_05T_DERATE, 0x1,
-		SHU_AC_DERATING_05T_TRP_05T_DERATE, 0x0,
-		SHU_AC_DERATING_05T_TRPAB_05T_DERATE, 0x1,
-		SHU_AC_DERATING_05T_TRAS_05T_DERATE, 0x0,
-		SHU_AC_DERATING_05T_TRRD_05T_DERATE, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_sref_ctrl,
-		SHU_SREF_CTRL_CKEHCMD, 0x3,
-		SHU_SREF_CTRL_SREF_CK_DLY, 0x3);
-	SET32_BITFIELDS(&ch[0].ao.shu_hmr4_dvfs_ctrl0,
-		SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT, 0x75,
-		SHU_HMR4_DVFS_CTRL0_REFRCNT, 0x000);
-	SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t,
-		SHU_AC_TIME_05T_TRC_05T, 0x0,
-		SHU_AC_TIME_05T_TRFCPB_05T, 0x0,
-		SHU_AC_TIME_05T_TRFC_05T, 0x1,
-		SHU_AC_TIME_05T_TPBR2PBR_05T, 0x0,
-		SHU_AC_TIME_05T_TXP_05T, 0x1,
-		SHU_AC_TIME_05T_TRTP_05T, 0x0,
-		SHU_AC_TIME_05T_TRCD_05T, 0x1,
-		SHU_AC_TIME_05T_TRP_05T, 0x0,
-		SHU_AC_TIME_05T_TRPAB_05T, 0x1,
-		SHU_AC_TIME_05T_TRAS_05T, 0x1,
-		SHU_AC_TIME_05T_TWR_M05T, 0x1,
-		SHU_AC_TIME_05T_TRRD_05T, 0x0,
-		SHU_AC_TIME_05T_TFAW_05T, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t,
-		SHU_AC_TIME_05T_TCKEPRD_05T, 0x0,
-		SHU_AC_TIME_05T_TR2PD_05T, 0x0,
-		SHU_AC_TIME_05T_TWTPD_M05T, 0x1,
-		SHU_AC_TIME_05T_TMRRI_05T, 0x0,
-		SHU_AC_TIME_05T_TMRWCKEL_05T, 0x0,
-		SHU_AC_TIME_05T_BGTRRD_05T, 0x0,
-		SHU_AC_TIME_05T_BGTCCD_05T, 0x0,
-		SHU_AC_TIME_05T_BGTWTR_M05T, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t,
-		SHU_AC_TIME_05T_TR2W_05T, 0x0,
-		SHU_AC_TIME_05T_TWTR_M05T, 0x0,
-		SHU_AC_TIME_05T_XRTR2W_05T, 0x0,
-		SHU_AC_TIME_05T_TMRD_05T, 0x1,
-		SHU_AC_TIME_05T_TMRW_05T, 0x0,
-		SHU_AC_TIME_05T_TMRR2MRW_05T, 0x1,
-		SHU_AC_TIME_05T_TW2MRW_05T, 0x0,
-		SHU_AC_TIME_05T_TR2MRW_05T, 0x1,
-		SHU_AC_TIME_05T_TPBR2ACT_05T, 0x1,
-		SHU_AC_TIME_05T_XRTW2R_M05T, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim_xrt,
-		SHU_ACTIM_XRT_XRTR2R, 0x03,
-		SHU_ACTIM_XRT_XRTR2W, 0x08,
-		SHU_ACTIM_XRT_XRTW2R, 0x1,
-		SHU_ACTIM_XRT_XRTW2W, 0x05);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim0,
-		SHU_ACTIM0_TWTR, 0x08,
-		SHU_ACTIM0_TWR, 0x0d,
-		SHU_ACTIM0_TRRD, 0x4,
-		SHU_ACTIM0_TRCD, 0x8,
-		SHU_ACTIM0_CKELCKCNT, 0x3);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim1,
-		SHU_ACTIM1_TRPAB, 0x8,
-		SHU_ACTIM1_TMRWCKEL, 0x8,
-		SHU_ACTIM1_TRP, 0x7,
-		SHU_ACTIM1_TRAS, 0x0b,
-		SHU_ACTIM1_TRC, 0x00);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim2,
-		SHU_ACTIM2_TXP, 0x0,
-		SHU_ACTIM2_TMRRI, 0x0c,
-		SHU_ACTIM2_TRTP, 0x2,
-		SHU_ACTIM2_TR2W, 0x09,
-		SHU_ACTIM2_TFAW, 0x0b);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim3,
-		SHU_ACTIM3_TRFCPB, 0x4d,
-		SHU_ACTIM3_MANTMRR, 0x4,
-		SHU_ACTIM3_TR2MRR, 0x4,
-		SHU_ACTIM3_TRFC, 0xa5,
-		SHU_ACTIM3_TWTR_L, 0x00);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim4,
-		SHU_ACTIM4_TXREFCNT, 0x0b5,
-		SHU_ACTIM4_TMRR2MRW, 0x0d,
-		SHU_ACTIM4_TMRR2W, 0x0c,
-		SHU_ACTIM4_TZQCS, 0x28);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim5,
-		SHU_ACTIM5_TR2PD, 0x0e,
-		SHU_ACTIM5_TWTPD, 0x10,
-		SHU_ACTIM5_TPBR2PBR, 0x23,
-		SHU_ACTIM5_TPBR2ACT, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim6,
-		SHU_ACTIM6_TZQLAT2, 0x0e,
-		SHU_ACTIM6_TMRD, 0x7,
-		SHU_ACTIM6_TMRW, 0x5,
-		SHU_ACTIM6_TW2MRW, 0x0a,
-		SHU_ACTIM6_TR2MRW, 0x10);
-	SET32_BITFIELDS(&ch[0].ao.shu_ckectrl,
-		SHU_CKECTRL_TPDE_05T, 0x1,
-		SHU_CKECTRL_TPDX_05T, 0x0,
-		SHU_CKECTRL_TPDE, 0x1,
-		SHU_CKECTRL_TPDX, 0x1,
-		SHU_CKECTRL_TCKEPRD, 0x3,
-		SHU_CKECTRL_TCKESRX, 0x3);
-	SET32_BITFIELDS(&ch[0].ao.shu_misc,
-		SHU_MISC_REQQUE_MAXCNT, 0x2,
-		SHU_MISC_DCMDLYREF, 0x7,
-		SHU_MISC_DAREFEN, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq8,
-		SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0, 0x00e7,
-		SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0, 0x0,
-		SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 0x1,
-		SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 0x1,
-		SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq8,
-		SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1, 0x00e7,
-		SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1, 0x0,
-		SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 0x1,
-		SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 0x1,
-		SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq5,
-		SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0, 0x0e,
-		SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0, 0x0,
-		SHU_B0_DQ5_RG_ARPI_FB_B0, 0x00,
-		SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0, 0x0,
-		SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0, 0x0,
-		SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0, 0x4,
-		SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq5,
-		SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1, 0x0e,
-		SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1, 0x0,
-		SHU_B1_DQ5_RG_ARPI_FB_B1, 0x00,
-		SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1, 0x0,
-		SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1, 0x0,
-		SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1, 0x4,
-		SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly0,
-		SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x6d,
-		SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x6d,
-		SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x6d,
-		SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x6d);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly1,
-		SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x6d,
-		SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x6d,
-		SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x6d,
-		SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x6d);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly2,
-		SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x6d,
-		SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x6d,
-		SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x6d,
-		SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x6d);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly3,
-		SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x6d,
-		SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x6d,
-		SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x6d,
-		SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x6d);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly4,
-		SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x6d,
-		SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x6d);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly5,
-		SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x061,
-		SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x061);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly0,
-		SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x6c,
-		SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x6c,
-		SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x6c,
-		SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x6c);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly1,
-		SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x6c,
-		SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x6c,
-		SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x6c,
-		SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x6c);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly2,
-		SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x6c,
-		SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x6c,
-		SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x6c,
-		SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x6c);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly3,
-		SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x6c,
-		SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x6c,
-		SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x6c,
-		SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x6c);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly4,
-		SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x6c,
-		SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x6c);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly5,
-		SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x060,
-		SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x060);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly0,
-		SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0x6d,
-		SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0x6d,
-		SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0x6d,
-		SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0x6d);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly1,
-		SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0x6d,
-		SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0x6d,
-		SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0x6d,
-		SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0x6d);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly2,
-		SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0x6d,
-		SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0x6d,
-		SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0x6d,
-		SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0x6d);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly3,
-		SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0x6d,
-		SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0x6d,
-		SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0x6d,
-		SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0x6d);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly4,
-		SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0x6d,
-		SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0x6d);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly5,
-		SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x061,
-		SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x061);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly0,
-		SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0x6c,
-		SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0x6c,
-		SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0x6c,
-		SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0x6c);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly1,
-		SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0x6c,
-		SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0x6c,
-		SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0x6c,
-		SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0x6c);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly2,
-		SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0x6c,
-		SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0x6c,
-		SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0x6c,
-		SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0x6c);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly3,
-		SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0x6c,
-		SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0x6c,
-		SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0x6c,
-		SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0x6c);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly4,
-		SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0x6c,
-		SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0x6c);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly5,
-		SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x060,
-		SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x060);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9,
-		B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 0x1,
-		B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 0x0,
-		B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0, 0x0,
-		B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0, 0x1,
-		B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0, 0x0,
-		B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0, 0x00,
-		B0_DQ9_R_DMDQSIEN_VALID_LAT_B0, 0x0,
-		B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0, 0x0,
-		B0_DQ9_R_DMRXDVS_VALID_LAT_B0, 0x0,
-		B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9,
-		B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 0x1,
-		B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 0x0,
-		B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1, 0x0,
-		B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1, 0x1,
-		B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1, 0x0,
-		B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1, 0x00,
-		B1_DQ9_R_DMDQSIEN_VALID_LAT_B1, 0x0,
-		B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1, 0x0,
-		B1_DQ9_R_DMRXDVS_VALID_LAT_B1, 0x0,
-		B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq4,
-		B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0, 0x75,
-		B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0, 0x75,
-		B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0, 0x2d,
-		B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0, 0x2d);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq4,
-		B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1, 0x75,
-		B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1, 0x75,
-		B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1, 0x2d,
-		B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1, 0x2d);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5,
-		B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0, 0x0e,
-		B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 0x0,
-		B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0, 0x0,
-		B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0, 0x0,
-		B0_DQ5_RG_RX_ARDQ_EYE_EN_B0, 0x0,
-		B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0, 0x1,
-		B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5,
-		B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1, 0x0e,
-		B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 0x0,
-		B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1, 0x0,
-		B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1, 0x0,
-		B1_DQ5_RG_RX_ARDQ_EYE_EN_B1, 0x0,
-		B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1, 0x1,
-		B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1, 0x0);
-}
-
-static void sv_algorithm_assistance_lp4_4266(void)
-{
-	SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rdsel_track,
-		SHU_MISC_RDSEL_TRACK_DMDATLAT_I, 0x10,
-		SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK, 0x1,
-		SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN, 0x0,
-		SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG, 0xfcb,
-		SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS, 0x035);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rdat,
-		MISC_SHU_RDAT_DATLAT, 0x10,
-		MISC_SHU_RDAT_DATLAT_DSEL, 0x0f,
-		MISC_SHU_RDAT_DATLAT_DSEL_PHY, 0x0f);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_phy_rx_ctrl,
-		MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN, 0x1,
-		MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET, 0x2,
-		MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET, 0x2,
-		MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD, 0x1,
-		MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL, 0x1,
-		MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD, 0x2,
-		MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rankctl,
-		MISC_SHU_RANKCTL_RANKINCTL_RXDLY, 0x4,
-		MISC_SHU_RANKCTL_RANK_RXDLY_OPT, 0x1,
-		MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN, 0x1,
-		MISC_SHU_RANKCTL_RANKINCTL_STB, 0x6,
-		MISC_SHU_RANKCTL_RANKINCTL, 0x5,
-		MISC_SHU_RANKCTL_RANKINCTL_ROOT1, 0x5,
-		MISC_SHU_RANKCTL_RANKINCTL_PHY, 0x8);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rank_sel_lat,
-		MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0, 0x2,
-		MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1, 0x2,
-		MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA, 0x2);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqsctl,
-		MISC_SHU_RK_DQSCTL_DQSINCTL, 0x7);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqsctl,
-		MISC_SHU_RK_DQSCTL_DQSINCTL, 0x7);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_dqsien_mck_ui_dly,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x1,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0x5,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x1,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_dqsien_pi_dly,
-		SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x01);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_dqsien_mck_ui_dly,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x9,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0xd,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x1,
-		SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_dqsien_pi_dly,
-		SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x08);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_dqsien_mck_ui_dly,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x1,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0x5,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x1,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_dqsien_pi_dly,
-		SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x01);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_dqsien_mck_ui_dly,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x9,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0xd,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x1,
-		SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_dqsien_pi_dly,
-		SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x08);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_odtctrl,
-		MISC_SHU_ODTCTRL_RODTEN, 0x1,
-		MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG, 0x0,
-		MISC_SHU_ODTCTRL_RODT_LAT, 0x7,
-		MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN, 0x0,
-		MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT, 0x0,
-		MISC_SHU_ODTCTRL_FIXRODT, 0x0,
-		MISC_SHU_ODTCTRL_RODTEN_OPT, 0x1,
-		MISC_SHU_ODTCTRL_RODTE2, 0x1,
-		MISC_SHU_ODTCTRL_RODTE, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7,
-		SHU_B0_DQ7_R_DMRANKRXDVS_B0, 0x0,
-		SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0, 0x0,
-		SHU_B0_DQ7_R_DMDQMDBI_SHU_B0, 0x0,
-		SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0, 0x0,
-		SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0, 0x0,
-		SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0, 0x0,
-		SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0, 0x0,
-		SHU_B0_DQ7_R_DMRODTEN_B0, 0x1,
-		SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7,
-		SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0x0,
-		SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0x0,
-		SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0x0,
-		SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0, 0x0,
-		SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0, 0x1,
-		SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0, 0x2,
-		SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0, 0x1,
-		SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7,
-		SHU_B1_DQ7_R_DMRANKRXDVS_B1, 0x0,
-		SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1, 0x0,
-		SHU_B1_DQ7_R_DMDQMDBI_SHU_B1, 0x0,
-		SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1, 0x0,
-		SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1, 0x0,
-		SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1, 0x0,
-		SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7,
-		SHU_B1_DQ7_R_DMRODTEN_B1, 0x1,
-		SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1, 0x0,
-		SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0x0,
-		SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0x0,
-		SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0x0,
-		SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1, 0x0,
-		SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1, 0x1,
-		SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1, 0x2,
-		SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1, 0x1,
-		SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_rodten_mck_ui_dly,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x4,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x4,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x0,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_rodten_mck_ui_dly,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x4,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x4,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x1,
-		SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_rodten_mck_ui_dly,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x4,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x4,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x0,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_rodten_mck_ui_dly,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x4,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x4,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x1,
-		SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_rx_cg_set0,
-		SHU_RX_CG_SET0_DLE_LAST_EXTEND3, 0x0,
-		SHU_RX_CG_SET0_READ_START_EXTEND3, 0x0,
-		SHU_RX_CG_SET0_DLE_LAST_EXTEND2, 0x1,
-		SHU_RX_CG_SET0_READ_START_EXTEND2, 0x1,
-		SHU_RX_CG_SET0_DLE_LAST_EXTEND1, 0x1,
-		SHU_RX_CG_SET0_READ_START_EXTEND1, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rank_sel_stb,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN, 0x1,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23, 0x0,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE, 0x0,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK, 0x1,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK, 0x0,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN, 0x0,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, 0x6,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS, 0x0,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS, 0x0,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS, 0x2,
-		SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqscal,
-		MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60,
-		MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1,
-		MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f,
-		MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqscal,
-		MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60,
-		MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1,
-		MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f,
-		MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_ini_uipi,
-		SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x01,
-		SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x11);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_ini_uipi,
-		SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x01,
-		SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x11);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_ini_uipi,
-		SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x08,
-		SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x19);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_ini_uipi,
-		SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x08,
-		SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x19);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_next_ini_uipi,
-		SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x01,
-		SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x11,
-		SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x15);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_next_ini_uipi,
-		SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x01,
-		SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x11,
-		SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x15);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_next_ini_uipi,
-		SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x08,
-		SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x19,
-		SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x1d);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_next_ini_uipi,
-		SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x08,
-		SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x19,
-		SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x1d);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_dq0,
-		SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0,
-		SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0,
-		SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x13,
-		SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x13,
-		SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00,
-		SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0,
-		SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_dq0,
-		SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0,
-		SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0,
-		SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x16,
-		SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x16,
-		SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00,
-		SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0,
-		SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_dq0,
-		SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0,
-		SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0,
-		SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x2b,
-		SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x2b,
-		SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x01,
-		SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0,
-		SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_dq0,
-		SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0,
-		SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0,
-		SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x2b,
-		SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x2b,
-		SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x01,
-		SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0,
-		SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_dcm_ctrl0,
-		SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT, 0x1,
-		SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT, 0x3,
-		SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL, 0x5,
-		SHU_DCM_CTRL0_APHYPI_CKCGL_CNT, 0x2,
-		SHU_DCM_CTRL0_APHYPI_CKCGH_CNT, 0x4,
-		SHU_DCM_CTRL0_FASTWAKE2, 0x0,
-		SHU_DCM_CTRL0_FASTWAKE, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_aphy_tx_picg_ctrl,
-		SHU_APHY_TX_PICG_CTRL_TX_PICG_CNT, 0x3,
-		SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P1, 0x3,
-		SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P0, 0x3,
-		SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT, 0x2,
-		SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_aphy_tx_picg_ctrl,
-		SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x4,
-		SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x3);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_aphy_tx_picg_ctrl,
-		SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x4,
-		SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x3);
-	SET32_BITFIELDS(&ch[0].ao.shu_new_xrw2w_ctrl,
-		SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0, 0x2,
-		SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1, 0x2,
-		SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs0,
-		SHU_SELPH_DQS0_TXDLY_DQS0, 0x4,
-		SHU_SELPH_DQS0_TXDLY_DQS1, 0x4,
-		SHU_SELPH_DQS0_TXDLY_DQS2, 0x1,
-		SHU_SELPH_DQS0_TXDLY_DQS3, 0x1,
-		SHU_SELPH_DQS0_TXDLY_OEN_DQS0, 0x4,
-		SHU_SELPH_DQS0_TXDLY_OEN_DQS1, 0x4,
-		SHU_SELPH_DQS0_TXDLY_OEN_DQS2, 0x1,
-		SHU_SELPH_DQS0_TXDLY_OEN_DQS3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs1,
-		SHU_SELPH_DQS1_DLY_DQS0, 0x5,
-		SHU_SELPH_DQS1_DLY_DQS1, 0x5,
-		SHU_SELPH_DQS1_DLY_DQS2, 0x1,
-		SHU_SELPH_DQS1_DLY_DQS3, 0x1,
-		SHU_SELPH_DQS1_DLY_OEN_DQS0, 0x2,
-		SHU_SELPH_DQS1_DLY_OEN_DQS1, 0x2,
-		SHU_SELPH_DQS1_DLY_OEN_DQS2, 0x1,
-		SHU_SELPH_DQS1_DLY_OEN_DQS3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq0,
-		SHURK_SELPH_DQ0_TXDLY_DQ0, 0x4,
-		SHURK_SELPH_DQ0_TXDLY_DQ1, 0x4,
-		SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x4,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x4,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq1,
-		SHURK_SELPH_DQ1_TXDLY_DQM0, 0x4,
-		SHURK_SELPH_DQ1_TXDLY_DQM1, 0x4,
-		SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x4,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x4,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq2,
-		SHURK_SELPH_DQ2_DLY_DQ0, 0x6,
-		SHURK_SELPH_DQ2_DLY_DQ1, 0x6,
-		SHURK_SELPH_DQ2_DLY_DQ2, 0x1,
-		SHURK_SELPH_DQ2_DLY_DQ3, 0x1,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x3,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x3,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq3,
-		SHURK_SELPH_DQ3_DLY_DQM0, 0x6,
-		SHURK_SELPH_DQ3_DLY_DQM1, 0x6,
-		SHURK_SELPH_DQ3_DLY_DQM2, 0x1,
-		SHURK_SELPH_DQ3_DLY_DQM3, 0x1,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x3,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x3,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq0,
-		SHURK_SELPH_DQ0_TXDLY_DQ0, 0x4,
-		SHURK_SELPH_DQ0_TXDLY_DQ1, 0x4,
-		SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x4,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x4,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1,
-		SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq1,
-		SHURK_SELPH_DQ1_TXDLY_DQM0, 0x4,
-		SHURK_SELPH_DQ1_TXDLY_DQM1, 0x4,
-		SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x4,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x4,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1,
-		SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq2,
-		SHURK_SELPH_DQ2_DLY_DQ0, 0x7,
-		SHURK_SELPH_DQ2_DLY_DQ1, 0x7,
-		SHURK_SELPH_DQ2_DLY_DQ2, 0x1,
-		SHURK_SELPH_DQ2_DLY_DQ3, 0x1,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x4,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x4,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1,
-		SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq3,
-		SHURK_SELPH_DQ3_DLY_DQM0, 0x7,
-		SHURK_SELPH_DQ3_DLY_DQM1, 0x7,
-		SHURK_SELPH_DQ3_DLY_DQM2, 0x1,
-		SHURK_SELPH_DQ3_DLY_DQM3, 0x1,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x4,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x4,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1,
-		SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal1,
-		SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x013,
-		SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x016);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal2,
-		SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x013,
-		SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x016);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal5,
-		SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x013,
-		SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x016);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal1,
-		SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x02b,
-		SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x02b);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal2,
-		SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x02b,
-		SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x02b);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal5,
-		SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x02b,
-		SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x02b);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_pi,
-		SHURK_PI_RK0_ARPI_DQ_B1, 0x16,
-		SHURK_PI_RK0_ARPI_DQ_B0, 0x13,
-		SHURK_PI_RK0_ARPI_DQM_B1, 0x16,
-		SHURK_PI_RK0_ARPI_DQM_B0, 0x13);
-	SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_pi,
-		SHURK_PI_RK0_ARPI_DQ_B1, 0x2b,
-		SHURK_PI_RK0_ARPI_DQ_B0, 0x2b,
-		SHURK_PI_RK0_ARPI_DQM_B1, 0x2b,
-		SHURK_PI_RK0_ARPI_DQM_B0, 0x2b);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly0,
-		SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x10,
-		SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x10,
-		SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x10,
-		SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x10);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly1,
-		SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x10,
-		SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x10,
-		SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x10,
-		SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x10);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly3,
-		SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x10,
-		SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00,
-		SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly0,
-		SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x04,
-		SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x04,
-		SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x04,
-		SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x04);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly1,
-		SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x04,
-		SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x04,
-		SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x04,
-		SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x04);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly3,
-		SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x04,
-		SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00,
-		SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly0,
-		SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x08,
-		SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x08,
-		SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x08,
-		SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x08);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly1,
-		SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x08,
-		SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x08,
-		SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x08,
-		SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x08);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly3,
-		SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x08,
-		SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00,
-		SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly0,
-		SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x08,
-		SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x08,
-		SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x08,
-		SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x08);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly1,
-		SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x08,
-		SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x08,
-		SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x08,
-		SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x08);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly3,
-		SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x08,
-		SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00,
-		SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00);
-	SET32_BITFIELDS(&ch[0].ao.shu_tx_rankctl,
-		SHU_TX_RANKCTL_TXRANKINCTL_TXDLY, 0x1,
-		SHU_TX_RANKCTL_TXRANKINCTL, 0x1,
-		SHU_TX_RANKCTL_TXRANKINCTL_ROOT, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_ac_derating0,
-		SHU_AC_DERATING0_ACDERATEEN, 0x0,
-		SHU_AC_DERATING0_TRRD_DERATE, 0x5,
-		SHU_AC_DERATING0_TRCD_DERATE, 0xb);
-	SET32_BITFIELDS(&ch[0].ao.shu_ac_derating1,
-		SHU_AC_DERATING1_TRPAB_DERATE, 0xb,
-		SHU_AC_DERATING1_TRP_DERATE, 0x9,
-		SHU_AC_DERATING1_TRAS_DERATE, 0x0f,
-		SHU_AC_DERATING1_TRC_DERATE, 0x00);
-	SET32_BITFIELDS(&ch[0].ao.shu_ac_derating_05t,
-		SHU_AC_DERATING_05T_TRC_05T_DERATE, 0x0,
-		SHU_AC_DERATING_05T_TRCD_05T_DERATE, 0x0,
-		SHU_AC_DERATING_05T_TRP_05T_DERATE, 0x1,
-		SHU_AC_DERATING_05T_TRPAB_05T_DERATE, 0x0,
-		SHU_AC_DERATING_05T_TRAS_05T_DERATE, 0x0,
-		SHU_AC_DERATING_05T_TRRD_05T_DERATE, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_sref_ctrl,
-		SHU_SREF_CTRL_CKEHCMD, 0x3,
-		SHU_SREF_CTRL_SREF_CK_DLY, 0x3);
-	SET32_BITFIELDS(&ch[0].ao.shu_hmr4_dvfs_ctrl0,
-		SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT, 0x86,
-		SHU_HMR4_DVFS_CTRL0_REFRCNT, 0x000);
-	SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t,
-		SHU_AC_TIME_05T_TRC_05T, 0x0,
-		SHU_AC_TIME_05T_TRFCPB_05T, 0x1,
-		SHU_AC_TIME_05T_TRFC_05T, 0x0,
-		SHU_AC_TIME_05T_TPBR2PBR_05T, 0x0,
-		SHU_AC_TIME_05T_TXP_05T, 0x0,
-		SHU_AC_TIME_05T_TRTP_05T, 0x1,
-		SHU_AC_TIME_05T_TRCD_05T, 0x0,
-		SHU_AC_TIME_05T_TRP_05T, 0x1,
-		SHU_AC_TIME_05T_TRPAB_05T, 0x0,
-		SHU_AC_TIME_05T_TRAS_05T, 0x0,
-		SHU_AC_TIME_05T_TWR_M05T, 0x0,
-		SHU_AC_TIME_05T_TRRD_05T, 0x0,
-		SHU_AC_TIME_05T_TFAW_05T, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t,
-		SHU_AC_TIME_05T_TCKEPRD_05T, 0x0,
-		SHU_AC_TIME_05T_TR2PD_05T, 0x1,
-		SHU_AC_TIME_05T_TWTPD_M05T, 0x0,
-		SHU_AC_TIME_05T_TMRRI_05T, 0x0,
-		SHU_AC_TIME_05T_TMRWCKEL_05T, 0x1,
-		SHU_AC_TIME_05T_BGTRRD_05T, 0x0,
-		SHU_AC_TIME_05T_BGTCCD_05T, 0x0,
-		SHU_AC_TIME_05T_BGTWTR_M05T, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t,
-		SHU_AC_TIME_05T_TR2W_05T, 0x0,
-		SHU_AC_TIME_05T_TWTR_M05T, 0x1,
-		SHU_AC_TIME_05T_XRTR2W_05T, 0x0,
-		SHU_AC_TIME_05T_TMRD_05T, 0x0,
-		SHU_AC_TIME_05T_TMRW_05T, 0x1,
-		SHU_AC_TIME_05T_TMRR2MRW_05T, 0x0,
-		SHU_AC_TIME_05T_TW2MRW_05T, 0x0,
-		SHU_AC_TIME_05T_TR2MRW_05T, 0x0,
-		SHU_AC_TIME_05T_TPBR2ACT_05T, 0x0,
-		SHU_AC_TIME_05T_XRTW2R_M05T, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim_xrt,
-		SHU_ACTIM_XRT_XRTR2R, 0x03,
-		SHU_ACTIM_XRT_XRTR2W, 0x08,
-		SHU_ACTIM_XRT_XRTW2R, 0x1,
-		SHU_ACTIM_XRT_XRTW2W, 0x05);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim0,
-		SHU_ACTIM0_TWTR, 0x0a,
-		SHU_ACTIM0_TWR, 0x0f,
-		SHU_ACTIM0_TRRD, 0x3,
-		SHU_ACTIM0_TRCD, 0xa,
-		SHU_ACTIM0_CKELCKCNT, 0x3);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim1,
-		SHU_ACTIM1_TRPAB, 0xa,
-		SHU_ACTIM1_TMRWCKEL, 0x8,
-		SHU_ACTIM1_TRP, 0x8,
-		SHU_ACTIM1_TRAS, 0x0e,
-		SHU_ACTIM1_TRC, 0x00);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim2,
-		SHU_ACTIM2_TXP, 0x1,
-		SHU_ACTIM2_TMRRI, 0x0e,
-		SHU_ACTIM2_TRTP, 0x2,
-		SHU_ACTIM2_TR2W, 0x09,
-		SHU_ACTIM2_TFAW, 0x08);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim3,
-		SHU_ACTIM3_TRFCPB, 0x59,
-		SHU_ACTIM3_MANTMRR, 0x4,
-		SHU_ACTIM3_TR2MRR, 0x4,
-		SHU_ACTIM3_TRFC, 0xbf,
-		SHU_ACTIM3_TWTR_L, 0x00);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim4,
-		SHU_ACTIM4_TXREFCNT, 0x0cf,
-		SHU_ACTIM4_TMRR2MRW, 0x0f,
-		SHU_ACTIM4_TMRR2W, 0x0b,
-		SHU_ACTIM4_TZQCS, 0x2e);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim5,
-		SHU_ACTIM5_TR2PD, 0x0f,
-		SHU_ACTIM5_TWTPD, 0x12,
-		SHU_ACTIM5_TPBR2PBR, 0x29,
-		SHU_ACTIM5_TPBR2ACT, 0x0);
-	SET32_BITFIELDS(&ch[0].ao.shu_actim6,
-		SHU_ACTIM6_TZQLAT2, 0x10,
-		SHU_ACTIM6_TMRD, 0x8,
-		SHU_ACTIM6_TMRW, 0x5,
-		SHU_ACTIM6_TW2MRW, 0x0b,
-		SHU_ACTIM6_TR2MRW, 0x12);
-	SET32_BITFIELDS(&ch[0].ao.shu_ckectrl,
-		SHU_CKECTRL_TPDE_05T, 0x1,
-		SHU_CKECTRL_TPDX_05T, 0x0,
-		SHU_CKECTRL_TPDE, 0x1,
-		SHU_CKECTRL_TPDX, 0x1,
-		SHU_CKECTRL_TCKEPRD, 0x3,
-		SHU_CKECTRL_TCKESRX, 0x3);
-	SET32_BITFIELDS(&ch[0].ao.shu_misc,
-		SHU_MISC_REQQUE_MAXCNT, 0x2,
-		SHU_MISC_DCMDLYREF, 0x7,
-		SHU_MISC_DAREFEN, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq8,
-		SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0, 0x0100,
-		SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0, 0x0,
-		SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 0x1,
-		SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 0x1,
-		SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 0x0,
-		SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq8,
-		SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1, 0x0100,
-		SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1, 0x0,
-		SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 0x1,
-		SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 0x1,
-		SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 0x0,
-		SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq5,
-		SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0, 0x0e,
-		SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0, 0x0,
-		SHU_B0_DQ5_RG_ARPI_FB_B0, 0x00,
-		SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0, 0x0,
-		SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0, 0x0,
-		SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0, 0x3,
-		SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq5,
-		SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1, 0x0e,
-		SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1, 0x0,
-		SHU_B1_DQ5_RG_ARPI_FB_B1, 0x00,
-		SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1, 0x0,
-		SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1, 0x0,
-		SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1, 0x3,
-		SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly0,
-		SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x54,
-		SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x54,
-		SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x54,
-		SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x54);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly1,
-		SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x54,
-		SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x54,
-		SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x54,
-		SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x54);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly2,
-		SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x54,
-		SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x54,
-		SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x54,
-		SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x54);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly3,
-		SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x54,
-		SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x54,
-		SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x54,
-		SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x54);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly4,
-		SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x54,
-		SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x54);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly5,
-		SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x04a,
-		SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x04a);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly0,
-		SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x46,
-		SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x46,
-		SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x46,
-		SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x46);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly1,
-		SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x46,
-		SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x46,
-		SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x46,
-		SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x46);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly2,
-		SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x46,
-		SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x46,
-		SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x46,
-		SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x46);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly3,
-		SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x46,
-		SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x46,
-		SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x46,
-		SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x46);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly4,
-		SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x46,
-		SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x46);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly5,
-		SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x038,
-		SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x038);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly0,
-		SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0xcd,
-		SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0xcd,
-		SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0xcd,
-		SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0xcd);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly1,
-		SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0xcd,
-		SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0xcd,
-		SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0xcd,
-		SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0xcd);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly2,
-		SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0xcd,
-		SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0xcd,
-		SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0xcd,
-		SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0xcd);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly3,
-		SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0xcd,
-		SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0xcd,
-		SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0xcd,
-		SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0xcd);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly4,
-		SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0xcd,
-		SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0xcd);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly5,
-		SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x0bd,
-		SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x0bd);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly0,
-		SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0xfe,
-		SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0xfe,
-		SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0xfe,
-		SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0xfe);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly1,
-		SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0xfe,
-		SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0xfe,
-		SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0xfe,
-		SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0xfe);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly2,
-		SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0xfe,
-		SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0xfe,
-		SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0xfe,
-		SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0xfe);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly3,
-		SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0xfe,
-		SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0xfe,
-		SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0xfe,
-		SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0xfe);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly4,
-		SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0xfe,
-		SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0xfe);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly5,
-		SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x0f4,
-		SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x0f4);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9,
-		B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 0x1,
-		B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 0x0,
-		B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0, 0x0,
-		B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0, 0x1,
-		B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0, 0x0,
-		B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0, 0x00,
-		B0_DQ9_R_DMDQSIEN_VALID_LAT_B0, 0x0,
-		B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0, 0x0,
-		B0_DQ9_R_DMRXDVS_VALID_LAT_B0, 0x0,
-		B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9,
-		B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 0x1,
-		B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 0x0,
-		B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1, 0x0,
-		B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1, 0x1,
-		B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1, 0x0,
-		B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1, 0x00,
-		B1_DQ9_R_DMDQSIEN_VALID_LAT_B1, 0x0,
-		B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1, 0x0,
-		B1_DQ9_R_DMRXDVS_VALID_LAT_B1, 0x0,
-		B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq4,
-		B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0, 0x5a,
-		B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0, 0x5a,
-		B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0, 0x14,
-		B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0, 0x14);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq4,
-		B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1, 0x53,
-		B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1, 0x53,
-		B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1, 0x0d,
-		B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1, 0x0d);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5,
-		B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0, 0x0e,
-		B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 0x0,
-		B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0, 0x0,
-		B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0, 0x0,
-		B0_DQ5_RG_RX_ARDQ_EYE_EN_B0, 0x0,
-		B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0, 0x1,
-		B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5,
-		B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1, 0x0e,
-		B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 0x0,
-		B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1, 0x0,
-		B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1, 0x0,
-		B1_DQ5_RG_RX_ARDQ_EYE_EN_B1, 0x0,
-		B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1, 0x1,
-		B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1, 0x0);
-}
-
-static u32 get_write_latency_by_mr(u8 mr_wl)
-{
-	u32 write_latency;
-
-	switch (mr_wl) {
-	case 0:
-		write_latency = 4;
-		break;
-	case 1:
-		write_latency = 6;
-		break;
-	case 2:
-		write_latency = 8;
-		break;
-	case 3:
-		write_latency = 10;
-		break;
-	case 4:
-		write_latency = 12;
-		break;
-	case 5:
-		write_latency = 14;
-		break;
-	case 6:
-		write_latency = 16;
-		break;
-	case 7:
-		write_latency = 18;
-		break;
-	default:
-		dramc_err("error: unexpected mr_wl: %x\n", mr_wl);
-		return 0;
-	}
-
-	dramc_info("mr_wl: %x map to WriteLatency: %d\n", mr_wl, write_latency);
-	return write_latency;
-}
-
-static void tx_path_algorithm(const struct ddr_cali *cali)
-{
-	u8 write_latency, wl_mr;
-	const u8 ckr = 1;
-	u8 dqs_total_ui;
-	u8 dqs_oe_total_ui;
-	u8 dqs_mck, dqs_ui;
-	u8 dqs_oe_mck, dqs_oe_ui;
-	u8 shift;
-	const u8 tx_dq_oe_shift = 3;
-
-	wl_mr = (cali->mr_value->mr02[get_fsp(cali)] & 0x3f) >> 3;
-	shift = get_mck2ui_div_shift(cali);
-	write_latency = get_write_latency_by_mr(wl_mr);
-	dqs_total_ui = write_latency * ckr * 2 + 1;
-
-	dqs_oe_total_ui = dqs_total_ui - tx_dq_oe_shift;
-	dqs_ui = dqs_total_ui - ((dqs_total_ui >> shift) << shift);
-	dqs_mck = dqs_total_ui >> shift;
-	dqs_oe_ui = dqs_oe_total_ui - ((dqs_oe_total_ui >> shift) << shift);
-	dqs_oe_mck = dqs_oe_total_ui >> shift;
-	dramc_dbg("[TX_path_calculate] write_latency=%u, DQS_TotalUI=%u\n",
-		write_latency, dqs_total_ui);
-	dramc_dbg("[TX_path_calculate] DQS = (%u,%u) DQS_OE = (%u,%u)\n",
-		dqs_mck, dqs_ui, dqs_oe_mck, dqs_oe_ui);
-
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-		SET32_BITFIELDS(&ch[chn].ao.shu_selph_dqs0,
-			SHU_SELPH_DQS0_TXDLY_DQS0, dqs_mck,
-			SHU_SELPH_DQS0_TXDLY_DQS1, dqs_mck,
-			SHU_SELPH_DQS0_TXDLY_OEN_DQS0, dqs_oe_mck,
-			SHU_SELPH_DQS0_TXDLY_OEN_DQS1, dqs_oe_mck);
-		SET32_BITFIELDS(&ch[chn].ao.shu_selph_dqs1,
-			SHU_SELPH_DQS1_DLY_DQS0, dqs_ui,
-			SHU_SELPH_DQS1_DLY_DQS1, dqs_ui,
-			SHU_SELPH_DQS1_DLY_OEN_DQS0, dqs_oe_ui,
-			SHU_SELPH_DQS1_DLY_OEN_DQS1, dqs_oe_ui);
-	}
-}
-
-static void replace_dv_init(const struct ddr_cali *cali)
-{
-	bool is_4266;
-	u8 dq_hyst_sel, ca_hyst_sel;
-	u8 dq_cap_sel, ca_cap_sel;
-	u8 dq_bw_sel_b0 = 0, dq_bw_sel_b1 = 0, ca_bw_sel_ca = 0, clk_bw_sel_ca = 0;
-
-	dram_freq_grp freq_group = cali->freq_group;
-
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5,
-		B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1, 0);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5,
-		B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0, 0);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_rxdvs0,
-		B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0, 0,
-		B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0, 0);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_rxdvs0,
-		B1_RXDVS0_R_RX_DLY_TRACK_ENA_B1, 0,
-		B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1, 0);
-
-	for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) {
-		SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].rk[rk].rk_b0_rxdvs2,
-			RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0, 0,
-			RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0, 0,
-			RK_B0_RXDVS2_R_RK0_DVS_MODE_B0, 0);
-		SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].rk[rk].rk_b0_rxdvs2,
-			RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1, 0,
-			RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1, 0,
-			RK_B1_RXDVS2_R_RK0_DVS_MODE_B1, 0);
-	}
-
-	SET32_BITFIELDS(&ch[0].ao.cbt_wlev_ctrl1, CBT_WLEV_CTRL1_CATRAINLAT, 0);
-	SET32_BITFIELDS(&ch[0].ao.swcmd_ctrl1, SWCMD_CTRL1_WRFIFO_MODE2, 0);
-
-	u32 bc_bak = dramc_get_broadcast();
-	dramc_set_broadcast(DRAMC_BROADCAST_OFF);
-
-	switch (freq_group) {
-	case DDRFREQ_400:
-	case DDRFREQ_600:
-	case DDRFREQ_800:
-	case DDRFREQ_933:
-		dq_cap_sel = 0x18;
-		ca_cap_sel = 0x18;
-		break;
-	case DDRFREQ_1200:
-		dq_cap_sel = 0x14;
-		ca_cap_sel = 0x14;
-		break;
-	case DDRFREQ_1600:
-		dq_cap_sel = 0x4;
-		ca_cap_sel = 0x4;
-		break;
-	case DDRFREQ_2133:
-		dq_cap_sel = 0x2;
-		ca_cap_sel = 0x2;
-		break;
-	default:
-		die("Invalid DDR frequency group %u\n", freq_group);
-		return;
-	}
-
-	if (freq_group <= DDRFREQ_933) {
-		dq_hyst_sel = 0x1;
-		ca_hyst_sel = 0x1;
-	} else {
-		dq_hyst_sel = 0x0;
-		ca_hyst_sel = 0x0;
-	}
-
-	if (freq_group <= DDRFREQ_1200)
-		clk_bw_sel_ca = 1;
-
-	is_4266 = freq_group >= DDRFREQ_2133;
-	if (is_4266) {
-		dq_bw_sel_b0 = 1;
-		dq_bw_sel_b1 = 1;
-		ca_bw_sel_ca = 1;
-	}
-
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-		SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq6,
-			SHU_B0_DQ6_RG_ARPI_HYST_SEL_B0, dq_hyst_sel,
-			SHU_B0_DQ6_RG_ARPI_CAP_SEL_B0, dq_cap_sel);
-		SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq6,
-			SHU_B1_DQ6_RG_ARPI_HYST_SEL_B1, dq_hyst_sel,
-			SHU_B1_DQ6_RG_ARPI_CAP_SEL_B1, dq_cap_sel);
-		SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd6,
-			SHU_CA_CMD6_RG_ARPI_HYST_SEL_CA, ca_hyst_sel,
-			SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA, ca_cap_sel);
-		SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq2,
-			SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B0, is_4266,
-			SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B0, is_4266,
-			SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B0, 0,
-			SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B0, 0);
-		SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq2,
-			SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1, is_4266,
-			SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B1, is_4266,
-			SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B1, 0,
-			SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B1, 0);
-		SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd2,
-			SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CLK_CA, is_4266,
-			SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CA_CA, is_4266,
-			SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_FORCE_CLK_CA, 0,
-			SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_CA_FORCE_CA, 0);
-		SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_rx_pipe_ctrl,
-			SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN, 0x0);
-		write32(&ch[chn].phy_ao.misc_dbg_irq_ctrl1, 0x0);
-		write32(&ch[chn].phy_ao.misc_dbg_irq_ctrl4, 0x0);
-		write32(&ch[chn].phy_ao.misc_dbg_irq_ctrl7, 0x0);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rx_cg_ctrl,
-			MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY, 0,
-			MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY, 2,
-			MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT, 0,
-			MISC_SHU_RX_CG_CTRL_RX_DCM_OPT, 0);
-		SET32_BITFIELDS(&ch[chn].ao.hmr4, HMR4_MR4INT_LIMITEN, 0);
-		SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFPEND_OPT1, 0);
-		SET32_BITFIELDS(&ch[chn].ao.refctrl3, REFCTRL3_REF_DERATING_EN, 0);
-		SET32_BITFIELDS(&ch[chn].ao.dramc_irq_en,
-			DRAMC_IRQ_EN_DRAMC_IRQ_EN_RSV, 0x3fff,
-			DRAMC_IRQ_EN_MR4INT_EN, 0x0);
-		SET32_BITFIELDS(&ch[chn].ao.shu_conf0, SHU_CONF0_PBREFEN, 0);
-		SET32_BITFIELDS(&ch[chn].phy_ao.ca_tx_mck,
-			CA_TX_MCK_R_DMRESET_FRPHY_OPT, 0x1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl2,
-			MISC_DVFSCTL2_RG_ADA_MCK8X_EN_SHUFFLE, 0x1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, MISC_IMPCAL_IMPBINARY, 0x1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq10,
-			SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0, 0x1,
-			SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0, 0x1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq10,
-			SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1, 0x1,
-			SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1, 0x1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq8,
-			SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 1,
-			SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 1,
-			SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 1,
-			SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 1,
-			SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 1,
-			SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 1,
-			SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 1,
-			SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 1,
-			SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 1,
-			SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 1,
-			SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq8,
-			SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 1,
-			SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 1,
-			SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 1,
-			SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 1,
-			SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 1,
-			SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 1,
-			SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 1,
-			SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 1,
-			SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 1,
-			SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 1,
-			SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dll2,
-			SHU_B0_DLL2_RG_ARDQ_REV_B0, 0x1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dll2,
-			SHU_B1_DLL2_RG_ARDQ_REV_B1, 0x1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll2,
-			SHU_CA_DLL2_RG_ARCMD_REV, 0x1);
-		SET32_BITFIELDS(&ch[chn].ao.dummy_rd, DUMMY_RD_DQSG_DMYRD_EN, 0);
-		SET32_BITFIELDS(&ch[chn].ao.dramc_dbg_sel1,
-			DRAMC_DBG_SEL1_DEBUG_SEL_0, 0x1e);
-		SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl2, SWCMD_CTRL2_RTSWCMD_AGE, 0x20);
-		SET32_BITFIELDS(&ch[chn].ao.rtmrw_ctrl0, RTMRW_CTRL0_RTMRW_AGE, 0x20);
-		SET32_BITFIELDS(&ch[chn].ao.dllfrz_ctrl,
-			DLLFRZ_CTRL_DLLFRZ, 0,
-			DLLFRZ_CTRL_DLLFRZ_MON_PBREF_OPT, 0);
-		SET32_BITFIELDS(&ch[chn].ao.mpc_ctrl,
-			MPC_CTRL_RTSWCMD_HPRI_EN, 1,
-			MPC_CTRL_RTMRW_HPRI_EN, 1);
-		SET32_BITFIELDS(&ch[chn].ao.hw_mrr_fun,
-			HW_MRR_FUN_R2MRRHPRICTL, 0,
-			HW_MRR_FUN_TR2MRR_ENA, 0);
-		SET32_BITFIELDS(&ch[chn].ao.actiming_ctrl,
-			ACTIMING_CTRL_REFNA_OPT, 1,
-			ACTIMING_CTRL_SEQCLKRUN3, 1);
-		SET32_BITFIELDS(&ch[chn].ao.ckectrl, CKECTRL_RUNTIMEMRRCKEFIX, 1);
-		SET32_BITFIELDS(&ch[chn].ao.dvfs_ctrl0,
-			DVFS_CTRL0_DVFS_SYNC_MASK, 0,
-			DVFS_CTRL0_R_DVFS_SREF_OPT, 1);
-		SET32_BITFIELDS(&ch[chn].ao.dvfs_timing_ctrl1,
-			DVFS_TIMING_CTRL1_SHU_PERIOD_GO_ZERO_CNT, 1);
-		SET32_BITFIELDS(&ch[chn].ao.hmr4,
-			HMR4_REFRCNT_OPT, 1,
-			HMR4_REFR_PERIOD_OPT, 0,
-			HMR4_SPDR_MR4_OPT, 1,
-			HMR4_HMR4_TOG_OPT, 0);
-		SET32_BITFIELDS(&ch[chn].ao.rx_set0, RX_SET0_SMRR_UPD_OLD, 0);
-		SET32_BITFIELDS(&ch[chn].ao.dramctrl, DRAMCTRL_SHORTQ_OPT, 1);
-		SET32_BITFIELDS(&ch[chn].ao.misctl0,
-			MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS, 1);
-		SET32_BITFIELDS(&ch[chn].ao.perfctl0, PERFCTL0_EBG_EN, 0);
-		SET32_BITFIELDS(&ch[chn].ao.clkar,
-			CLKAR_REQQUECLKRUN, 1,
-			CLKAR_REQQUE_PACG_DIS, 0x7fff);
-		SET32_BITFIELDS(&ch[chn].ao.refctrl0,
-			REFCTRL0_PBREF_BK_REFA_ENA, 0,
-			REFCTRL0_PBREF_BK_REFA_NUM, 0);
-		SET32_BITFIELDS(&ch[chn].ao.refctrl1,
-			REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA, 0);
-		SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFPB2AB_IGZQCS, 0);
-		SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFPENDINGINT_OPT1, 1);
-		SET32_BITFIELDS(&ch[chn].ao.ref_bounce1,
-			REF_BOUNCE1_REFRATE_DEBOUNCE_TH, 5);
-		SET32_BITFIELDS(&ch[chn].ao.refpend2, REFPEND2_MPENDREFCNT_TH8, 8);
-		SET32_BITFIELDS(&ch[chn].ao.scsmctrl, SCSMCTRL_SC_PG_MAN_DIS, 0);
-		SET32_BITFIELDS(&ch[chn].ao.scsmctrl_cg,
-			SCSMCTRL_CG_SCSM_CGAR, 1,
-			SCSMCTRL_CG_SCARB_SM_CGAR, 1);
-		SET32_BITFIELDS(&ch[chn].ao.rtswcmd_cnt,
-			RTSWCMD_CNT_RTSWCMD_CNT, 0x30);
-		SET32_BITFIELDS(&ch[chn].ao.dramc_irq_en,
-			DRAMC_IRQ_EN_DRAMC_IRQ_EN_RSV, 0x3fff);
-		SET32_BITFIELDS(&ch[chn].ao.shu_dcm_ctrl0,
-			SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT, 1);
-		SET32_BITFIELDS(&ch[chn].ao.shu_hmr4_dvfs_ctrl0,
-			SHU_HMR4_DVFS_CTRL0_REFRCNT, 0x1ff,
-			SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT, 0);
-		SET32_BITFIELDS(&ch[chn].ao.shu_hwset_vrcg,
-			SHU_HWSET_VRCG_VRCGDIS_PRDCNT, 11);
-		SET32_BITFIELDS(&ch[chn].ao.shu_misc, SHU_MISC_REQQUE_MAXCNT, 2);
-		SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dll_arpi4,
-			B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B0, 1,
-			B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B0, 1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dll_arpi4,
-			B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B1, 1,
-			B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B1, 1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.ca_dll_arpi4,
-			CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CLK_CA, 1,
-			CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CA_CA, 1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd11,
-			CA_CMD11_RG_RRESETB_DRVN, 0xa,
-			CA_CMD11_RG_RRESETB_DRVP, 0xa);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl2,
-			MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL, 0x1f);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl9,
-			MISC_CG_CTRL9_RG_MCK4X_O_FB_CK_CG_OFF, 0,
-			MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_O_OFF, 0,
-			MISC_CG_CTRL9_RG_MCK4X_O_OPENLOOP_MODE_EN, 0,
-			MISC_CG_CTRL9_RG_MCK4X_Q_FB_CK_CG_OFF, 0,
-			MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_Q_OFF, 0,
-			MISC_CG_CTRL9_RG_MCK4X_Q_OPENLOOP_MODE_EN, 0,
-			MISC_CG_CTRL9_RG_MCK4X_I_FB_CK_CG_OFF, 0,
-			MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_I_OFF, 0,
-			MISC_CG_CTRL9_RG_MCK4X_I_OPENLOOP_MODE_EN, 0,
-			MISC_CG_CTRL9_RG_M_CK_OPENLOOP_MODE_EN, 0);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl2,
-			MISC_DVFSCTL2_RG_ADA_MCK8X_EN_SHUFFLE, 1,
-			MISC_DVFSCTL2_RG_DLL_SHUFFLE, 0);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl3,
-			MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_BCLK, 0x10,
-			MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE, 1,
-			MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI, 3,
-			MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_BCLK, 1,
-			MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_MCLK, 1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_ddr_reserve,
-			MISC_DDR_RESERVE_WDT_CONF_ISO_CNT, 0xf);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_imp_ctrl1,
-			MISC_IMP_CTRL1_RG_RIMP_SUS_ECO_OPT, 1,
-			MISC_IMP_CTRL1_IMP_ABN_LAT_CLR, 1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal,
-			MISC_IMPCAL_IMPCAL_BYPASS_UP_CA_DRV, 1,
-			MISC_IMPCAL_IMPCAL_DRVUPDOPT, 1,
-			MISC_IMPCAL_IMPBINARY, 1,
-			MISC_IMPCAL_DQDRVSWUPD, 1,
-			MISC_IMPCAL_DRVCGWREF, 0);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_dutyscan1,
-			MISC_DUTYSCAN1_EYESCAN_DQS_OPT, 1,
-			MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN, 1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfs_emi_clk,
-			MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY, 0);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl0,
-			MISC_CTRL0_IDLE_DCM_CHB_CDC_ECO_OPT, 0,
-			MISC_CTRL0_IMPCAL_CDC_ECO_OPT, 1,
-			MISC_CTRL0_IMPCAL_LP_ECO_OPT, 1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl4,
-			MISC_CTRL4_R_OPT2_CG_CS, 0,
-			MISC_CTRL4_R_OPT2_CG_CLK, 0,
-			MISC_CTRL4_R_OPT2_CG_CMD, 0,
-			MISC_CTRL4_R_OPT2_CG_DQSIEN, 0,
-			MISC_CTRL4_R_OPT2_CG_DQ, 0,
-			MISC_CTRL4_R_OPT2_CG_DQS, 0,
-			MISC_CTRL4_R_OPT2_CG_DQM, 0,
-			MISC_CTRL4_R_OPT2_CG_MCK, 0,
-			MISC_CTRL4_R_OPT2_MPDIV_CG, 0);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl6,
-			MISC_CTRL6_RG_ADA_MCK8X_EN_SHU_OPT, 1,
-			MISC_CTRL6_RG_PHDET_EN_SHU_OPT, 1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_rx_autok_cfg0,
-			MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN, 1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq1,
-			SHU_B0_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B0, 1,
-			SHU_B0_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B0, 1,
-			SHU_B0_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B0, 1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq1,
-			SHU_B1_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B1, 1,
-			SHU_B1_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B1, 1,
-			SHU_B1_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B1, 1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq10,
-			SHU_B0_DQ10_RG_RX_ARDQS_BW_SEL_B0, 1,
-			SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0, 1,
-			SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0, 1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq10,
-			SHU_B1_DQ10_RG_RX_ARDQS_BW_SEL_B1, 1,
-			SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1, 1,
-			SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1, 1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq11,
-			SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0, dq_bw_sel_b0);
-		SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq11,
-			SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1, dq_bw_sel_b1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd11,
-			SHU_CA_CMD11_RG_RX_ARCA_BW_SEL_CA, ca_bw_sel_ca);
-		SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd10,
-			SHU_CA_CMD10_RG_RX_ARCLK_BW_SEL_CA, clk_bw_sel_ca);
-		SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd1,
-			SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA, 1,
-			SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA, 1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd8,
-			SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA, 1,
-			SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA, 1,
-			SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA, 1,
-			SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA, 1,
-			SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA, 1,
-			SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA, 1,
-			SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA, 1,
-			SHU_CA_CMD8_R_RMRODTEN_CG_IG_CA, 1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd12,
-			SHU_CA_CMD12_RG_RIMP_REV, 0);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_impedamce_upd_dis1,
-			MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_ODTN_UPD_DIS, 1,
-			MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVN_UPD_DIS, 1,
-			MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVP_UPD_DIS, 1,
-			MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_ODTN_UPD_DIS, 1,
-			MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVN_UPD_DIS, 1,
-			MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVP_UPD_DIS, 1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rx_cg_ctrl,
-			MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY, 0,
-			MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY, 2,
-			MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT, 0,
-			MISC_SHU_RX_CG_CTRL_RX_DCM_OPT, 0);
-	}
-
-	dramc_set_broadcast(bc_bak);
-}
-
-static void rx_picg_setting(const struct ddr_cali *cali)
-{
-	u8 talk_lat = (get_div_mode(cali) == DIV4_MODE) ? 1 : 0;
-
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_stbcal,
-		MISC_SHU_STBCAL_STBCALEN, 0);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_stbcal,
-		MISC_SHU_STBCAL_STB_SELPHCALEN, 0);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal1,
-		MISC_STBCAL1_STBCNT_SHU_RST_EN, 1);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal2,
-		MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN, 1);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_stbcal,
-		MISC_SHU_STBCAL_DQSIEN_PICG_MODE, 1);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_rx_in_gate_en_ctrl,
-		MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT, 1);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_rx_in_buff_en_ctrl,
-		MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT, 1);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal2,
-		MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN, 0);
-	for (u8 rk = 0; rk < cali->support_ranks; rk++)
-		SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[rk].misc_shu_rk_dqsien_picg_ctrl,
-			MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT, talk_lat,
-			MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT, 0);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_rx_in_buff_en_ctrl,
-		MISC_RX_IN_BUFF_EN_CTRL_DIS_IN_BUFF_EN, 0,
-		MISC_RX_IN_BUFF_EN_CTRL_FIX_IN_BUFF_EN, 0,
-		MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_4BYTE_EN, 0);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_rx_in_gate_en_ctrl,
-		MISC_RX_IN_GATE_EN_CTRL_DIS_IN_GATE_EN, 0,
-		MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN, 0,
-		MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_4BYTE_EN, 0);
-}
-
-static void dqs_stb_settings(void)
-{
-	u32 dqsien_mode = 1;
-
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_stbcal,
-		MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE, dqsien_mode);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq10,
-		SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0, dqsien_mode);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq10,
-		SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1, dqsien_mode);
-}
-
-static void rodt_settings(const struct ddr_cali *cali)
-{
-	u8 vref_sel;
-	u8 odt_onoff = get_odt_state(cali);
-	if (get_odt_state(cali) == ODT_ON)
-		vref_sel = 0x2c;
-	else
-		vref_sel = 0x37;
-
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5,
-		B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 1);
-	SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5,
-		B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_vref,
-		SHU_B0_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B0, !odt_onoff);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_vref,
-		SHU_B1_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B1, !odt_onoff);
-
-	for (u8 rk = 0; rk < cali->support_ranks; rk++) {
-		SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[rk].shu_b0_phy_vref_sel,
-			RG_RX_ARDQ_VREF_SEL_LB_B0, vref_sel,
-			RG_RX_ARDQ_VREF_SEL_UB_B0, vref_sel);
-		SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[rk].shu_b0_phy_vref_sel,
-			RG_RX_ARDQ_VREF_SEL_LB_B1, vref_sel,
-			RG_RX_ARDQ_VREF_SEL_UB_B1, vref_sel);
-	}
-
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_vref,
-		SHU_B0_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B0, 1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_vref,
-		SHU_B1_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B1, 1);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_odtctrl, MISC_SHU_ODTCTRL_RODTEN, 1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, SHU_B0_DQ7_R_DMRODTEN_B0, 1);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, SHU_B1_DQ7_R_DMRODTEN_B1, 1);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rodtenstb,
-		MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN, 1,
-		MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL, 1,
-		MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME, 0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq13,
-		SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0, !odt_onoff);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq13,
-		SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1, !odt_onoff);
-	SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd13,
-		SHU_CA_CMD13_RG_TX_ARCA_IO_ODT_DIS_CA, !odt_onoff);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq13,
-		SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0, 0,
-		SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0, 0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq14,
-		SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0, 0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq13,
-		SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1, 0,
-		SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1, 0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq14,
-		SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1, 0);
-}
-
-void dramc_cmd_ui_delay_setting(u8 chn, u8 value)
-{
-	SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca7,
-		SHU_SELPH_CA7_DLY_RA0, value,
-		SHU_SELPH_CA7_DLY_RA1, value,
-		SHU_SELPH_CA7_DLY_RA2, value,
-		SHU_SELPH_CA7_DLY_RA3, value,
-		SHU_SELPH_CA7_DLY_RA4, value,
-		SHU_SELPH_CA7_DLY_RA5, value,
-		SHU_SELPH_CA7_DLY_RA6, value);
-	SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca5, SHU_SELPH_CA5_DLY_CKE, value);
-	SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca6, SHU_SELPH_CA6_DLY_CKE1, value);
-}
-
-void cbt_delay_ca_clk(u8 chn, u8 rank, s32 delay)
-{
-	if (delay < 0)
-		/* Set CLK delay */
-		SET32_BITFIELDS(&ch[chn].phy_ao.ca_rk[rank].shu_r0_ca_cmd0,
-			SHU_R0_CA_CMD0_RG_ARPI_CMD, 0,
-			SHU_R0_CA_CMD0_RG_ARPI_CLK, -delay,
-			SHU_R0_CA_CMD0_RG_ARPI_CS, -delay);
-	else
-		/* Set CA output delay */
-		SET32_BITFIELDS(&ch[chn].phy_ao.ca_rk[rank].shu_r0_ca_cmd0,
-			SHU_R0_CA_CMD0_RG_ARPI_CMD, delay,
-			SHU_R0_CA_CMD0_RG_ARPI_CLK, 0,
-			SHU_R0_CA_CMD0_RG_ARPI_CS, 0);
-}
-
-static void set_mck_8x_low_pwr_option(void)
-{
-	const u32 mck_8x_mode = 1;
-
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_lp_ctrl,
-		MISC_LP_CTRL_RG_SC_ARPI_RESETB_8X_SEQ_LP_SEL, mck_8x_mode,
-		MISC_LP_CTRL_RG_ADA_MCK8X_8X_SEQ_LP_SEL, mck_8x_mode,
-		MISC_LP_CTRL_RG_AD_MCK8X_8X_SEQ_LP_SEL, mck_8x_mode,
-		MISC_LP_CTRL_RG_MIDPI_EN_8X_SEQ_LP_SEL, mck_8x_mode,
-		MISC_LP_CTRL_RG_MIDPI_CKDIV4_EN_8X_SEQ_LP_SEL, mck_8x_mode,
-		MISC_LP_CTRL_RG_MCK8X_CG_SRC_LP_SEL, mck_8x_mode,
-		MISC_LP_CTRL_RG_MCK8X_CG_SRC_AND_LP_SEL, mck_8x_mode);
-}
-
-static void update_initial_settings(const struct ddr_cali *cali)
-{
-	const u8 ca_pi = 0, ca_ui = 1;
-	u8 fsp = get_fsp(cali);
-	dram_freq_grp freq_group = get_freq_group(cali);
-	u8 buf_en_head;
-
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl3, MISC_CTRL3_ARPI_CG_CLK_OPT, 0);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl4, MISC_CTRL4_R_OPT2_CG_CLK, 0);
-
-	replace_dv_init(cali);
-
-	SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd14,
-		SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA, 0xc0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7,
-		SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0, 0x0,
-		SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0, 0x0,
-		SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0, 0x0);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7,
-		SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1, 0x0,
-		SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1, 0x0,
-		SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1, 0x0);
-
-	rx_picg_setting(cali);
-	dramc_sw_impedance_save_register(cali);
-	dqs_stb_settings();
-	rodt_settings(cali);
-	SET32_BITFIELDS(&ch[0].ao.shu_tx_set0, SHU_TX_SET0_DBIWR, 0x0);
-
-	dramc_cmd_ui_delay_setting(CHANNEL_A, ca_ui);
-	SET32_BITFIELDS(&ch[0].ao.shu_selph_ca5,
-		SHU_SELPH_CA5_DLY_CS, 0x1,
-		SHU_SELPH_CA5_DLY_CS1, 0x1);
-
-	for (u8 rk = 0; rk < cali->support_ranks; rk++)
-		cbt_delay_ca_clk(CHANNEL_A, rk, ca_pi);
-
-	SET32_BITFIELDS(&ch[0].ao.refctrl1, REFCTRL1_REF_OVERHEAD_PBR2PB_ENA, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.misctl0, MISCTL0_REFP_ARBMASK_PBR2PBR_ENA, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.scheduler_com, SCHEDULER_COM_PBR2PBR_OPT, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.shu_tx_set0, SHU_TX_SET0_WPST1P5T, fsp);
-	SET32_BITFIELDS(&ch[0].ao.dummy_rd,
-		DUMMY_RD_DMYRD_REORDER_DIS, 0x1,
-		DUMMY_RD_SREF_DMYRD_EN, 0x1);
-	SET32_BITFIELDS(&ch[0].ao.dramctrl,
-		DRAMCTRL_ALL_BLOCK_CTO_ALE_DBG_EN, 0x0,
-		DRAMCTRL_DVFS_BLOCK_CTO_ALE_DBG_EN, 0x1,
-		DRAMCTRL_SELFREF_BLOCK_CTO_ALE_DBG_EN, 0x1);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal2, MISC_STBCAL2_DQSGCNT_BYP_REF, 1);
-
-	if (freq_group <= DDRFREQ_800)
-		buf_en_head = 0;
-	else if (freq_group <= DDRFREQ_1200)
-		buf_en_head = 1;
-	else
-		buf_en_head = 2;
-
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_phy_rx_ctrl,
-			MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD, buf_en_head);
-
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl1, MISC_CTRL1_R_DMARPIDQ_SW, 1);
-	SET32_BITFIELDS(&ch[0].phy_ao.ca_tx_mck,
-		CA_TX_MCK_R_DMRESETB_DRVP_FRPHY, 0xa,
-		CA_TX_MCK_R_DMRESETB_DRVN_FRPHY, 0xa);
-	SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rank_sel_lat,
-		MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0, 0x3,
-		MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1, 0x3,
-		MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA, 0x3);
-	set_mck_8x_low_pwr_option();
-}
-
-static void dramc_setting(const struct ddr_cali *cali)
-{
-	dram_freq_grp freq_group = cali->freq_group;
-
-	dramc_set_broadcast(DRAMC_BROADCAST_ON);
-	switch (freq_group) {
-	case DDRFREQ_400:
-		sv_algorithm_assistance_lp4_800();
-		break;
-	case DDRFREQ_600:
-	case DDRFREQ_800:
-	case DDRFREQ_933:
-	case DDRFREQ_1200:
-		sv_algorithm_assistance_lp4_1600();
-		break;
-	case DDRFREQ_1600:
-		sv_algorithm_assistance_lp4_3733();
-		break;
-	case DDRFREQ_2133:
-		sv_algorithm_assistance_lp4_4266();
-		break;
-	default:
-		die("Invalid DDR frequency group %u\n", freq_group);
-		return;
-	}
-
-	update_initial_settings(cali);
-	dramc_set_broadcast(DRAMC_BROADCAST_OFF);
-}
-
-void cke_fix_onoff(const struct ddr_cali *cali, u8 chn, u8 rank, int option)
-{
-	u8 cke_on = 0, cke_off = 0;
-	bool set_rank1 = (rank == RANK_MAX) && (cali->support_ranks == DUAL_RANK_DDR);
-
-	if (option != CKE_DYNAMIC) {
-		cke_on = option;
-		cke_off = 1 - option;
-	}
-
-	if (rank == RANK_0 || rank == RANK_MAX) {
-		SET32_BITFIELDS(&ch[chn].ao.ckectrl,
-			CKECTRL_CKEFIXOFF, cke_off,
-			CKECTRL_CKEFIXON, cke_on);
-	}
-	if (rank == RANK_1 || set_rank1) {
-		SET32_BITFIELDS(&ch[chn].ao.ckectrl,
-			CKECTRL_CKE1FIXOFF, cke_off,
-			CKECTRL_CKE1FIXON, cke_on);
-	}
-}
-
-static void dramc_power_on_sequence(const struct ddr_cali *cali)
-{
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl1,
-			MISC_CTRL1_R_DMDA_RRESETB_I, 0x0);
-		cke_fix_onoff(cali, chn, RANK_MAX, CKE_FIXOFF);
-		udelay(200);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl1,
-			MISC_CTRL1_R_DMDA_RRESETB_I, 0x1);
-		SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl,
-			DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 1);
-		SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl,
-			DRAMC_PD_CTRL_TCKFIXON, 1);
-		mdelay(2);
-		cke_fix_onoff(cali, chn, RANK_MAX, CKE_FIXON);
-		udelay(2);
-		SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl,
-			DRAMC_PD_CTRL_TCKFIXON, 0);
-		SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl,
-			DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 0);
-	}
-}
-
-static void dramc_zq_calibration(const struct ddr_cali *cali, u8 chn, u8 rank)
-{
-	const u32 timeout = 100;
-
-	struct reg_bak regs_bak[] = {
-		{&ch[chn].ao.swcmd_en},
-		{&ch[chn].ao.swcmd_ctrl0},
-		{&ch[chn].ao.dramc_pd_ctrl},
-		{&ch[chn].ao.ckectrl},
-	};
-
-	for (int i = 0; i < ARRAY_SIZE(regs_bak); i++)
-		regs_bak[i].value = read32(regs_bak[i].addr);
-
-	SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 1);
-	SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, DRAMC_PD_CTRL_TCKFIXON, 1);
-	udelay(1);
-	cke_fix_onoff(cali, chn, rank, CKE_FIXON);
-	SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_SWTRIG_ZQ_RK, rank);
-	SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_ZQCEN_SWTRIG, 1);
-	if (!wait_us(timeout, READ32_BITFIELD(&ch[chn].nao.spcmdresp3,
-					      SPCMDRESP3_ZQC_SWTRIG_RESPONSE))) {
-		dramc_err("ZQCAL Start failed (time out)\n");
-		return;
-	}
-	SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_ZQCEN_SWTRIG, 0);
-
-	udelay(1);
-	SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_ZQLATEN_SWTRIG, 1);
-	if (!wait_us(timeout, READ32_BITFIELD(&ch[chn].nao.spcmdresp3,
-					      SPCMDRESP3_ZQLAT_SWTRIG_RESPONSE))) {
-		dramc_err("ZQCAL Latch failed (time out)\n");
-		return;
-	}
-	SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_ZQLATEN_SWTRIG, 0);
-
-	udelay(1);
-	for (int i = 0; i < ARRAY_SIZE(regs_bak); i++)
-		write32(regs_bak[i].addr, regs_bak[i].value);
-}
-
-u8 dramc_mode_reg_read(u8 chn, u8 mr_idx)
-{
-	const u32 timeout = 10000;
-	u8 value;
-
-	SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSMA, mr_idx);
-	SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_MRREN, 1);
-
-	/* Wait until MRW command fired */
-	if (!wait_ms(timeout, READ32_BITFIELD(&ch[chn].nao.spcmdresp,
-					      SPCMDRESP_MRR_RESPONSE))) {
-		dramc_err("Read mode register time out\n");
-		return -1;
-	}
-
-	value = READ32_BITFIELD(&ch[chn].nao.mrr_status, MRR_STATUS_MRR_SW_REG);
-	SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_MRREN, 0);
-	dramc_dbg("Read MR%d = %#x\n", mr_idx, value);
-
-	return value;
-}
-
-u8 dramc_mode_reg_read_by_rank(u8 chn, u8 rank, u8 mr_idx)
-{
-	u8 value;
-	u8 rank_bak;
-
-	rank_bak = READ32_BITFIELD(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK);
-	SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, rank);
-	value = dramc_mode_reg_read(chn, mr_idx);
-	SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, rank_bak);
-
-	return value;
-}
-
-void dramc_mode_reg_write_by_rank(const struct ddr_cali *cali,
-				  u8 chn, u8 rank, u8 mr_idx, u8 value)
-{
-	u32 bk_bak, ckectrl_bak;
-	dramc_info("MRW CH%d RK%d MR%d = %#x\n", chn, rank, mr_idx, value);
-
-	bk_bak = READ32_BITFIELD(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK);
-	ckectrl_bak = read32(&ch[chn].ao.ckectrl);
-
-	SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, rank);
-	cke_fix_onoff(cali, chn, rank, CKE_FIXON);
-	SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSMA, mr_idx);
-	SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSOP, value);
-	SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_MRWEN, 1);
-	while (READ32_BITFIELD(&ch[chn].nao.spcmdresp, SPCMDRESP_MRW_RESPONSE) == 0)
-		udelay(1);
-
-	SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_MRWEN, 0);
-	write32(&ch[chn].ao.ckectrl, ckectrl_bak);
-	SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, bk_bak);
-}
-
-void cbt_switch_freq(const struct ddr_cali *cali, cbt_freq freq)
-{
-	static u8 _cur_freq = CBT_UNKNOWN_FREQ;
-
-	/* if frequency is the same as before, do nothing */
-	if (_cur_freq == freq)
-		return;
-	_cur_freq = freq;
-
-	enable_dfs_hw_mode_clk();
-
-	if (freq == CBT_LOW_FREQ)
-		dramc_dfs_direct_jump_rg_mode(cali, DRAM_DFS_SHU1);
-	else
-		dramc_dfs_direct_jump_rg_mode(cali, DRAM_DFS_SHU0);
-
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_clk_ctrl,
-			MISC_CLK_CTRL_DVFS_CLK_MEM_SEL, 0,
-			MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN, 0);
-}
-
-static void dramc_mode_reg_init(const struct ddr_cali *cali)
-{
-	u8 chn;
-	u8 set_mrsrk;
-	u8 operate_fsp = get_fsp(cali);
-	struct mr_values *mr_value = cali->mr_value;
-
-	u32 bc_bak = dramc_get_broadcast();
-	dramc_set_broadcast(DRAMC_BROADCAST_OFF);
-	dramc_power_on_sequence(cali);
-
-	if (get_fsp(cali) == FSP_1) {
-		for (chn = 0; chn < CHANNEL_MAX; chn++)
-			SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2,
-				CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 1,
-				CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0,
-				CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff);
-		cbt_switch_freq(cali, CBT_LOW_FREQ);
-		for (chn = 0; chn < CHANNEL_MAX; chn++)
-			SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2,
-				CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 0,
-				CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 1,
-				CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff);
-	}
-
-	for (chn = 0; chn < CHANNEL_MAX; chn++) {
-		for (u8 rk = 0; rk < cali->support_ranks; rk++) {
-			dramc_dbg("ModeRegInit CH%u RK%u\n", chn, rk);
-			for (u8 fsp = FSP_0; fsp < FSP_MAX; fsp++) {
-				if (fsp == FSP_0) {
-					dramc_dbg("FSP0\n");
-					mr_value->mr13[rk] = BIT(4) | BIT(3);
-					mr_value->mr22[fsp] = 0x38;
-					mr_value->mr11[fsp] = 0x0;
-				} else {
-					dramc_dbg("FSP1\n");
-					mr_value->mr13[rk] |= 0x40;
-
-					if (cali->cbt_mode[rk] == CBT_NORMAL_MODE)
-						mr_value->mr11[fsp] = 0x3 | 0x40;
-					else
-						mr_value->mr11[fsp] = 0x3 | 0x20;
-
-					if (rk == RANK_0)
-						mr_value->mr22[fsp] = 0x4;
-					else
-						mr_value->mr22[fsp] = 0x2c;
-				}
-
-				dramc_mode_reg_write_by_rank(cali, chn, rk, 13,
-					mr_value->mr13[rk]);
-				dramc_mode_reg_write_by_rank(cali, chn, rk, 12,
-					mr_value->mr12[chn][rk][fsp]);
-				dramc_mode_reg_write_by_rank(cali, chn, rk, 1,
-					mr_value->mr01[fsp]);
-				dramc_mode_reg_write_by_rank(cali, chn, rk, 2,
-					mr_value->mr02[fsp]);
-				dramc_mode_reg_write_by_rank(cali, chn, rk, 11,
-					mr_value->mr11[fsp]);
-				dramc_mode_reg_write_by_rank(cali, chn, rk, 21,
-					mr_value->mr21[fsp]);
-				dramc_mode_reg_write_by_rank(cali, chn, rk, 51,
-					mr_value->mr51[fsp]);
-				dramc_mode_reg_write_by_rank(cali, chn, rk, 22,
-					mr_value->mr22[fsp]);
-				dramc_mode_reg_write_by_rank(cali, chn, rk, 14,
-					mr_value->mr14[chn][rk][fsp]);
-				dramc_mode_reg_write_by_rank(cali, chn, rk, 3,
-					mr_value->mr03[fsp]);
-				dramc_mode_reg_write_by_rank(cali, chn, rk, 4,
-					mr_value->mr04[rk]);
-				dramc_mode_reg_write_by_rank(cali, chn, rk, 3,
-					mr_value->mr03[fsp]);
-			}
-
-			dramc_zq_calibration(cali, chn, rk);
-
-			if (operate_fsp == FSP_0)
-				mr_value->mr13[rk] &= 0x3f;
-			else
-				mr_value->mr13[rk] |= 0xc0;
-		}
-
-		if (cali->support_ranks == DUAL_RANK_DDR)
-			set_mrsrk = 0x3;
-		else
-			set_mrsrk = RANK_0;
-
-		dramc_mode_reg_write_by_rank(cali, chn, set_mrsrk, 13, mr_value->mr13[RANK_0]);
-
-		SET32_BITFIELDS(&ch[chn].ao.shu_hwset_mr13,
-			SHU_HWSET_MR13_HWSET_MR13_OP, mr_value->mr13[RANK_0] | BIT(3),
-			SHU_HWSET_MR13_HWSET_MR13_MRSMA, 13);
-		SET32_BITFIELDS(&ch[chn].ao.shu_hwset_vrcg,
-			SHU_HWSET_VRCG_HWSET_VRCG_OP, mr_value->mr13[RANK_0] | BIT(3),
-			SHU_HWSET_VRCG_HWSET_VRCG_MRSMA, 13);
-		SET32_BITFIELDS(&ch[chn].ao.shu_hwset_mr2,
-			SHU_HWSET_MR2_HWSET_MR2_OP, mr_value->mr02[operate_fsp],
-			SHU_HWSET_MR2_HWSET_MR2_MRSMA, 2);
-	}
-
-	if (operate_fsp == FSP_1) {
-		for (chn = 0; chn < CHANNEL_MAX; chn++)
-			SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2,
-				CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 1,
-				CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0,
-				CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff);
-		cbt_switch_freq(cali, CBT_HIGH_FREQ);
-		for (chn = 0; chn < CHANNEL_MAX; chn++)
-			SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2,
-				CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 0,
-				CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 1,
-				CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff);
-	}
-
-	for (chn = 0; chn < CHANNEL_MAX; chn++)
-		SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, RANK_0);
-
-	dramc_set_broadcast(bc_bak);
-}
-
-static void move_dramc_delay(const struct ddr_cali *cali, reg_transfer *ui,
-			     reg_transfer *mck, s8 shift_ui)
-{
-	s32 sum;
-	u8 ui_offset = ui->offset, ui_width = 4, mck_offset = mck->offset, mck_width = 3;
-	u32 *ui_reg = ui->addr, *mck_reg = mck->addr;
-
-	u32 tmp_ui, tmp_mck, ui_mask, mck_mask;
-	u8 div_shift = get_mck2ui_div_shift(cali);
-
-	ui_mask = BIT(ui_width) - 1;
-	mck_mask = BIT(mck_width) - 1;
-	tmp_ui = ((read32(ui_reg) >> ui_offset) & ui_mask) & ~(1 << div_shift);
-	tmp_mck = (read32(mck_reg) >> mck_offset) & mck_mask;
-
-	sum = (tmp_mck << div_shift) + tmp_ui + shift_ui;
-
-	if (sum < 0) {
-		tmp_ui = 0;
-		tmp_mck = 0;
-	} else {
-		tmp_mck = sum >> div_shift;
-		tmp_ui = sum - (tmp_mck << div_shift);
-	}
-
-	clrsetbits32(ui_reg, ui_mask << ui_offset, tmp_ui << ui_offset);
-	clrsetbits32(mck_reg, mck_mask << mck_offset, tmp_mck << mck_offset);
-}
-
-void shift_dq_ui(const struct ddr_cali *cali, u8 rk, s8 shift_ui)
-{
-	u8 chn = cali->chn;
-	reg_transfer ui_regs[] = {
-		{&ch[chn].ao.shu_rk[rk].shurk_selph_dq3, 0},
-		{&ch[chn].ao.shu_rk[rk].shurk_selph_dq3, 4},
-		{&ch[chn].ao.shu_rk[rk].shurk_selph_dq2, 0},
-		{&ch[chn].ao.shu_rk[rk].shurk_selph_dq2, 4}
-	};
-	reg_transfer mck_regs[] = {
-		{&ch[chn].ao.shu_rk[rk].shurk_selph_dq1, 0},
-		{&ch[chn].ao.shu_rk[rk].shurk_selph_dq1, 4},
-		{&ch[chn].ao.shu_rk[rk].shurk_selph_dq0, 0},
-		{&ch[chn].ao.shu_rk[rk].shurk_selph_dq0, 4}
-	};
-
-	for (int idx = 0; idx < ARRAY_SIZE(ui_regs); idx++)
-		move_dramc_delay(cali, &ui_regs[idx], &mck_regs[idx], shift_ui);
-}
-
-static void ddr_update_ac_timing(const struct ddr_cali *cali)
-{
-	u8 table_idx;
-	const struct ac_timing *ac_tim;
-	const dram_freq_grp freq_group = cali->freq_group;
-
-	u8 rank_inctl, tx_dly, datlat_dsel;
-	const u8 root = 0;
-	u8 tx_rank_inctl;
-	const u8 tref_bw = 0;
-	u8 tfaw_05t, trrd_05t;
-	u16 xrtwtw, xtrtrt, xrtw2r, xrtr2w, tfaw;
-	u16 trtw, trtw_05t, tmrr2w, trrd;
-	u16 phs_inctl;
-	u32 rank_inctl_root;
-
-	for (table_idx = 0; table_idx < AC_TIMING_NUMBER; table_idx++)
-		if (ac_timing_tbl[table_idx].freq_group == freq_group &&
-		     ac_timing_tbl[table_idx].div_mode == get_div_mode(cali) &&
-		     ac_timing_tbl[table_idx].cbt_mode == get_cbt_mode(cali)) {
-			dramc_dbg("Found matched AC timing table %u\n", table_idx);
-			break;
-		}
-
-	if (table_idx == AC_TIMING_NUMBER) {
-		dramc_err("Error: no matched AC timing table found\n");
-		return;
-	}
-
-	ac_tim = &ac_timing_tbl[table_idx];
-
-	trtw = ac_tim->trtw_odt_on;
-	trtw_05t = ac_tim->trtw_odt_on_05T;
-	xrtw2r = ac_tim->xrtw2r_odt_on;
-	xrtr2w = ac_tim->xrtr2w_odt_on;
-	tfaw = ac_tim->tfaw_4266;
-	tfaw_05t = ac_tim->tfaw_4266_05T;
-	trrd = ac_tim->trrd_4266;
-	trrd_05t = ac_tim->trrd_4266_05T;
-	xtrtrt = ac_tim->xrtr2r_new_mode;
-	xrtwtw = ac_tim->xrtw2w_new_mode;
-	tmrr2w = ac_tim->tmrr2w_odt_on;
-
-	if (READ32_BITFIELD(&ch[0].phy_ao.shu_misc_rx_pipe_ctrl,
-			    SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN))
-		datlat_dsel = ac_tim->datlat;
-	else
-		datlat_dsel = ac_tim->datlat > 1 ? ac_tim->datlat - 1 : 0;
-
-	if (ac_tim->dqsinctl >= 2) {
-		rank_inctl_root = ac_tim->dqsinctl - 2;
-	} else {
-		dramc_err("rank_inctl_root <2, need check\n");
-		rank_inctl_root = 0;
-	}
-	phs_inctl = (ac_tim->dqsinctl == 0) ? 0 : (ac_tim->dqsinctl - 1);
-
-	if (freq_group <= DDRFREQ_800) {
-		if (get_div_mode(cali) == DIV4_MODE)	{
-			tx_rank_inctl = 1;
-			tx_dly = 2;
-		} else {
-			tx_rank_inctl = 0;
-			tx_dly = 1;
-		}
-	} else {
-		tx_rank_inctl = 1;
-		tx_dly = 2;
-	}
-
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-		SET32_BITFIELDS(&ch[chn].ao.shu_actim1,
-			SHU_ACTIM1_TRAS, ac_tim->tras,
-			SHU_ACTIM1_TRP, ac_tim->trp,
-			SHU_ACTIM1_TRPAB, ac_tim->trpab,
-			SHU_ACTIM1_TMRWCKEL, ac_tim->tmrwckel,
-			SHU_ACTIM1_TRC, ac_tim->trc);
-		SET32_BITFIELDS(&ch[chn].ao.shu_actim3,
-			SHU_ACTIM3_TRFC, ac_tim->trfc,
-			SHU_ACTIM3_TR2MRR, ac_tim->tr2mrr,
-			SHU_ACTIM3_TRFCPB, ac_tim->trfcpb);
-		SET32_BITFIELDS(&ch[chn].ao.shu_actim2,
-			SHU_ACTIM2_TXP, ac_tim->txp,
-			SHU_ACTIM2_TMRRI, ac_tim->tmrri,
-			SHU_ACTIM2_TFAW, tfaw,
-			SHU_ACTIM2_TR2W, trtw,
-			SHU_ACTIM2_TRTP, ac_tim->trtp);
-		SET32_BITFIELDS(&ch[chn].ao.shu_actim0,
-			SHU_ACTIM0_TRCD, ac_tim->trcd,
-			SHU_ACTIM0_TWR, ac_tim->twr,
-			SHU_ACTIM0_TRRD, trrd);
-		SET32_BITFIELDS(&ch[chn].ao.shu_actim5,
-			SHU_ACTIM5_TPBR2PBR, ac_tim->tpbr2pbr,
-			SHU_ACTIM5_TWTPD, ac_tim->twtpd,
-			SHU_ACTIM5_TPBR2ACT, ac_tim->tpbr2act);
-		SET32_BITFIELDS(&ch[chn].ao.shu_actim6,
-			SHU_ACTIM6_TR2MRW, ac_tim->tr2mrw,
-			SHU_ACTIM6_TW2MRW, ac_tim->tw2mrw,
-			SHU_ACTIM6_TMRD, ac_tim->tmrd,
-			SHU_ACTIM6_TZQLAT2, ac_tim->zqlat2,
-			SHU_ACTIM6_TMRW, ac_tim->tmrw);
-		SET32_BITFIELDS(&ch[chn].ao.shu_actim4,
-			SHU_ACTIM4_TMRR2MRW, ac_tim->tmrr2mrw,
-			SHU_ACTIM4_TMRR2W, tmrr2w,
-			SHU_ACTIM4_TZQCS, ac_tim->tzqcs,
-			SHU_ACTIM4_TXREFCNT, ac_tim->txrefcnt);
-		SET32_BITFIELDS(&ch[chn].ao.shu_ckectrl, SHU_CKECTRL_TCKEPRD, ac_tim->ckeprd);
-		SET32_BITFIELDS(&ch[chn].ao.shu_actim_xrt,
-			SHU_ACTIM_XRT_XRTW2W, xrtwtw,
-			SHU_ACTIM_XRT_XRTW2R, xrtw2r,
-			SHU_ACTIM_XRT_XRTR2W, xrtr2w,
-			SHU_ACTIM_XRT_XRTR2R, xtrtrt);
-		SET32_BITFIELDS(&ch[chn].ao.shu_hwset_vrcg,
-			SHU_HWSET_VRCG_VRCGDIS_PRDCNT, ac_tim->vrcgdis_prdcnt);
-		SET32_BITFIELDS(&ch[chn].ao.shu_hwset_mr2,
-			SHU_HWSET_MR2_HWSET_MR2_OP, ac_tim->hwset_mr2_op);
-		SET32_BITFIELDS(&ch[chn].ao.shu_hwset_mr13,
-			SHU_HWSET_MR13_HWSET_MR13_OP, ac_tim->hwset_mr13_op);
-		SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t,
-			SHU_AC_TIME_05T_TWTR_M05T, ac_tim->twtr_05T,
-			SHU_AC_TIME_05T_TR2W_05T, trtw_05t,
-			SHU_AC_TIME_05T_TWTPD_M05T, ac_tim->twtpd_05T,
-			SHU_AC_TIME_05T_TFAW_05T, tfaw_05t,
-			SHU_AC_TIME_05T_TRRD_05T, trrd_05t,
-			SHU_AC_TIME_05T_TWR_M05T, ac_tim->twr_05T,
-			SHU_AC_TIME_05T_TRAS_05T, ac_tim->tras_05T,
-			SHU_AC_TIME_05T_TRPAB_05T, ac_tim->trpab_05T,
-			SHU_AC_TIME_05T_TRP_05T, ac_tim->trp_05T,
-			SHU_AC_TIME_05T_TRCD_05T, ac_tim->trcd_05T,
-			SHU_AC_TIME_05T_TRTP_05T, ac_tim->trtp_05T,
-			SHU_AC_TIME_05T_TXP_05T, ac_tim->txp_05T);
-		SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t,
-			SHU_AC_TIME_05T_TRFC_05T, ac_tim->trfc_05T,
-			SHU_AC_TIME_05T_TRFCPB_05T, ac_tim->trfcpb_05T,
-			SHU_AC_TIME_05T_TPBR2PBR_05T, ac_tim->tpbr2pbr_05T,
-			SHU_AC_TIME_05T_TPBR2ACT_05T, ac_tim->tpbr2act_05T,
-			SHU_AC_TIME_05T_TR2MRW_05T, ac_tim->tr2mrw_05T,
-			SHU_AC_TIME_05T_TW2MRW_05T, ac_tim->tw2mrw_05T,
-			SHU_AC_TIME_05T_TMRR2MRW_05T, ac_tim->tmrr2mrw_05T,
-			SHU_AC_TIME_05T_TMRW_05T, ac_tim->tmrw_05T,
-			SHU_AC_TIME_05T_TMRD_05T, ac_tim->tmrd_05T,
-			SHU_AC_TIME_05T_TMRWCKEL_05T, ac_tim->tmrwckel_05T,
-			SHU_AC_TIME_05T_TMRRI_05T, ac_tim->tmrri_05T,
-			SHU_AC_TIME_05T_TRC_05T, ac_tim->trc_05T);
-		SET32_BITFIELDS(&ch[chn].ao.shu_actim0, SHU_ACTIM0_TWTR, ac_tim->twtr);
-		SET32_BITFIELDS(&ch[chn].ao.shu_ckectrl,
-			SHU_CKECTRL_TPDE, ac_tim->tpde,
-			SHU_CKECTRL_TPDX, ac_tim->tpdx,
-			SHU_CKECTRL_TPDE_05T, ac_tim->tpde_05T,
-			SHU_CKECTRL_TPDX_05T, ac_tim->tpdx_05T);
-		SET32_BITFIELDS(&ch[chn].ao.shu_actim5, SHU_ACTIM5_TR2PD, ac_tim->trtpd);
-		SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t,
-			SHU_AC_TIME_05T_TR2PD_05T, ac_tim->trtpd_05T);
-		SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating0,
-			SHU_AC_DERATING0_TRCD_DERATE, ac_tim->trcd_derate,
-			SHU_AC_DERATING0_TRRD_DERATE, ac_tim->trrd_derate);
-		SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating1,
-			SHU_AC_DERATING1_TRC_DERATE, ac_tim->trc_derate,
-			SHU_AC_DERATING1_TRAS_DERATE, ac_tim->tras_derate,
-			SHU_AC_DERATING1_TRP_DERATE, ac_tim->trp_derate,
-			SHU_AC_DERATING1_TRPAB_DERATE, ac_tim->trpab_derate);
-		SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating_05t,
-			SHU_AC_DERATING_05T_TRRD_05T_DERATE, ac_tim->trrd_derate_05T,
-			SHU_AC_DERATING_05T_TRAS_05T_DERATE, ac_tim->tras_derate_05T,
-			SHU_AC_DERATING_05T_TRPAB_05T_DERATE, ac_tim->trpab_derate_05T,
-			SHU_AC_DERATING_05T_TRP_05T_DERATE, ac_tim->trp_derate_05T,
-			SHU_AC_DERATING_05T_TRCD_05T_DERATE, ac_tim->trcd_derate_05T,
-			SHU_AC_DERATING_05T_TRC_05T_DERATE, ac_tim->trc_derate_05T);
-		SET32_BITFIELDS(&ch[chn].ao.refctrl3, REFCTRL3_REF_DERATING_EN, 0xc0);
-		SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating0,
-			SHU_AC_DERATING0_ACDERATEEN, 0x1);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_rk[0].misc_shu_rk_dqsctl,
-			MISC_SHU_RK_DQSCTL_DQSINCTL, ac_tim->dqsinctl);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_rk[1].misc_shu_rk_dqsctl,
-			MISC_SHU_RK_DQSCTL_DQSINCTL, ac_tim->dqsinctl);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_odtctrl,
-			MISC_SHU_ODTCTRL_RODT_LAT, ac_tim->dqsinctl);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rankctl,
-			MISC_SHU_RANKCTL_RANKINCTL_PHY, ac_tim->dqsinctl,
-			MISC_SHU_RANKCTL_RANKINCTL_ROOT1, rank_inctl_root,
-			MISC_SHU_RANKCTL_RANKINCTL, rank_inctl_root);
-		SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_rank_sel_stb,
-			SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, phs_inctl);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rdat,
-			MISC_SHU_RDAT_DATLAT, ac_tim->datlat,
-			MISC_SHU_RDAT_DATLAT_DSEL, datlat_dsel,
-			MISC_SHU_RDAT_DATLAT_DSEL_PHY, datlat_dsel);
-		SET32_BITFIELDS(&ch[chn].ao.shu_actiming_conf,
-			SHU_ACTIMING_CONF_REFBW_FR, tref_bw);
-		rank_inctl = READ32_BITFIELD(&ch[0].phy_ao.misc_shu_rankctl,
-			MISC_SHU_RANKCTL_RANKINCTL);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rankctl,
-			MISC_SHU_RANKCTL_RANKINCTL_RXDLY, rank_inctl);
-		SET32_BITFIELDS(&ch[chn].ao.shu_tx_rankctl,
-			SHU_TX_RANKCTL_TXRANKINCTL_ROOT, root,
-			SHU_TX_RANKCTL_TXRANKINCTL, tx_rank_inctl,
-			SHU_TX_RANKCTL_TXRANKINCTL_TXDLY, tx_dly);
-	}
-}
-
-static void set_cke2rank_independent(void)
-{
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-		SET32_BITFIELDS(&ch[chn].ao.rkcfg, RKCFG_CKE2RANK, 0);
-		SET32_BITFIELDS(&ch[chn].ao.ckectrl,
-			CKECTRL_CKE2RANK_OPT3, 0,
-			CKECTRL_CKE2RANK_OPT, 0,
-			CKECTRL_CKE2RANK_OPT2, 1,
-			CKECTRL_CKE2RANK_OPT5, 0,
-			CKECTRL_CKE2RANK_OPT6, 0,
-			CKECTRL_CKE2RANK_OPT7, 1,
-			CKECTRL_CKE2RANK_OPT8, 0,
-			CKECTRL_CKETIMER_SEL, 0,
-			CKECTRL_FASTWAKE_SEL, 1,
-			CKECTRL_CKEWAKE_SEL, 0);
-		SET32_BITFIELDS(&ch[chn].ao.shu_dcm_ctrl0,
-			SHU_DCM_CTRL0_FASTWAKE, 1,
-			SHU_DCM_CTRL0_FASTWAKE2, 1);
-		SET32_BITFIELDS(&ch[chn].ao.actiming_ctrl, ACTIMING_CTRL_CLKWITRFC, 0);
-	}
-}
-
-static void dramc_hw_gating_onoff(bool is_on)
-{
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl2,
-			MISC_DVFSCTL2_R_DVFS_OPTION, is_on,
-			MISC_DVFSCTL2_R_DVFS_PARK_N, is_on);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_stbcal2,
-			MISC_STBCAL2_STB_GERRSTOP, is_on);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_stbcal,
-			MISC_SHU_STBCAL_STBCALEN, is_on);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_stbcal,
-			MISC_SHU_STBCAL_STB_SELPHCALEN, is_on);
-	}
-}
-
-static void dramc_reset_delay_chain_before_calibration(void)
-{
-	u32 bc_bak = dramc_get_broadcast();
-	dramc_set_broadcast(DRAMC_BROADCAST_OFF);
-
-	for (u8 rk = RANK_0; rk < RANK_MAX; rk++) {
-		for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-			struct ddrphy_ao_regs *phy_ao = &ch[chn].phy_ao;
-
-			SET32_BITFIELDS(&phy_ao->ca_rk[rk].shu_r0_ca_txdly0,
-				SHU_R0_CA_TXDLY0_TX_ARCA0_DLY, 0,
-				SHU_R0_CA_TXDLY0_TX_ARCA1_DLY, 0,
-				SHU_R0_CA_TXDLY0_TX_ARCA2_DLY, 0,
-				SHU_R0_CA_TXDLY0_TX_ARCA3_DLY, 0);
-			SET32_BITFIELDS(&phy_ao->ca_rk[rk].shu_r0_ca_txdly1,
-				SHU_R0_CA_TXDLY1_TX_ARCA4_DLY, 0,
-				SHU_R0_CA_TXDLY1_TX_ARCA5_DLY, 0,
-				SHU_R0_CA_TXDLY1_TX_ARCA6_DLY, 0,
-				SHU_R0_CA_TXDLY1_TX_ARCA7_DLY, 0);
-			SET32_BITFIELDS(&phy_ao->byte[0].rk[rk].shu_r0_b0_txdly0,
-				SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0,
-				SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0,
-				SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0,
-				SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0);
-			SET32_BITFIELDS(&phy_ao->byte[0].rk[rk].shu_r0_b0_txdly1,
-				SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0,
-				SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0,
-				SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0,
-				SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0);
-			SET32_BITFIELDS(&phy_ao->byte[1].rk[rk].shu_r0_b0_txdly0,
-				SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0,
-				SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0,
-				SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0,
-				SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0);
-			SET32_BITFIELDS(&phy_ao->byte[1].rk[rk].shu_r0_b0_txdly1,
-				SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0,
-				SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0,
-				SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0,
-				SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0);
-			SET32_BITFIELDS(&phy_ao->byte[0].rk[rk].shu_r0_b0_txdly3,
-				SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x0);
-			SET32_BITFIELDS(&phy_ao->byte[1].rk[rk].shu_r0_b0_txdly3,
-				SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x0);
-		}
-	}
-
-	dramc_set_broadcast(bc_bak);
-}
-
-static void dramc_init(const struct ddr_cali *cali)
-{
-	dramc_setting(cali);
-	dramc_reset_delay_chain_before_calibration();
-	dramc_8_phase_cal(cali);
-	dramc_duty_calibration(cali->params);
-	dramc_mode_reg_init(cali);
-
-	ddr_update_ac_timing(cali);
-}
-
-static void dramc_before_calibration(const struct ddr_cali *cali)
-{
-	u8 ma_type = get_column_num();
-	dram_freq_grp freq_group = cali->freq_group;
-	u8 dis_imp_hw = (freq_group > DDRFREQ_1200) ? 0 : 1;
-
-	dramc_hw_gating_onoff(false);
-
-	cke_fix_onoff(cali, CHANNEL_A, RANK_MAX, CKE_FIXON);
-	cke_fix_onoff(cali, CHANNEL_B, RANK_MAX, CKE_FIXON);
-
-	set_cke2rank_independent();
-
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-		SET32_BITFIELDS(&ch[chn].ao.shu_tx_set0, SHU_TX_SET0_DBIWR, 0x0);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_impedamce_upd_dis1,
-			MISC_SHU_IMPEDAMCE_UPD_DIS1_ODTN_UPD_DIS, dis_imp_hw,
-			MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVN_UPD_DIS, dis_imp_hw,
-			MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVP_UPD_DIS, dis_imp_hw,
-			MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS, dis_imp_hw,
-			MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVN_UPD_DIS, dis_imp_hw,
-			MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVP_UPD_DIS, dis_imp_hw,
-			MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_ODTN_UPD_DIS, dis_imp_hw,
-			MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVN_UPD_DIS, dis_imp_hw,
-			MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVP_UPD_DIS, dis_imp_hw,
-			MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_ODTN_UPD_DIS, dis_imp_hw,
-			MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVN_UPD_DIS, dis_imp_hw,
-			MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVP_UPD_DIS, dis_imp_hw,
-			MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVP_UPD_DIS, 1,
-			MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVN_UPD_DIS, 1,
-			MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS, 1);
-
-		SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_impcal1,
-			SHU_MISC_IMPCAL1_IMPCALCNT, dis_imp_hw ? 0x0 : 0x40);
-		SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_drving1,
-			SHU_MISC_DRVING1_DIS_IMPCAL_HW, dis_imp_hw);
-		SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_drving1,
-			SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK, dis_imp_hw);
-		SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_drving2,
-			SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN, dis_imp_hw);
-		SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd12,
-			SHU_CA_CMD12_RG_RIMP_UNTERM_EN, dis_imp_hw);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_clk_ctrl,
-			MISC_CLK_CTRL_DVFS_CLK_MEM_SEL, 0,
-			MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN, 0);
-		SET32_BITFIELDS(&ch[chn].ao.shu_zq_set0,
-			SHU_ZQ_SET0_ZQCSCNT, 0x1ff,
-			SHU_ZQ_SET0_TZQLAT, 0x1b);
-		SET32_BITFIELDS(&ch[chn].ao.zq_set0,
-			ZQ_SET0_ZQCSDUAL, 1,
-			ZQ_SET0_ZQCSMASK_OPT, 0,
-			ZQ_SET0_ZQMASK_CGAR, 0,
-			ZQ_SET0_ZQCS_MASK_SEL_CGAR, 0);
-	}
-	SET32_BITFIELDS(&ch[0].ao.zq_set0, ZQ_SET0_ZQCSMASK, 1);
-	SET32_BITFIELDS(&ch[1].ao.zq_set0, ZQ_SET0_ZQCSMASK, 0);
-
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-		SET32_BITFIELDS(&ch[chn].ao.zq_set0, ZQ_SET0_ZQCS_MASK_SEL, 0);
-		SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq2,
-			SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0, 0);
-		SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq2,
-			SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1, 0);
-		SET32_BITFIELDS(&ch[chn].ao.dcm_sub_ctrl,
-			DCM_SUB_CTRL_SUBCLK_CTRL_TX_AUTOK, 0x0);
-		SET32_BITFIELDS(&ch[chn].ao.dcm_sub_ctrl,
-			DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING, 0);
-		SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_DQSOSCRDIS, 0x1);
-		SET32_BITFIELDS(&ch[chn].ao.refctrl0, REFCTRL0_REFDIS, 0x1);
-		SET32_BITFIELDS(&ch[chn].ao.shu_matype, SHU_MATYPE_MATYPE, ma_type);
-	}
-	tx_path_algorithm(cali);
-}
-
-void dfs_init_for_calibration(const struct ddr_cali *cali)
-{
-	dramc_init_default_mr_value(cali);
-	dramc_init(cali);
-	dramc_before_calibration(cali);
-}
-
-void tx_picg_setting(const struct ddr_cali *cali)
-{
-	u32 dqs_oen_final, dq_oen_final;
-	u16 dqs_oen_2t[2], dqs_oen_05t[2], dqs_oen_delay[2];
-	u16 dq_oen_2t[2], dq_oen_05t[2], dq_oen_delay[2];
-	u16 comb_tx_sel[2];
-	u16 shift_dqs_div[2], shift_dq_div[2];
-	u16 comb_tx_picg_cnt;
-	u8 div_ratio;
-
-	comb_tx_picg_cnt = 3;
-	if (get_div_mode(cali) == DIV8_MODE) {
-		shift_dqs_div[0] = 10;
-		shift_dqs_div[1] = 6;
-		shift_dq_div[0] = 8;
-		shift_dq_div[1] = 4;
-		div_ratio = 3;
-	} else {
-		shift_dqs_div[0] = 2;
-		shift_dqs_div[1] = 0;
-		shift_dq_div[0] = 0;
-		shift_dq_div[1] = 0;
-		div_ratio = 2;
-	}
-
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-		struct dramc_ao_regs *dramc_ao = &ch[chn].ao;
-
-		dqs_oen_2t[0] = READ32_BITFIELD(&dramc_ao->shu_selph_dqs0,
-			SHU_SELPH_DQS0_TXDLY_OEN_DQS0);
-		dqs_oen_05t[0] = READ32_BITFIELD(&dramc_ao->shu_selph_dqs1,
-			SHU_SELPH_DQS1_DLY_OEN_DQS0);
-		dqs_oen_delay[0] = (dqs_oen_2t[0] << div_ratio) + dqs_oen_05t[0];
-		dqs_oen_2t[1] = READ32_BITFIELD(&dramc_ao->shu_selph_dqs0,
-			SHU_SELPH_DQS0_TXDLY_OEN_DQS1);
-		dqs_oen_05t[1] = READ32_BITFIELD(&dramc_ao->shu_selph_dqs1,
-			SHU_SELPH_DQS1_DLY_OEN_DQS1);
-		dqs_oen_delay[1] = (dqs_oen_2t[1] << div_ratio) + dqs_oen_05t[1];
-
-		dqs_oen_final = MIN(dqs_oen_delay[0], dqs_oen_delay[1]) + 1;
-
-		comb_tx_sel[0] = (dqs_oen_final > shift_dqs_div[0]) ?
-			((dqs_oen_final - shift_dqs_div[0]) >> div_ratio) : 0;
-
-		if (get_div_mode(cali) == DIV4_MODE)
-			comb_tx_sel[1] = 0;
-		else
-			comb_tx_sel[1] = (dqs_oen_final > shift_dqs_div[1]) ?
-				((dqs_oen_final - shift_dqs_div[1]) >> div_ratio) : 0;
-
-		SET32_BITFIELDS(&dramc_ao->shu_aphy_tx_picg_ctrl,
-			SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P0, comb_tx_sel[0],
-			SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P1, comb_tx_sel[1],
-			SHU_APHY_TX_PICG_CTRL_TX_PICG_CNT, comb_tx_picg_cnt);
-		for (int rk = RANK_0; rk < cali->support_ranks; rk++) {
-			dq_oen_2t[0] = READ32_BITFIELD(&dramc_ao->shu_rk[rk].shurk_selph_dq0,
-				SHURK_SELPH_DQ0_TXDLY_OEN_DQ0);
-			dq_oen_05t[0] = READ32_BITFIELD(&dramc_ao->shu_rk[rk].shurk_selph_dq2,
-				SHURK_SELPH_DQ2_DLY_OEN_DQ0);
-			dq_oen_delay[0] = (dq_oen_2t[0] << div_ratio) + dq_oen_05t[0];
-			dq_oen_2t[1] = READ32_BITFIELD(&dramc_ao->shu_rk[rk].shurk_selph_dq0,
-				SHURK_SELPH_DQ0_TXDLY_OEN_DQ1);
-			dq_oen_05t[1] = READ32_BITFIELD(&dramc_ao->shu_rk[rk].shurk_selph_dq2,
-				SHURK_SELPH_DQ2_DLY_OEN_DQ1);
-			dq_oen_delay[1] = (dq_oen_2t[1] << div_ratio) + dq_oen_05t[1];
-
-			dq_oen_final = MIN(dq_oen_delay[0], dq_oen_delay[1]) + 1;
-
-			comb_tx_sel[0] = (dq_oen_final > shift_dq_div[0]) ?
-				((dq_oen_final - shift_dq_div[0]) >> div_ratio) : 0;
-
-			if (get_div_mode(cali) == DIV4_MODE)
-				comb_tx_sel[1] = 0;
-			else
-				comb_tx_sel[1] = (dq_oen_final > shift_dq_div[1]) ?
-					((dq_oen_final - shift_dq_div[1]) >> div_ratio) : 0;
-
-			SET32_BITFIELDS(&dramc_ao->shu_rk[rk].shurk_aphy_tx_picg_ctrl,
-				SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, comb_tx_sel[0],
-				SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, comb_tx_sel[1]);
-		}
-	}
-}
-
-void xrtrtr_shu_setting(const struct ddr_cali *cali)
-{
-	const dram_freq_grp freq_group = get_freq_group(cali);
-	u8 rk_sel_ui_minus = 0, rk_sel_mck_minus = 0;
-
-	if (freq_group == DDRFREQ_400)
-		rk_sel_mck_minus = 1;
-	else if (freq_group >= DDRFREQ_1600)
-		rk_sel_ui_minus = 2;
-
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
-		SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_rank_sel_stb,
-			SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS, rk_sel_mck_minus,
-			SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS, rk_sel_ui_minus,
-			SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS, 0x0,
-			SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS, 0x0,
-			SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN, 0x0,
-			SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK, 0x0,
-			SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK, 0x1,
-			SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE, 0x0,
-			SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23, 0x0,
-			SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN, 0x1);
-}
-
-void freq_jump_ratio_calculation(const struct ddr_cali *cali)
-{
-	u32 src_freq, dst_freq, src_shu, dst_shu, jump_ratio_index;
-	u16 jump_ratio[DRAM_DFS_SHU_MAX] = {0};
-
-	jump_ratio_index = 0;
-	src_freq = get_frequency(cali);
-	src_shu = get_shu(cali);
-
-	if (get_freq_group_by_shu_save(src_shu) != DDRFREQ_400) {
-		for (dst_shu = DRAM_DFS_SHU0; dst_shu < DRAM_DFS_SHU_MAX; dst_shu++) {
-			dst_freq = get_frequency_by_shu(dst_shu);
-			jump_ratio[jump_ratio_index] =
-				DIV_ROUND_CLOSEST(dst_freq * 32, src_freq);
-
-			dramc_dbg("Jump ratio [%u]: %#x Freq %d -> %d, DDR%u -> DDR%u\n",
-				jump_ratio_index, jump_ratio[jump_ratio_index],
-				src_shu, dst_shu, src_freq << 1, dst_freq << 1);
-			jump_ratio_index++;
-		}
-	}
-
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-		SET32_BITFIELDS(&ch[chn].ao.shu_freq_ratio_set0,
-			SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0, jump_ratio[0],
-			SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1, jump_ratio[1],
-			SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2, jump_ratio[2],
-			SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3, jump_ratio[3]);
-		SET32_BITFIELDS(&ch[chn].ao.shu_freq_ratio_set1,
-			SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO4, jump_ratio[4],
-			SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO5, jump_ratio[5],
-			SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO6, jump_ratio[6]);
-	}
-}
-
-void dramc_hmr4_presetting(const struct ddr_cali *cali)
-{
-	for (u8 chn = CHANNEL_A; chn < CHANNEL_MAX; chn++) {
-		SET32_BITFIELDS(&ch[chn].ao.hmr4, HMR4_REFR_PERIOD_OPT, 1);
-		SET32_BITFIELDS(&ch[chn].ao.hmr4, HMR4_REFRCNT_OPT, 0);
-		SET32_BITFIELDS(&ch[chn].ao.shu_hmr4_dvfs_ctrl0,
-			SHU_HMR4_DVFS_CTRL0_REFRCNT, 0x80);
-
-		if (get_cbt_mode(cali) == CBT_BYTE_MODE1)
-			SET32_BITFIELDS(&ch[chn].ao.hmr4, HMR4_HMR4_BYTEMODE_EN, 1);
-		else
-			SET32_BITFIELDS(&ch[chn].ao.hmr4, HMR4_HMR4_BYTEMODE_EN, 0);
-
-		SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFRATE_MON_CLR, 0);
-		SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFRATE_MON_CLR, 1);
-		SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFRATE_MON_CLR, 0);
-	}
-}
-
-void dramc_enable_perbank_refresh(bool en)
-{
-	if (en) {
-		for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-			SET32_BITFIELDS(&ch[chn].ao.refctrl0,
-				REFCTRL0_PBREF_BK_REFA_ENA, 1,
-				REFCTRL0_PBREF_BK_REFA_NUM, 2);
-			SET32_BITFIELDS(&ch[chn].ao.refctrl0,
-				REFCTRL0_KEEP_PBREF, 0,
-				REFCTRL0_KEEP_PBREF_OPT, 1);
-			SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFPB2AB_IGZQCS, 1);
-		}
-	}
-
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
-		SET32_BITFIELDS(&ch[chn].ao.shu_conf0, SHU_CONF0_PBREFEN, en);
-}
-
-void dramc_modified_refresh_mode(void)
-{
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-		SET32_BITFIELDS(&ch[chn].ao.refpend1,
-			REFPEND1_MPENDREFCNT_TH0, 2,
-			REFPEND1_MPENDREFCNT_TH1, 2,
-			REFPEND1_MPENDREFCNT_TH2, 4,
-			REFPEND1_MPENDREFCNT_TH3, 5,
-			REFPEND1_MPENDREFCNT_TH4, 5,
-			REFPEND1_MPENDREFCNT_TH5, 3,
-			REFPEND1_MPENDREFCNT_TH6, 3,
-			REFPEND1_MPENDREFCNT_TH7, 3);
-		SET32_BITFIELDS(&ch[chn].ao.refctrl1,
-			REFCTRL1_REFPEND_OPT1, 1,
-			REFCTRL1_REFPEND_OPT2, 1);
-		SET32_BITFIELDS(&ch[chn].ao.shu_ref0, SHU_REF0_MPENDREF_CNT, 4);
-	}
-}
-
-void dramc_cke_debounce(const struct ddr_cali *cali)
-{
-	if (get_freq_group(cali) < DDRFREQ_2133)
-		return;
-
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
-		for (u8 rk = 0; rk < cali->support_ranks; rk++)
-			SET32_BITFIELDS(&ch[chn].ao.shu_rk[rk].shurk_cke_ctrl,
-				SHURK_CKE_CTRL_CKE_DBE_CNT, 15);
-}
-
-void dramc_hw_dqsosc(const struct ddr_cali *cali, u8 chn)
-{
-	SET32_BITFIELDS(&ch[chn].ao.tx_freq_ratio_old_mode0,
-		TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT, 1);
-	SET32_BITFIELDS(&ch[chn].ao.tx_tracking_set0,
-		TX_TRACKING_SET0_SHU_PRELOAD_TX_HW, 1,
-		TX_TRACKING_SET0_SHU_PRELOAD_TX_START, 0,
-		TX_TRACKING_SET0_SW_UP_TX_NOW_CASE, 0);
-
-	SET32_BITFIELDS(&ch[chn].ao.mpc_ctrl, MPC_CTRL_MPC_BLOCKALE_OPT, 1);
-	SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl1, MISC_CTRL1_R_DMARPIDQ_SW, 0);
-	SET32_BITFIELDS(&ch[chn].ao.dcm_sub_ctrl, DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING, 1);
-	SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_ARUIDQ_SW, 1);
-	SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_DQSOSCRDIS, 0);
-	SET32_BITFIELDS(&ch[chn].ao.rk[0].rk_dqsosc, RK_DQSOSC_DQSOSCR_RK0EN, 1);
-	if (cali->support_ranks == DUAL_RANK_DDR)
-		SET32_BITFIELDS(&ch[chn].ao.rk[1].rk_dqsosc, RK_DQSOSC_DQSOSCR_RK0EN, 1);
-	SET32_BITFIELDS(&ch[chn].ao.tx_set0, TX_SET0_DRSCLR_RK0_EN, 1);
-	SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_DQSOSC_CALEN, 1);
-}
-
-void apply_write_dbi_power_improve(bool en)
-{
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
-		SET32_BITFIELDS(&ch[chn].ao.dbiwr_protect,
-			DBIWR_PROTECT_DBIWR_OPT_B1, 0,
-			DBIWR_PROTECT_DBIWR_OPT_B0, 0,
-			DBIWR_PROTECT_DBIWR_PINMUX_EN, 0,
-			DBIWR_PROTECT_DBIWR_IMP_EN, en);
-}
-
-void dramc_write_dbi_onoff(u8 onoff)
-{
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
-		SET32_BITFIELDS(&ch[chn].ao.shu_tx_set0, SHU_TX_SET0_DBIWR, onoff);
-	dramc_info("Dramc Write-DBI: %s\n", (onoff == DBI_ON) ? "on" : "off");
-}
diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c
deleted file mode 100644
index 5c6d94dbad..0000000000
--- a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c
+++ /dev/null
@@ -1,656 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <soc/dramc_pi_api.h>
-#include <soc/dramc_register.h>
-
-static const u8 imp_vref_sel[ODT_MAX][IMP_DRV_MAX] = {
-	/* DRVP  DRVN  ODTP  ODTN */
-	[ODT_OFF] = {0x37, 0x33, 0x00, 0x37},
-	[ODT_ON] = {0x3a, 0x33, 0x00, 0x3a},
-};
-
-static void dramc_imp_cal_vref_sel(dram_odt_state odt, imp_drv_type drv_type)
-{
-	u8 vref_tmp = imp_vref_sel[odt][drv_type];
-
-	switch (drv_type) {
-	case DRVP:
-		SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd12,
-			SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVP, vref_tmp);
-		break;
-	case DRVN:
-		SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd12,
-			SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVN, vref_tmp);
-		break;
-	case ODTN:
-		SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd12,
-			SHU_CA_CMD12_RG_RIMP_VREF_SEL_ODTN, vref_tmp);
-		break;
-	default:
-		die("Can't support drv_type %d\n", drv_type);
-		break;
-	}
-}
-
-static u32 dramc_sw_imp_cal_result(imp_drv_type drv_type)
-{
-	u32 drive = 0, cal_res = 0;
-	u32 change = (drv_type == DRVP) ? 1 : 0;
-
-	static const char *const drv_type_str[IMP_DRV_MAX] = {
-		[DRVP] = "DRVP",
-		[DRVN] = "DRVN",
-		[ODTP] = "ODTP",
-		[ODTN] = "ODTN",
-	};
-	if (drv_type >= IMP_DRV_MAX)
-		die("Can't support drv_type %d", drv_type);
-
-	const char *drv_str = drv_type_str[drv_type];
-
-	for (drive = 0; drive < 32; drive++) {
-		if (drv_type == DRVP)
-			SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_impcal1,
-				SHU_MISC_IMPCAL1_IMPDRVP, drive);
-		else if (drv_type == DRVN || drv_type == ODTN)
-			SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_impcal1,
-				SHU_MISC_IMPCAL1_IMPDRVN, drive);
-
-		udelay(1);
-		cal_res = READ32_BITFIELD(&ch[0].phy_nao.misc_phy_rgs_cmd,
-				MISC_PHY_RGS_CMD_RGS_RIMPCALOUT);
-		dramc_dbg("OCD %s=%d ,CALOUT=%d\n", drv_str, drive, cal_res);
-
-		if (cal_res == change) {
-			dramc_info("%s calibration passed! result=%d\n", drv_str, drive);
-			break;
-		}
-	}
-
-	if (drive == 32) {
-		drive = 31;
-		dramc_err("OCD %s calibration failed! %s=%d\n", drv_str, drv_str, drive);
-	}
-
-	return drive;
-}
-
-void dramc_sw_impedance_cal(dram_odt_state odt, struct dram_impedance *imp)
-{
-	const u8 chn = 0;
-	u8 i_chn, enp, enn;
-	u32 bc_bak, impcal_bak, cal_res;
-	u32 drvp_result = 0xff, odtn_result = 0xff, drvn_result = 0xff;
-
-	bc_bak = dramc_get_broadcast();
-	dramc_set_broadcast(DRAMC_BROADCAST_OFF);
-	for (i_chn = 0; i_chn < CHANNEL_MAX; i_chn++) {
-		SET32_BITFIELDS(&ch[i_chn].phy_ao.misc_lp_ctrl,
-			MISC_LP_CTRL_RG_ARDMSUS_10, 0x0,
-			MISC_LP_CTRL_RG_ARDMSUS_10_LP_SEL, 0x0,
-			MISC_LP_CTRL_RG_RIMP_DMSUS_10, 0x0,
-			MISC_LP_CTRL_RG_RIMP_DMSUS_10_LP_SEL, 0x0);
-		SET32_BITFIELDS(&ch[i_chn].phy_ao.misc_impcal, MISC_IMPCAL_IMPCAL_HW, 0);
-	}
-
-	impcal_bak = read32(&ch[chn].phy_ao.misc_impcal);
-	SET32_BITFIELDS(&ch[chn].phy_ao.misc_imp_ctrl1, MISC_IMP_CTRL1_RG_RIMP_PRE_EN, 0);
-	SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal,
-		MISC_IMPCAL_IMPCAL_CALI_ENN, 0,
-		MISC_IMPCAL_IMPCAL_IMPPDP, 1,
-		MISC_IMPCAL_IMPCAL_IMPPDN, 1);
-	SET32_BITFIELDS(&ch[chn].phy_ao.misc_imp_ctrl1,
-		MISC_IMP_CTRL1_RG_IMP_EN, 1,
-		MISC_IMP_CTRL1_RG_RIMP_DDR3_SEL, 0,
-		MISC_IMP_CTRL1_RG_RIMP_VREF_EN, 1,
-		MISC_IMP_CTRL1_RG_RIMP_DDR4_SEL, 1);
-	udelay(1);
-	SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, MISC_IMPCAL_IMPCAL_CALI_EN, 1);
-	SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_impcal1,
-		SHU_MISC_IMPCAL1_IMPDRVN, 0,
-		SHU_MISC_IMPCAL1_IMPDRVP, 0);
-
-	for (imp_drv_type drv_type = DRVP; drv_type < IMP_DRV_MAX; drv_type++) {
-		if (drv_type == ODTP)
-			continue;
-		dramc_imp_cal_vref_sel(odt, drv_type);
-
-		switch (drv_type) {
-		case DRVP:
-			enp = 0x1;
-			enn = 0x0;
-			drvp_result = 0;
-			break;
-		case DRVN:
-		case ODTN:
-			enp = 0x0;
-			enn = (drv_type == DRVN) ? 0x0 : 0x1;
-			break;
-		default:
-			die("Can't support drv_type %d\n", drv_type);
-			break;
-		}
-
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal,
-			MISC_IMPCAL_IMPCAL_CALI_ENP, enp);
-		SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal,
-			MISC_IMPCAL_IMPCAL_CALI_ENN, enn);
-		SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_impcal1,
-			SHU_MISC_IMPCAL1_IMPDRVP, drvp_result);
-		SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd12,
-			SHU_CA_CMD12_RG_RIMP_DRV05, 0);
-
-		cal_res = dramc_sw_imp_cal_result(drv_type);
-		switch (drv_type) {
-		case DRVP:
-			drvp_result = cal_res;
-			break;
-		case DRVN:
-			drvn_result = cal_res;
-			break;
-		case ODTN:
-			odtn_result = cal_res;
-			break;
-		default:
-			die("Can't support drv_type %d\n", drv_type);
-			break;
-		}
-	}
-
-	imp->result[odt][DRVP] = drvp_result;
-	imp->result[odt][DRVN] = drvn_result;
-	imp->result[odt][ODTP] = 0;
-	imp->result[odt][ODTN] = odtn_result;
-
-	dramc_info("freq_region=%d, Reg: DRVP=%d, DRVN=%d, ODTN=%d\n",
-		odt, drvp_result, drvn_result, odtn_result);
-
-	write32(&ch[chn].phy_ao.misc_impcal, impcal_bak);
-	dramc_set_broadcast(bc_bak);
-}
-
-void dramc_sw_impedance_save_register(const struct ddr_cali *cali)
-{
-	u8 ca_term, dq_term;
-	u32 bc_bak = dramc_get_broadcast();
-	const u32 (*result)[IMP_DRV_MAX] = cali->impedance.result;
-	struct ddrphy_ao_regs *phy_ao = &ch[0].phy_ao;
-
-	ca_term = get_odt_state(cali);
-	dq_term = (get_freq_group(cali) < DDRFREQ_2133) ? ODT_OFF : ODT_ON;
-
-	dramc_set_broadcast(DRAMC_BROADCAST_ON);
-	SET32_BITFIELDS(&phy_ao->shu_misc_drving1,
-		SHU_MISC_DRVING1_DQDRVP2, result[dq_term][DRVP],
-		SHU_MISC_DRVING1_DQDRVN2, result[dq_term][DRVN]);
-	SET32_BITFIELDS(&phy_ao->shu_misc_drving2,
-		SHU_MISC_DRVING2_DQDRVP1, result[dq_term][DRVP],
-		SHU_MISC_DRVING2_DQDRVN1, result[dq_term][DRVN]);
-	SET32_BITFIELDS(&phy_ao->shu_misc_drving3,
-		SHU_MISC_DRVING3_DQODTP2, result[dq_term][ODTP],
-		SHU_MISC_DRVING3_DQODTN2, result[dq_term][ODTN]);
-	SET32_BITFIELDS(&phy_ao->shu_misc_drving4,
-		SHU_MISC_DRVING4_DQODTP1, result[dq_term][ODTP],
-		SHU_MISC_DRVING4_DQODTN1, result[dq_term][ODTN]);
-
-	SET32_BITFIELDS(&phy_ao->shu_misc_drving1,
-		SHU_MISC_DRVING1_DQSDRVP2, result[dq_term][DRVP],
-		SHU_MISC_DRVING1_DQSDRVN2, result[dq_term][DRVN]);
-	SET32_BITFIELDS(&phy_ao->shu_misc_drving1,
-		SHU_MISC_DRVING1_DQSDRVP1, result[dq_term][DRVP],
-		SHU_MISC_DRVING1_DQSDRVN1, result[dq_term][DRVN]);
-	SET32_BITFIELDS(&phy_ao->shu_misc_drving3,
-		SHU_MISC_DRVING3_DQSODTP2, result[dq_term][ODTP],
-		SHU_MISC_DRVING3_DQSODTN2, result[dq_term][ODTN]);
-	SET32_BITFIELDS(&phy_ao->shu_misc_drving3,
-		SHU_MISC_DRVING3_DQSODTP, result[dq_term][ODTP],
-		SHU_MISC_DRVING3_DQSODTN, result[dq_term][ODTN]);
-
-	SET32_BITFIELDS(&phy_ao->shu_misc_drving2,
-		SHU_MISC_DRVING2_CMDDRVP2, result[ca_term][DRVP],
-		SHU_MISC_DRVING2_CMDDRVN2, result[ca_term][DRVN]);
-	SET32_BITFIELDS(&phy_ao->shu_misc_drving2,
-		SHU_MISC_DRVING2_CMDDRVP1, result[ca_term][DRVP],
-		SHU_MISC_DRVING2_CMDDRVN1, result[ca_term][DRVN]);
-	SET32_BITFIELDS(&phy_ao->shu_misc_drving4,
-		SHU_MISC_DRVING4_CMDODTP2, result[ca_term][ODTP],
-		SHU_MISC_DRVING4_CMDODTN2, result[ca_term][ODTN]);
-	SET32_BITFIELDS(&phy_ao->shu_misc_drving4,
-		SHU_MISC_DRVING4_CMDODTP1, result[ca_term][ODTP],
-		SHU_MISC_DRVING4_CMDODTN1, result[ca_term][ODTN]);
-
-	SET32_BITFIELDS(&phy_ao->misc_shu_drving8, MISC_SHU_DRVING8_CS_DRVP, 0xF);
-	SET32_BITFIELDS(&phy_ao->misc_shu_drving8, MISC_SHU_DRVING8_CS_DRVN, 0x14);
-
-	dramc_set_broadcast(bc_bak);
-}
-
-static void dramc_phy_reset(u8 chn)
-{
-	SET32_BITFIELDS(&ch[chn].ao.rx_set0, RX_SET0_RDATRST, 1);
-	SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl1, MISC_CTRL1_R_DMPHYRST, 1);
-	SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dq9,
-		B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 0,
-		B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 0);
-	SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dq9,
-		B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 0,
-		B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 0);
-	udelay(1);
-	SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dq9,
-		B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 1,
-		B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 1);
-	SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dq9,
-		B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 1,
-		B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 1);
-	SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl1, MISC_CTRL1_R_DMPHYRST, 0);
-	SET32_BITFIELDS(&ch[chn].ao.rx_set0, RX_SET0_RDATRST, 0);
-}
-
-static int dramc_8_phase_cal_find_best_dly(u8 phase_sm, u8 ph_dly, u8 ph_dly_back,
-					   int *ph_dly_final, int *ph_dly_loop_break)
-{
-	const u8 early_break_cnt = 5;
-	static u8 loop_cnt = 0;
-	static u16 r0 = 0xffff, r180 = 0xffff, r_tmp = 0xffff, p_tmp = 0xffff;
-	s16 err_code;
-	static s16 err_code_min = 0x7fff;
-	u16 dqs_dly;
-	const u16 jm_dly_start = 0, jm_dly_end = 512, jm_dly_step = 1;
-	u32 sample_cnt, ones_cnt;
-	u8 dqs_level = DQS_LEVEL_UNKNOWN;
-
-	dramc_dbg("8PH dly = %u\n", ph_dly);
-	*ph_dly_loop_break = 0;
-
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq1,
-		SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0, ph_dly);
-	SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq1,
-		SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1, ph_dly);
-	SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd1,
-		SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA, ph_dly);
-
-	for (dqs_dly = jm_dly_start; dqs_dly < jm_dly_end; dqs_dly += jm_dly_step) {
-		/* Set DQS delay */
-		SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_phy2,
-			B0_PHY2_RG_RX_ARDQS_JM_DLY_B0, dqs_dly);
-		SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_phy2,
-			B1_PHY2_RG_RX_ARDQS_JM_DLY_B1, dqs_dly);
-		dramc_phy_reset(0);
-		SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1,
-			MISC_DUTYSCAN1_REG_SW_RST, 1);
-		SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1,
-			MISC_DUTYSCAN1_REG_SW_RST, 0);
-		SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1,
-			MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 1);
-		udelay(10);
-		SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1,
-			MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 0);
-		sample_cnt = READ32_BITFIELD(&ch[0].phy_nao.misc_duty_toggle_cnt,
-					     MISC_DUTY_TOGGLE_CNT_TOGGLE_CNT);
-		ones_cnt = READ32_BITFIELD(&ch[0].phy_nao.misc_duty_dqs0_err_cnt,
-					   MISC_DUTY_DQS0_ERR_CNT_DQS0_ERR_CNT);
-
-		if (ones_cnt < sample_cnt / 2) {
-			if (dqs_level == DQS_LEVEL_UNKNOWN)
-				dramc_dbg("[L] %u, %8u\n", dqs_dly, ones_cnt);
-			dqs_level = 0;
-		} else if (dqs_level == 0) {
-			dqs_level = 1;
-			dramc_dbg("[H] %u, %8u\n", dqs_dly, ones_cnt);
-
-			if (phase_sm == DQS_8PH_DEGREE_0) {
-				r0 = dqs_dly;
-				dramc_dbg("R0 = %u\n", r0);
-			} else if (phase_sm == DQS_8PH_DEGREE_180) {
-				r180 = dqs_dly;
-				if (r180 <= r0) {
-					dqs_level = DQS_LEVEL_UNKNOWN;
-					continue;
-				}
-
-				r_tmp = r0 + ((r180 - r0) >> 2);
-				dramc_dbg("R = %u, R180 = %u\n", r_tmp, r180);
-			} else if (phase_sm == DQS_8PH_DEGREE_45) {
-				p_tmp = dqs_dly;
-				dramc_dbg("p_tmp = %u, R0 = %u\n", p_tmp, r0);
-				if (p_tmp <= r0) {
-					dqs_level = DQS_LEVEL_UNKNOWN;
-					continue;
-				}
-
-				err_code = ABS(p_tmp - r_tmp);
-
-				if (err_code == 0) {
-					*ph_dly_final = ph_dly;
-					*ph_dly_loop_break = 1;
-				} else if (err_code < err_code_min) {
-					err_code_min = err_code;
-					*ph_dly_final = ph_dly;
-					loop_cnt = 0;
-				} else {
-					loop_cnt++;
-					if (loop_cnt > early_break_cnt)
-						*ph_dly_loop_break = 1;
-				}
-
-				dramc_dbg("diff (P-R) = %d, min = %d, break count = %u\n",
-					err_code, err_code_min, loop_cnt);
-			} else {
-				die("Invalid phase_sm: %u!\n", phase_sm);
-			}
-
-			break;
-		}
-	}
-
-	if (dqs_level == DQS_LEVEL_UNKNOWN || dqs_level == 0) {
-		*ph_dly_final = ph_dly_back;
-		dramc_err("8-Phase SM_%u failed, falling back to default\n", phase_sm);
-		return 0;
-	} else if (*ph_dly_loop_break) {
-		return -1;
-	}
-
-	return -2;
-}
-
-static void dramc_8_phase_cal_set_best_dly(const struct ddr_cali *cali, u8 ph_dly_back)
-{
-	u8 dqsien_pi;
-	u8 phase_sm, ph_dly, ph_start, ph_end;
-	int ph_dly_loop_break;
-	int ph_dly_final = 0xff;	/* default delay: 0xff */
-
-	for (phase_sm = DQS_8PH_DEGREE_0; phase_sm < DQS_8PH_DEGREE_MAX; phase_sm++) {
-		switch (phase_sm) {
-		case DQS_8PH_DEGREE_0:
-			dqsien_pi = 16;
-			ph_start = 0;
-			ph_end = 1;
-			break;
-		case DQS_8PH_DEGREE_180:
-			dqsien_pi = 48;
-			ph_start = 0;
-			ph_end = 1;
-			break;
-		case DQS_8PH_DEGREE_45:
-			dqsien_pi = 24;
-			ph_start = 0;
-			ph_end = 32;
-			break;
-		default:
-			die("Invalid phase_sm: %u!\n", phase_sm);
-			return;
-		}
-
-		dramc_dbg("8-Phase SM_%u, 8PH_dly (%u~%u), DQSIEN PI = %u, 8PH_Dly = %u\n",
-			phase_sm, ph_start, ph_end, dqsien_pi, ph_dly_back);
-
-		for (u8 rk = RANK_0; rk < cali->support_ranks; rk++)
-			SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[rk].shu_rk_b0_dqsien_pi_dly,
-				SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, dqsien_pi);
-
-		for (ph_dly = ph_start; ph_dly < ph_end; ph_dly++) {
-			int ret = dramc_8_phase_cal_find_best_dly(phase_sm, ph_dly,
-					ph_dly_back, &ph_dly_final, &ph_dly_loop_break);
-			if (ret == 0)
-				goto final_found;
-			if (ph_dly_loop_break)
-				break;
-		}
-	}
-
-final_found:
-	dramc_dbg("8 phase calibration ph_dly_final = %u\n", ph_dly_final);
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-		SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq1,
-			SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0, ph_dly_final);
-		SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq1,
-			SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1, ph_dly_final);
-		SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd1,
-			SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA, ph_dly_final);
-	}
-}
-
-void dramc_8_phase_cal(const struct ddr_cali *cali)
-{
-	u8 ph_dly_back = 0;
-	dram_freq_grp freq_group = cali->freq_group;
-	/* ch0 and ch1 of phy_ao */
-	struct ddrphy_ao_regs *phy_ao = &ch[0].phy_ao;
-	struct ddrphy_ao_regs *phy_ao_ch1 = &ch[1].phy_ao;
-
-	if (freq_group < DDRFREQ_2133) {
-		dramc_info("Freq %u < 2133, do not need do 8-Phase\n", get_frequency(cali));
-		return;
-	}
-
-	struct reg_bak regs_bak[] = {
-		{&phy_ao->misc_dutyscan1},
-		{&phy_ao->dvs_b[0].b0_dq6},
-		{&phy_ao->dvs_b[1].b0_dq6},
-		{&phy_ao->dvs_b[0].b0_dq5},
-		{&phy_ao->dvs_b[1].b0_dq5},
-		{&phy_ao->dvs_b[0].b0_dq3},
-		{&phy_ao->dvs_b[1].b0_dq3},
-		{&phy_ao->misc_ctrl1},
-		{&phy_ao->misc_ctrl4},
-		{&phy_ao->dvs_b[0].b0_phy2},
-		{&phy_ao->dvs_b[1].b0_phy2},
-		{&phy_ao->byte[0].shu_b0_dll_arpi2},
-		{&phy_ao->byte[1].shu_b0_dll_arpi2},
-		{&phy_ao->byte[0].shu_b0_dq11},
-		{&phy_ao->byte[1].shu_b0_dq11},
-		{&phy_ao->shu_ca_cmd11},
-		{&phy_ao->misc_stbcal},
-		{&phy_ao->byte[0].rk[0].shu_rk_b0_dqsien_pi_dly},
-		{&phy_ao->byte[0].rk[1].shu_rk_b0_dqsien_pi_dly},
-		{&phy_ao->misc_jmeter},
-		{&phy_ao->misc_shu_stbcal},
-		{&phy_ao->shu_ca_dll1},
-		{&phy_ao->byte[0].shu_b0_dll1},
-		{&phy_ao->byte[1].shu_b0_dll1},
-		{&phy_ao->dvs_b[0].b0_dq2},
-		{&phy_ao->dvs_b[1].b0_dq2},
-		{&phy_ao->ca_cmd2},
-		{&phy_ao->byte[0].shu_b0_dq13},
-		{&phy_ao->byte[1].shu_b0_dq13},
-		{&phy_ao->shu_ca_cmd13},
-		{&phy_ao_ch1->shu_ca_dll1},
-		{&phy_ao_ch1->byte[0].shu_b0_dll1},
-		{&phy_ao_ch1->byte[1].shu_b0_dll1},
-		{&phy_ao_ch1->dvs_b[0].b0_dq2},
-		{&phy_ao_ch1->dvs_b[1].b0_dq2},
-		{&phy_ao_ch1->ca_cmd2},
-		{&phy_ao_ch1->byte[0].shu_b0_dq13},
-		{&phy_ao_ch1->byte[1].shu_b0_dq13},
-		{&phy_ao_ch1->shu_ca_cmd13},
-	};
-	for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++)
-		regs_bak[i].value = read32(regs_bak[i].addr);
-
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-		phy_ao = &ch[chn].phy_ao;
-		SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_dq2,
-			B0_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B0, 0,
-			B0_DQ2_RG_TX_ARDQS_OE_TIE_EN_B0, 1,
-			B0_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B0, 0,
-			B0_DQ2_RG_TX_ARWCK_OE_TIE_EN_B0, 1,
-			B0_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B0, 0,
-			B0_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B0, 1,
-			B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0, 0,
-			B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0, 1,
-			B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0, 0,
-			B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0, 0xff);
-		SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_dq2,
-			B1_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B1, 0,
-			B1_DQ2_RG_TX_ARDQS_OE_TIE_EN_B1, 1,
-			B1_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B1, 0,
-			B1_DQ2_RG_TX_ARWCK_OE_TIE_EN_B1, 1,
-			B1_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B1, 0,
-			B1_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B1, 1,
-			B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1, 0,
-			B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1, 1,
-			B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1, 0,
-			B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1, 0xff);
-		SET32_BITFIELDS(&phy_ao->ca_cmd2,
-			CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA, 0,
-			CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA, 1,
-			CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA, 0,
-			CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA, 1,
-			CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0,
-			CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff);
-		SET32_BITFIELDS(&phy_ao->byte[0].shu_b0_dq13,
-			SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0, 0,
-			SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0, 1);
-		SET32_BITFIELDS(&phy_ao->byte[1].shu_b0_dq13,
-			SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1, 0,
-			SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1, 1);
-		SET32_BITFIELDS(&phy_ao->shu_ca_cmd13,
-			SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA, 0,
-			SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA, 1);
-	}
-
-	phy_ao = &ch[0].phy_ao;
-	ph_dly_back = READ32_BITFIELD(&phy_ao->byte[0].shu_b0_dq1,
-		SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0);
-	SET32_BITFIELDS(&phy_ao->misc_shu_stbcal,
-		MISC_SHU_STBCAL_STBCALEN, 0x0,
-		MISC_SHU_STBCAL_STB_SELPHCALEN, 0x0);
-	SET32_BITFIELDS(&phy_ao->byte[0].shu_b0_dq11,
-		SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0, 0);
-	SET32_BITFIELDS(&phy_ao->byte[1].shu_b0_dq11,
-		SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1, 0);
-	SET32_BITFIELDS(&phy_ao->shu_ca_cmd11,
-		SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA, 0);
-
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-		phy_ao = &ch[chn].phy_ao;
-		SET32_BITFIELDS(&phy_ao->shu_ca_dll1,
-			SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 0x0,
-			SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA, 0x0);
-		SET32_BITFIELDS(&phy_ao->byte[0].shu_b0_dll1,
-			SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0, 0x0,
-			SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0, 0x0);
-		SET32_BITFIELDS(&phy_ao->byte[1].shu_b0_dll1,
-			SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1, 0x0,
-			SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1, 0x0);
-	}
-
-	phy_ao = &ch[0].phy_ao;
-	SET32_BITFIELDS(&phy_ao->misc_ctrl1, MISC_CTRL1_R_DMDQSIENCG_EN, 0);
-	SET32_BITFIELDS(&phy_ao->byte[0].shu_b0_dll_arpi2,
-		SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0, 0);
-	SET32_BITFIELDS(&phy_ao->byte[1].shu_b0_dll_arpi2,
-		SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1, 0);
-	SET32_BITFIELDS(&phy_ao->misc_dutyscan1,
-		MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN, 1);
-	SET32_BITFIELDS(&phy_ao->misc_ctrl4, MISC_CTRL4_R_OPT2_CG_DQSIEN, 0);
-	SET32_BITFIELDS(&phy_ao->misc_stbcal, MISC_STBCAL_DQSIENCG_NORMAL_EN, 0);
-	SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_dq6,
-		B0_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B0, 1);
-	SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_dq6,
-		B1_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B1, 1);
-	SET32_BITFIELDS(&phy_ao->misc_dutyscan1, MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 1);
-	SET32_BITFIELDS(&phy_ao->misc_dutyscan1,
-		MISC_DUTYSCAN1_EYESCAN_DQS_SYNC_EN, 0x1,
-		MISC_DUTYSCAN1_EYESCAN_NEW_DQ_SYNC_EN, 0x1,
-		MISC_DUTYSCAN1_EYESCAN_DQ_SYNC_EN, 0x1);
-	SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_dq5, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0, 1);
-	SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_dq5, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1, 1);
-	SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_dq5, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 1);
-	SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_dq5, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 1);
-	SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_dq3, B0_DQ3_RG_RX_ARDQ_SMT_EN_B0, 1);
-	SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_dq3, B1_DQ3_RG_RX_ARDQ_SMT_EN_B1, 1);
-	SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_phy2, B0_PHY2_RG_RX_ARDQS_JM_EN_B0, 1);
-	SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_phy2, B1_PHY2_RG_RX_ARDQS_JM_EN_B1, 1);
-	SET32_BITFIELDS(&phy_ao->misc_jmeter, MISC_JMETER_JMTR_EN, 1);
-	SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_phy2, B0_PHY2_RG_RX_ARDQS_JM_SEL_B0, 1);
-	SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_phy2, B1_PHY2_RG_RX_ARDQS_JM_SEL_B1, 1);
-	SET32_BITFIELDS(&phy_ao->misc_dutyscan1, MISC_DUTYSCAN1_RX_MIOCK_JIT_EN, 1);
-	SET32_BITFIELDS(&phy_ao->misc_dutyscan1, MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 0);
-	SET32_BITFIELDS(&phy_ao->misc_dutyscan1, MISC_DUTYSCAN1_DQSERRCNT_DIS, 0);
-
-	dramc_8_phase_cal_set_best_dly(cali, ph_dly_back);
-
-	for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++)
-		write32(regs_bak[i].addr, regs_bak[i].value);
-}
-
-static void duty_delay_reg_convert(s8 duty_delay, u8 *delay)
-{
-	if (duty_delay < 0)
-		*delay = -duty_delay;
-	else if (duty_delay > 0)
-		*delay = duty_delay + (1 << 5);
-	else
-		*delay = 0;
-}
-
-static void dramc_duty_set_clk_delay_cell(u8 chn, const s8 *duty_delay)
-{
-	u8 delay;
-
-	duty_delay_reg_convert(duty_delay[RANK_0], &delay);
-	SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_txduty,
-		SHU_CA_TXDUTY_DA_TX_ARCLK_DUTY_DLY, delay);
-}
-
-static void dramc_duty_set_dqs_delay_cell(u8 chn, const s8 *duty_delay)
-{
-	u8 dqs;
-	u8 delay;
-
-	for (dqs = 0; dqs < DQS_NUMBER; dqs++) {
-		duty_delay_reg_convert(duty_delay[dqs], &delay);
-		SET32_BITFIELDS(&ch[chn].phy_ao.byte[dqs].shu_b0_txduty,
-			SHU_B0_TXDUTY_DA_TX_ARDQS_DUTY_DLY_B0, delay);
-	}
-}
-
-static void dramc_duty_set_wck_delay_cell(u8 chn, const s8 *duty_delay)
-{
-	u8 dqs;
-	u8 delay;
-
-	for (dqs = 0; dqs < DQS_NUMBER; dqs++) {
-		duty_delay_reg_convert(duty_delay[dqs], &delay);
-		SET32_BITFIELDS(&ch[chn].phy_ao.byte[dqs].shu_b0_txduty,
-			SHU_B0_TXDUTY_DA_TX_ARWCK_DUTY_DLY_B0, delay);
-	}
-}
-
-static void dramc_duty_set_dqdqm_delay_cell(u8 chn, const s8 *duty_delay,
-					    u8 k_type)
-{
-	u8 dqs;
-	u8 delay;
-
-	for (dqs = 0; dqs < DQS_NUMBER; dqs++) {
-		duty_delay_reg_convert(duty_delay[dqs], &delay);
-
-		if (k_type == DUTYSCAN_K_DQ)
-			SET32_BITFIELDS(&ch[chn].phy_ao.byte[dqs].shu_b0_txduty,
-				SHU_B0_TXDUTY_DA_TX_ARDQ_DUTY_DLY_B0, delay);
-		else if (k_type == DUTYSCAN_K_DQM)
-			SET32_BITFIELDS(&ch[chn].phy_ao.byte[dqs].shu_b0_txduty,
-				SHU_B0_TXDUTY_DA_TX_ARDQM_DUTY_DLY_B0, delay);
-	}
-}
-
-void dramc_duty_calibration(const struct sdram_params *params)
-{
-	u32 bc_bak = dramc_get_broadcast();
-	dramc_set_broadcast(DRAMC_BROADCAST_OFF);
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-		dramc_duty_set_clk_delay_cell(chn, params->duty_clk_delay[chn]);
-		dramc_duty_set_dqs_delay_cell(chn, params->duty_dqs_delay[chn]);
-		dramc_duty_set_wck_delay_cell(chn, params->duty_wck_delay[chn]);
-		dramc_duty_set_dqdqm_delay_cell(chn, params->duty_dqm_delay[chn],
-			DUTYSCAN_K_DQM);
-		dramc_duty_set_dqdqm_delay_cell(chn, params->duty_dq_delay[chn],
-			DUTYSCAN_K_DQ);
-	}
-
-	dramc_set_broadcast(bc_bak);
-}
diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c
deleted file mode 100644
index ff2bfc9741..0000000000
--- a/src/soc/mediatek/mt8192/dramc_pi_main.c
+++ /dev/null
@@ -1,392 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <soc/dramc_pi_api.h>
-#include <soc/dramc_register.h>
-#include <soc/pll.h>
-#include <soc/pll_common.h>
-#include <soc/regulator.h>
-
-static void dramc_write_shift_mck_write_dbi(const struct ddr_cali *cali, s8 shift_value)
-{
-	u8 div_shift;
-	s8 ui_move;
-
-	div_shift = get_mck2ui_div_shift(cali);
-	ui_move = shift_value * (1 << div_shift);
-	shift_dq_ui(cali, cali->rank, ui_move);
-}
-
-static void dramc_ac_timing_optimize(const struct ddr_cali *cali)
-{
-	u8 rf_group, cab_id;
-	u8 trfc, trfc_05t, trfc_pb, trfrc_pb05t, tx_ref_cnt;
-
-	enum {
-		TRFCAB_130,
-		TRFCAB_180,
-		TRFCAB_280,
-		TRFCAB_380,
-		TRFCAB_NUM,
-	};
-	enum {
-		GRP_DDR800_DIV4_ACTIM,
-		GRP_DDR1200_ACTIM,
-		GRP_DDR1600_ACTIM,
-		GRP_DDR1866_ACTIM,
-		GRP_DDR2400_ACTIM,
-		GRP_DDR3200_ACTIM,
-		GRP_DDR4266_ACTIM,
-		GRP_ACTIM_NUM,
-	};
-	struct optimize_ac_time {
-		u8 trfc;
-		u8 trfc_05t;
-		u8 trfc_pb;
-		u8 trfrc_pb05t;
-		u16 tx_ref_cnt;
-	};
-
-	const u8 density = cali->density;
-	const dram_freq_grp freq_group = get_freq_group(cali);
-
-	/* tRFCab */
-	struct optimize_ac_time *ptr_trfcab_opt;
-	struct optimize_ac_time trfcab_opt[GRP_ACTIM_NUM][TRFCAB_NUM] = {
-		[GRP_DDR800_DIV4_ACTIM] = {
-			{.trfc = 14, .trfc_05t = 0, .trfc_pb = 0,
-				.trfrc_pb05t = 0, .tx_ref_cnt = 28},
-			{.trfc = 24, .trfc_05t = 0, .trfc_pb = 6,
-				.trfrc_pb05t = 0, .tx_ref_cnt = 38},
-			{.trfc = 44, .trfc_05t = 0, .trfc_pb = 16,
-				.trfrc_pb05t = 0, .tx_ref_cnt = 58},
-			{.trfc = 64, .trfc_05t = 0, .trfc_pb = 26,
-				.trfrc_pb05t = 0, .tx_ref_cnt = 78}
-		},
-		[GRP_DDR1200_ACTIM] = {
-			{.trfc = 8, .trfc_05t = 0, .trfc_pb = 0,
-				.trfrc_pb05t = 0, .tx_ref_cnt = 21},
-			{.trfc = 15, .trfc_05t = 1, .trfc_pb = 2,
-				.trfrc_pb05t = 0, .tx_ref_cnt = 29},
-			{.trfc = 30, .trfc_05t = 1, .trfc_pb = 9,
-				.trfrc_pb05t = 1, .tx_ref_cnt = 44},
-			{.trfc = 45, .trfc_05t = 1, .trfc_pb = 17,
-				.trfrc_pb05t = 0, .tx_ref_cnt = 59}
-		},
-		[GRP_DDR1600_ACTIM] = {
-			{.trfc = 14, .trfc_05t = 0, .trfc_pb = 0,
-				.trfrc_pb05t = 0, .tx_ref_cnt = 28},
-			{.trfc = 24, .trfc_05t = 0, .trfc_pb = 6,
-				.trfrc_pb05t = 0, .tx_ref_cnt = 38},
-			{.trfc = 44, .trfc_05t = 0, .trfc_pb = 16,
-				.trfrc_pb05t = 0, .tx_ref_cnt = 58},
-			{.trfc = 64, .trfc_05t = 0, .trfc_pb = 26,
-				.trfrc_pb05t = 0, .tx_ref_cnt = 78}
-		},
-		[GRP_DDR1866_ACTIM] = {
-			{.trfc = 18, .trfc_05t = 1, .trfc_pb = 2,
-				.trfrc_pb05t = 0, .tx_ref_cnt = 33},
-			{.trfc = 30, .trfc_05t = 0, .trfc_pb = 9,
-				.trfrc_pb05t = 0, .tx_ref_cnt = 44},
-			{.trfc = 53, .trfc_05t = 1, .trfc_pb = 21,
-				.trfrc_pb05t = 0, .tx_ref_cnt = 68},
-			{.trfc = 77, .trfc_05t = 0, .trfc_pb = 32,
-				.trfrc_pb05t = 1, .tx_ref_cnt = 91}
-		},
-		[GRP_DDR2400_ACTIM] = {
-			{.trfc = 27, .trfc_05t = 1, .trfc_pb = 6,
-				.trfrc_pb05t = 1, .tx_ref_cnt = 42},
-			{.trfc = 42, .trfc_05t = 1, .trfc_pb = 15,
-				.trfrc_pb05t = 1, .tx_ref_cnt = 57},
-			{.trfc = 72, .trfc_05t = 1, .trfc_pb = 30,
-				.trfrc_pb05t = 1, .tx_ref_cnt = 87},
-			{.trfc = 102, .trfc_05t = 1, .trfc_pb = 45,
-				.trfrc_pb05t = 1, .tx_ref_cnt = 117}
-		},
-		[GRP_DDR3200_ACTIM] = {
-			{.trfc = 40, .trfc_05t = 0, .trfc_pb = 12,
-				.trfrc_pb05t = 0, .tx_ref_cnt = 55},
-			{.trfc = 60, .trfc_05t = 0, .trfc_pb = 24,
-				.trfrc_pb05t = 0, .tx_ref_cnt = 75},
-			{.trfc = 100, .trfc_05t = 0, .trfc_pb = 44,
-				.trfrc_pb05t = 0, .tx_ref_cnt = 115},
-			{.trfc = 140, .trfc_05t = 0, .trfc_pb = 64,
-				.trfrc_pb05t = 0, .tx_ref_cnt = 155}
-		},
-		[GRP_DDR4266_ACTIM] = {
-			{.trfc = 57, .trfc_05t = 1, .trfc_pb = 20,
-				.trfrc_pb05t = 0, .tx_ref_cnt = 74},
-			{.trfc = 84, .trfc_05t = 0, .trfc_pb = 36,
-				.trfrc_pb05t = 0, .tx_ref_cnt = 100},
-			{.trfc = 137, .trfc_05t = 1, .trfc_pb = 63,
-				.trfrc_pb05t = 0, .tx_ref_cnt = 154},
-			{.trfc = 191, .trfc_05t = 0, .trfc_pb = 89,
-				.trfrc_pb05t = 1, .tx_ref_cnt = 207}
-		}
-	};
-
-	switch (density) {
-	case 0x0:
-		rf_group = TRFCAB_130;
-		break;
-	case 0x1:
-	case 0x2:
-		rf_group = TRFCAB_180;
-		break;
-	case 0x3:
-	case 0x4:
-		rf_group = TRFCAB_280;
-		break;
-	case 0x5:
-	case 0x6:
-		rf_group = TRFCAB_380;
-		break;
-	default:
-		die("Invalid DDR density %u\n", density);
-		return;
-	}
-
-	switch (freq_group) {
-	case DDRFREQ_400:
-		cab_id = GRP_DDR800_DIV4_ACTIM;
-		break;
-	case DDRFREQ_600:
-		cab_id = GRP_DDR1200_ACTIM;
-		break;
-	case DDRFREQ_800:
-		cab_id = GRP_DDR1600_ACTIM;
-		break;
-	case DDRFREQ_933:
-		cab_id = GRP_DDR1866_ACTIM;
-		break;
-	case DDRFREQ_1200:
-		cab_id = GRP_DDR2400_ACTIM;
-		break;
-	case DDRFREQ_1600:
-		cab_id = GRP_DDR3200_ACTIM;
-		break;
-	case DDRFREQ_2133:
-		cab_id = GRP_DDR4266_ACTIM;
-		break;
-	default:
-		die("Invalid DDR frequency group %u\n", freq_group);
-		return;
-	}
-
-	ptr_trfcab_opt = &trfcab_opt[cab_id][0];
-	trfc = ptr_trfcab_opt[rf_group].trfc;
-	trfc_05t = ptr_trfcab_opt[rf_group].trfc_05t;
-	trfc_pb = ptr_trfcab_opt[rf_group].trfc_pb;
-	trfrc_pb05t = ptr_trfcab_opt[rf_group].trfrc_pb05t;
-	tx_ref_cnt = ptr_trfcab_opt[rf_group].tx_ref_cnt;
-
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-		SET32_BITFIELDS(&ch[chn].ao.shu_actim3,
-				SHU_ACTIM3_TRFC, trfc);
-		SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t,
-				SHU_AC_TIME_05T_TRFC_05T, trfc_05t);
-		SET32_BITFIELDS(&ch[chn].ao.shu_actim4,
-				SHU_ACTIM4_TXREFCNT, tx_ref_cnt);
-		SET32_BITFIELDS(&ch[chn].ao.shu_actim3,
-				SHU_ACTIM3_TRFCPB, trfc_pb);
-		SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t,
-				SHU_AC_TIME_05T_TRFCPB_05T, trfrc_pb05t);
-		dramc_dbg("Density (MR8 OP[5:2]) %u, TRFC %u, TRFC_05T %u, TXREFCNT %u, "
-			  "TRFCpb %u, TRFCpb_05T %u\n",
-			  density, trfc, trfc_05t, tx_ref_cnt, trfc_pb, trfrc_pb05t);
-	}
-}
-
-static void set_vcore_voltage(const struct ddr_cali *cali)
-{
-	u32 vcore = get_vcore_value(cali);
-
-	dramc_info("Set DRAM vcore voltage to %u\n", vcore);
-	mainboard_set_regulator_vol(MTK_REGULATOR_VCORE, vcore);
-}
-
-static void get_dram_info_after_cal(struct ddr_cali *cali)
-{
-	u8 vendor_id, density, max_density = 0;
-	u32 size_gb, max_size = 0;
-
-	vendor_id = dramc_mode_reg_read_by_rank(CHANNEL_A, RANK_0, 5) & 0xff;
-	dramc_info("Vendor id is %#x\n", vendor_id);
-
-	for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) {
-		density = dramc_mode_reg_read_by_rank(CHANNEL_A, rk, 8) & 0xff;
-		dramc_dbg("MR8 %#x\n", density);
-		density = (density >> 2) & 0xf;
-
-		switch (density) {
-		/* these case values are from JESD209-4C MR8 Density OP[5:2] */
-		case 0x0:
-			size_gb = 4;
-			break;
-		case 0x1:
-			size_gb = 6;
-			break;
-		case 0x2:
-			size_gb = 8;
-			break;
-		case 0x3:
-			size_gb = 12;
-			break;
-		case 0x4:
-			size_gb = 16;
-			break;
-		case 0x5:
-			size_gb = 24;
-			break;
-		case 0x6:
-			size_gb = 32;
-			break;
-		case 0xC:
-			size_gb = 2;
-			break;
-		default:
-			dramc_err("Unexpected mode register density value: %#x\n", density);
-			size_gb = 0;
-			break;
-		}
-		if (size_gb > max_size) {
-			max_size = size_gb;
-			max_density = density;
-		}
-		dramc_dbg("RK%u size %uGb, density:%u\n", rk, size_gb, max_density);
-	}
-
-	cali->density = max_density;
-}
-
-static void dramc_calibration_single_channel(struct ddr_cali *cali, u8 chn)
-{
-	cali->chn = chn;
-	SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2,
-		CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 0,
-		CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 1,
-		CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff);
-}
-
-static void dramc_calibration_all_channels(struct ddr_cali *cali)
-{
-	u8 chn_bak, rank_bak;
-	const dbi_mode w_dbi = get_write_dbi(cali);
-
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
-		SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2,
-			CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 1,
-			CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0,
-			CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff);
-
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
-		dramc_calibration_single_channel(cali, chn);
-
-	if (w_dbi == DBI_ON) {
-		chn_bak = cali->chn;
-		rank_bak = cali->rank;
-		for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
-			for (u8 rank = RANK_0; rank < RANK_MAX; rank++) {
-				cali->chn = chn;
-				cali->rank = rank;
-				dramc_write_shift_mck_write_dbi(cali, -1);
-			}
-		cali->chn = chn_bak;
-		cali->rank = rank_bak;
-		apply_write_dbi_power_improve(true);
-	}
-
-	dramc_write_dbi_onoff(w_dbi);
-
-	tx_picg_setting(cali);
-	if (cali->support_ranks == DUAL_RANK_DDR)
-		xrtrtr_shu_setting(cali);
-	freq_jump_ratio_calculation(cali);
-
-	dramc_hmr4_presetting(cali);
-	dramc_enable_perbank_refresh(true);
-	dramc_modified_refresh_mode();
-	dramc_cke_debounce(cali);
-
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
-		dramc_hw_dqsosc(cali, chn);
-}
-
-static void mem_pll_init(void)
-{
-	SET32_BITFIELDS(&mtk_apmixed->mpll_con3, PLL_POWER_ISO_ENABLE, 3);
-
-	udelay(30);
-	SET32_BITFIELDS(&mtk_apmixed->mpll_con3, PLL_ISO_ENABLE, 0);
-
-	udelay(1);
-	SET32_BITFIELDS(&mtk_apmixed->mpll_con1, PLL_CON1, MPLL_CON1_FREQ);
-	SET32_BITFIELDS(&mtk_apmixed->mpll_con0, PLL_ENABLE, 1);
-
-	udelay(20);
-	SET32_BITFIELDS(&mtk_apmixed->pllon_con0, MPLL_IOS_SEL, 0);
-	SET32_BITFIELDS(&mtk_apmixed->pllon_con0, MPLL_EN_SEL, 0);
-	SET32_BITFIELDS(&mtk_apmixed->pllon_con1, MPLL_PWR_SEL, 0);
-	SET32_BITFIELDS(&mtk_apmixed->pllon_con2, MPLL_BY_ISO_DLY, 0);
-	SET32_BITFIELDS(&mtk_apmixed->pllon_con3, MPLL_BY_PWR_DLY, 0);
-}
-
-void init_dram(const struct dramc_data *dparam)
-{
-	u32 bc_bak;
-	u8 k_shuffle, k_shuffle_end;
-	u8 pll_mode = 0;
-	bool first_freq_k = true;
-
-	struct ddr_cali cali = {0};
-	struct mr_values mr_value;
-	const struct ddr_base_info *ddr_info = &dparam->ddr_info;
-
-	cali.pll_mode = &pll_mode;
-	cali.mr_value = &mr_value;
-	cali.support_ranks = ddr_info->support_ranks;
-	cali.cbt_mode[RANK_0] = ddr_info->cbt_mode[RANK_0];
-	cali.cbt_mode[RANK_1] = ddr_info->cbt_mode[RANK_1];
-	cali.emi_config = &ddr_info->emi_config;
-
-	dramc_set_broadcast(DRAMC_BROADCAST_ON);
-	mem_pll_init();
-
-	global_option_init(&cali);
-	bc_bak = dramc_get_broadcast();
-	dramc_set_broadcast(DRAMC_BROADCAST_OFF);
-	emi_mdl_init(cali.emi_config);
-	dramc_set_broadcast(bc_bak);
-
-	dramc_sw_impedance_cal(ODT_OFF, &cali.impedance);
-	dramc_sw_impedance_cal(ODT_ON, &cali.impedance);
-
-	if (ddr_info->config_dvfs == DRAMC_ENABLE_DVFS)
-		k_shuffle_end = CALI_SEQ_MAX;
-	else
-		k_shuffle_end = CALI_SEQ1;
-
-	for (k_shuffle = CALI_SEQ0; k_shuffle < k_shuffle_end; k_shuffle++) {
-		set_cali_datas(&cali, dparam, k_shuffle);
-		set_vcore_voltage(&cali);
-		dfs_init_for_calibration(&cali);
-
-		if (first_freq_k)
-			emi_init2();
-
-		dramc_calibration_all_channels(&cali);
-
-		/* only need to do once to get DDR's base information */
-		if (first_freq_k)
-			get_dram_info_after_cal(&cali);
-
-		dramc_ac_timing_optimize(&cali);
-		dramc_save_result_to_shuffle(DRAM_DFS_SHU0, cali.shu);
-
-		/* for frequency switch in dramc_mode_reg_init phase */
-		if (first_freq_k)
-			dramc_load_shuffle_to_dramc(cali.shu, DRAM_DFS_SHU1);
-
-		first_freq_k = false;
-		dramc_info("Calibration of data rate %u finished\n", get_frequency(&cali) * 2);
-	}
-}
diff --git a/src/soc/mediatek/mt8192/dramc_utility.c b/src/soc/mediatek/mt8192/dramc_utility.c
deleted file mode 100644
index 71a7eb6920..0000000000
--- a/src/soc/mediatek/mt8192/dramc_utility.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <soc/dramc_pi_api.h>
-#include <soc/dramc_register.h>
-#include <soc/infracfg.h>
-
-struct dfs_frequency_table {
-	u32 frequency;
-	dram_freq_grp freq_group;
-	dram_div_mode div_mode;
-	dram_dfs_shu shuffle_saved;
-	vref_cali_mode vref_cali;
-	u32 vcore;
-};
-
-static const struct dfs_frequency_table freq_shuffle_table[DRAM_DFS_SHU_MAX] = {
-	[CALI_SEQ0] = {800, DDRFREQ_800, DIV8_MODE, DRAM_DFS_SHU4, VREF_CALI_ON, 650000},
-	[CALI_SEQ1] = {1200, DDRFREQ_1200, DIV8_MODE, DRAM_DFS_SHU2, VREF_CALI_ON, 662500},
-	[CALI_SEQ2] = {600, DDRFREQ_600, DIV8_MODE, DRAM_DFS_SHU5, VREF_CALI_OFF, 650000},
-	[CALI_SEQ3] = {933, DDRFREQ_933, DIV8_MODE, DRAM_DFS_SHU3, VREF_CALI_OFF, 662500},
-	[CALI_SEQ4] = {400, DDRFREQ_400, DIV4_MODE, DRAM_DFS_SHU6, VREF_CALI_OFF, 650000},
-	[CALI_SEQ5] = {2133, DDRFREQ_2133, DIV8_MODE, DRAM_DFS_SHU0, VREF_CALI_ON, 725000},
-	[CALI_SEQ6] = {1600, DDRFREQ_1600, DIV8_MODE, DRAM_DFS_SHU1, VREF_CALI_OFF, 687500},
-};
-
-void dramc_set_broadcast(u32 onoff)
-{
-	write32(&mt8192_infracfg->dramc_wbr, onoff);
-}
-
-u32 dramc_get_broadcast(void)
-{
-	return read32(&mt8192_infracfg->dramc_wbr);
-}
-
-u8 get_fsp(const struct ddr_cali *cali)
-{
-	return cali->fsp;
-}
-
-dram_div_mode get_div_mode(const struct ddr_cali *cali)
-{
-	return cali->div_mode;
-}
-
-dram_freq_grp get_freq_group(const struct ddr_cali *cali)
-{
-	return cali->freq_group;
-}
-
-dbi_mode get_write_dbi(const struct ddr_cali *cali)
-{
-	return cali->w_dbi[get_fsp(cali)];
-}
-
-dram_odt_state get_odt_state(const struct ddr_cali *cali)
-{
-	return cali->odt_onoff;
-}
-
-dram_dfs_shu get_shu(const struct ddr_cali *cali)
-{
-	return cali->shu;
-}
-
-dram_cbt_mode get_cbt_mode(const struct ddr_cali *cali)
-{
-	return cali->cbt_mode[cali->rank];
-}
-
-u32 get_vcore_value(const struct ddr_cali *cali)
-{
-	return cali->vcore_voltage;
-}
-
-u32 get_frequency(const struct ddr_cali *cali)
-{
-	return cali->frequency;
-}
-
-vref_cali_mode get_vref_cali(const struct ddr_cali *cali)
-{
-	return cali->vref_cali;
-}
-
-dram_pinmux_type get_pinmux_type(const struct ddr_cali *cali)
-{
-	return cali->pinmux_type;
-}
-
-u8 get_mck2ui_div_shift(const struct ddr_cali *cali)
-{
-	if (get_div_mode(cali) == DIV4_MODE)
-		return 2;
-	else
-		return 3;
-}
-
-dram_dfs_shu get_shu_save_by_k_shu(dram_cali_seq k_shu)
-{
-	return freq_shuffle_table[k_shu].shuffle_saved;
-}
-
-dram_freq_grp get_freq_group_by_shu_save(dram_dfs_shu shu)
-{
-	for (u8 k_shu = CALI_SEQ0; k_shu < CALI_SEQ_MAX; k_shu++)
-		if (freq_shuffle_table[k_shu].shuffle_saved == shu)
-			return freq_shuffle_table[k_shu].freq_group;
-
-	dramc_err("Invalid shuffle: %d\n", shu);
-	return DDRFREQ_800;
-}
-
-u32 get_frequency_by_shu(dram_dfs_shu shu)
-{
-	for (u8 k_shu = CALI_SEQ0; k_shu < CALI_SEQ_MAX; k_shu++)
-		if (freq_shuffle_table[k_shu].shuffle_saved == shu)
-			return freq_shuffle_table[k_shu].frequency;
-
-	dramc_err("Invalid shuffle: %d, using k_shu = %d\n", shu, CALI_SEQ0);
-	return freq_shuffle_table[CALI_SEQ0].frequency;
-}
-
-dram_freq_grp get_highest_freq_group(void)
-{
-	dram_freq_grp highest_freq = DDRFREQ_800;
-
-	for (u8 k_shu = CALI_SEQ0; k_shu < CALI_SEQ_MAX; k_shu++)
-		if (freq_shuffle_table[k_shu].freq_group > highest_freq)
-			highest_freq = freq_shuffle_table[k_shu].freq_group;
-
-	dramc_dbg("Highest freq is: %d\n", highest_freq);
-	return highest_freq;
-}
-
-void set_cali_datas(struct ddr_cali *cali, const struct dramc_data *dparam, dram_cali_seq k_shu)
-{
-	const struct dfs_frequency_table *shuffle = &freq_shuffle_table[k_shu];
-
-	cali->chn = CHANNEL_A;
-	cali->rank = RANK_0;
-	cali->fsp = (shuffle->freq_group < DDRFREQ_1600) ? FSP_0 : FSP_1;
-	cali->w_dbi[FSP_0] = DBI_OFF;
-	cali->w_dbi[FSP_1] = DBI_ON;
-	cali->frequency = shuffle->frequency;
-	cali->freq_group = shuffle->freq_group;
-	cali->div_mode = shuffle->div_mode;
-	cali->shu = shuffle->shuffle_saved;
-	cali->vref_cali = shuffle->vref_cali;
-	cali->vcore_voltage = shuffle->vcore;
-	cali->odt_onoff = (cali->fsp == FSP_0) ? ODT_OFF : ODT_ON;
-	cali->params = &dparam->freq_params[cali->shu];
-
-	dramc_dbg("cali data (size: %ld) fsp: %d, freq_group: %d, div_mode: %d, "
-		  "shu: %d, vref_cali: %d, odt_onoff: %d, vcore: %d\n",
-		  sizeof(*cali), cali->fsp, cali->freq_group, cali->div_mode, cali->shu,
-		  cali->vref_cali, cali->odt_onoff, cali->vcore_voltage);
-}
-
-void dramc_auto_refresh_switch(u8 chn, bool enable)
-{
-	SET32_BITFIELDS(&ch[chn].ao.refctrl0, REFCTRL0_REFDIS, enable ? 0 : 1);
-
-	if (!enable)
-		udelay(READ32_BITFIELD(&ch[chn].nao.misc_statusa,
-		       MISC_STATUSA_REFRESH_QUEUE_CNT));
-}
diff --git a/src/soc/mediatek/mt8192/emi.c b/src/soc/mediatek/mt8192/emi.c
deleted file mode 100644
index a130a8874e..0000000000
--- a/src/soc/mediatek/mt8192/emi.c
+++ /dev/null
@@ -1,440 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <soc/dramc_pi_api.h>
-#include <soc/dramc_register.h>
-#include <soc/infracfg.h>
-#include <symbols.h>
-
-static struct emi_regs *emi_reg = (void *)EMI_BASE;
-static struct emi_mpu_regs *const emi_mpu = (void *)EMI_MPU_BASE;
-static struct infra_ao_mem_regs *infra_ao_mem = (void *)INFRACFG_AO_MEM_BASE;
-
-static void emi_center_config(void)
-{
-	/* set EMI default settings which EMI hardware needs */
-	write32(&emi_reg->cona, 0xf053f154);
-	write32(&emi_reg->conp, 0x182e2d33);
-	write32(&emi_reg->conb, 0x0f251025);
-	write32(&emi_reg->conq, 0x122a1027);
-	write32(&emi_reg->conc, 0x1a31162d);
-	write32(&emi_reg->conb_2nd, 0x182e2d33);
-	write32(&emi_reg->conc_2nd, 0x0f251025);
-	write32(&emi_reg->conp_2nd, 0x122a1027);
-	write32(&emi_reg->conq_2nd, 0x1a31162d);
-	write32(&emi_reg->conb_3rd, 0x1024202c);
-	write32(&emi_reg->conc_3rd, 0x0b210c21);
-	write32(&emi_reg->conp_3rd, 0x0f250d23);
-	write32(&emi_reg->conq_3rd, 0x152b1228);
-	write32(&emi_reg->conb_4th, 0x0c201a28);
-	write32(&emi_reg->conc_4th, 0x0d230a20);
-	write32(&emi_reg->conp_4th, 0x0e260d24);
-	write32(&emi_reg->conq_4th, 0x132d1229);
-	write32(&emi_reg->conb_5th, 0x0c201a28);
-	write32(&emi_reg->conc_5th, 0x0d230a20);
-	write32(&emi_reg->conp_5th, 0x0e260d24);
-	write32(&emi_reg->conq_5th, 0x132d1229);
-	write32(&emi_reg->conb_6th, 0x0c201a28);
-	write32(&emi_reg->conc_6th, 0x0d230a20);
-	write32(&emi_reg->conp_6th, 0x0e260d24);
-	write32(&emi_reg->conq_6th, 0x132d1229);
-	write32(&emi_reg->conb_7th, 0x0e290e28);
-	write32(&emi_reg->conc_7th, 0x091e1322);
-	write32(&emi_reg->mpud26_st, 0x0f29112a);
-	write32(&emi_reg->conq_7th, 0x0c240a1f);
-	write32(&emi_reg->conb_8th, 0x0e290e28);
-	write32(&emi_reg->conc_8th, 0x091e1322);
-	write32(&emi_reg->conp_8th, 0x0f29112a);
-	write32(&emi_reg->conq_8th, 0x0c240a1f);
-	write32(&emi_reg->cong, 0x37373a57);
-	write32(&emi_reg->conr, 0x3f3f3c39);
-	write32(&emi_reg->cong_2nd, 0x3836374e);
-	write32(&emi_reg->conr_2nd, 0x41413d3a);
-	write32(&emi_reg->cong_3rd, 0x33313241);
-	write32(&emi_reg->conr_3rd, 0x3a3a3835);
-	write32(&emi_reg->cong_4th, 0x34343542);
-	write32(&emi_reg->conr_4th, 0x3b3b3835);
-	write32(&emi_reg->cong_5th, 0x34343542);
-	write32(&emi_reg->conr_5th, 0x3b3b3835);
-	write32(&emi_reg->cong_6th, 0x34343542);
-	write32(&emi_reg->conr_6th, 0x3b3b3835);
-	write32(&emi_reg->cong_7th, 0x37333034);
-	write32(&emi_reg->conr_7th, 0x39393a39);
-	write32(&emi_reg->cong_8th, 0x37333034);
-	write32(&emi_reg->conr_8th, 0x39393a39);
-	write32(&emi_reg->cond, 0x3657587a);
-	write32(&emi_reg->cone, 0x0000c042);
-	write32(&emi_reg->conf, 0x08421000);
-	write32(&emi_reg->conh, 0x00000083);
-	write32(&emi_reg->conh_2nd, 0x00073210);
-	write32(&emi_reg->coni, 0x00008802);
-	write32(&emi_reg->conj, 0x00000000);
-	write32(&emi_reg->conm, 0x007812ff);
-	write32(&emi_reg->conn, 0x00000000);
-	write32(&emi_reg->mdct, 0x11120c1f);
-	write32(&emi_reg->shf0, 0x11120c1f);
-	write32(&emi_reg->mdct_2nd, 0x00001123);
-	write32(&emi_reg->shf1, 0x00001123);
-	write32(&emi_reg->iocl, 0xa8a8a8a8);
-	write32(&emi_reg->iocl_2nd, 0x25252525);
-	write32(&emi_reg->iocm, 0xa8a8a8a8);
-	write32(&emi_reg->iocm_2nd, 0x25252525);
-	write32(&emi_reg->testb, 0x00060037);
-	write32(&emi_reg->testc, 0x384a0014);
-	write32(&emi_reg->testd, 0xa0000000);
-	write32(&emi_reg->arba, 0x20107244);
-	write32(&emi_reg->arbb, 0x10107044);
-	write32(&emi_reg->arbc, 0x343450df);
-	write32(&emi_reg->arbd, 0x0000f0d0);
-	write32(&emi_reg->arbe, 0x10106048);
-	write32(&emi_reg->arbf, 0x343450df);
-	write32(&emi_reg->arbg, 0x83837044);
-	write32(&emi_reg->arbh, 0x83837044);
-	write32(&emi_reg->arbi, 0x00007108);
-	write32(&emi_reg->arbi_2nd, 0x00007108);
-	write32(&emi_reg->arbk, 0x090a4000);
-	write32(&emi_reg->slct, 0xff0bff00);
-	write32(&emi_reg->bmen, 0x00ff0001);
-	write32(&emi_reg->clua, 0x10000008);
-	write32(&emi_reg->slva, 0xffffffff);
-	write32(&emi_reg->thro_os0, 0x24240101);
-	write32(&emi_reg->thro_os1, 0x01012424);
-	write32(&emi_reg->thro_os2, 0x50500101);
-	write32(&emi_reg->thro_os3, 0x01015050);
-	write32(&emi_reg->thro_ctrl0, 0x0fc39a30);
-	write32(&emi_reg->thro_prd0, 0x05050003);
-	write32(&emi_reg->thro_prd1, 0x254dffff);
-	write32(&emi_reg->thro_lat0, 0x465a788c);
-	write32(&emi_reg->thro_lat1, 0x000003e8);
-	write32(&emi_reg->thro_lat2, 0x0000036b);
-	write32(&emi_reg->thro_lat3, 0x00000290);
-	write32(&emi_reg->thro_lat4, 0x00000200);
-	write32(&emi_reg->thro_lat5, 0x00000000);
-	write32(&emi_reg->thro_lat6, 0x00000000);
-	write32(&emi_reg->thro_ctrl1, 0x02531cff);
-	write32(&emi_reg->thro_prd2, 0x00002785);
-	write32(&emi_reg->thro_lat7, 0x000001b5);
-	write32(&emi_reg->thro_lat8, 0x003c0000);
-	write32(&emi_reg->thro_prd3, 0x0255250d);
-	write32(&emi_reg->bwlmta, 0xffff3c59);
-	write32(&emi_reg->bwlmtb, 0xffff00ff);
-	write32(&emi_reg->bwlmte, 0xffffffff);
-	write32(&emi_reg->bwlmtf, 0x0000ffff);
-	write32(&emi_reg->thro_lat9, 0x0000014b);
-	write32(&emi_reg->thro_lat10, 0x002d0000);
-	write32(&emi_reg->thro_lat11, 0x00000185);
-	write32(&emi_reg->thro_lat12, 0x003c0000);
-	write32(&emi_reg->thro_lat13, 0x00000185);
-	write32(&emi_reg->thro_lat14, 0x003c0000);
-	write32(&emi_reg->bwlmte_2nd, 0xffffffff);
-	write32(&emi_reg->bwlmtf_2nd, 0xffffffff);
-	write32(&emi_reg->bwlmtg_2nd, 0xffffffff);
-	write32(&emi_reg->bwlmte_4th, 0xffffffff);
-	write32(&emi_reg->bwlmtf_4th, 0x0000ffff);
-	write32(&emi_reg->bwlmte_5th, 0xffffffff);
-	write32(&emi_reg->bwlmtf_5th, 0xffffffff);
-	write32(&emi_reg->bwlmtg_5th, 0xffffffff);
-	write32(&emi_reg->thro_lat27, 0x41547082);
-	write32(&emi_reg->thro_lat28, 0x38382a38);
-	write32(&emi_reg->thro_lat29, 0x000001d4);
-	write32(&emi_reg->thro_lat30, 0x00000190);
-	write32(&emi_reg->thro_lat31, 0x0000012c);
-	write32(&emi_reg->thro_lat32, 0x000000ed);
-	write32(&emi_reg->thro_lat33, 0x000000c8);
-	write32(&emi_reg->thro_lat34, 0x00000096);
-	write32(&emi_reg->thro_lat35, 0x000000c8);
-	write32(&emi_reg->thro_lat36, 0x000000c8);
-	write32(&emi_reg->thro_lat41, 0x26304048);
-	write32(&emi_reg->thro_lat42, 0x20201820);
-	write32(&emi_reg->thro_lat55, 0x181e282f);
-	write32(&emi_reg->thro_lat56, 0x14140f18);
-	write32(&emi_reg->thro_lat69, 0x7496c8ea);
-	write32(&emi_reg->thro_lat70, 0x64644b64);
-	write32(&emi_reg->thro_lat83, 0x01010101);
-	write32(&emi_reg->thro_lat84, 0x01010101);
-	write32(&emi_reg->thro_lat97, 0x7496c8ea);
-	write32(&emi_reg->thro_lat98, 0x64644b64);
-	write32(&emi_reg->thro_lat111, 0x01010101);
-	write32(&emi_reg->thro_lat112, 0x01010101);
-	write32(&emi_reg->thro_prd5, 0x300ff025);
-	write32(&emi_reg->thro_lat113, 0x000003e8);
-	write32(&emi_reg->thro_lat114, 0x0000036b);
-	write32(&emi_reg->thro_lat115, 0x00000290);
-	write32(&emi_reg->thro_lat116, 0x00000200);
-	write32(&emi_reg->thro_lat117, 0x000001b5);
-	write32(&emi_reg->thro_lat118, 0x0000014b);
-	write32(&emi_reg->thro_lat119, 0x00000185);
-	write32(&emi_reg->thro_lat120, 0x00000185);
-	write32(&emi_reg->thro_lat125, 0x52698ca0);
-	write32(&emi_reg->thro_lat126, 0x46463546);
-	write32(&emi_reg->thro_lat139, 0x01010101);
-	write32(&emi_reg->thro_lat140, 0x01010101);
-	write32(&emi_reg->qos_mdr_be0a, 0x00000009);
-	write32(&emi_reg->qos_mdr_be1a, 0x00000000);
-	write32(&emi_reg->qos_mdr_shf0, 0x00730000);
-	write32(&emi_reg->qos_mdr_shf1, 0x00000808);
-	write32(&emi_reg->qos_mdw_be0a, 0x00000028);
-	write32(&emi_reg->qos_mdw_be1a, 0x00000000);
-	write32(&emi_reg->qos_mdw_shf0, 0x00730000);
-	write32(&emi_reg->qos_mdw_shf1, 0x00000808);
-	write32(&emi_reg->qos_apr_be0a, 0x00000080);
-	write32(&emi_reg->qos_apr_be1a, 0x00000000);
-	write32(&emi_reg->qos_apr_shf0, 0x30201008);
-	write32(&emi_reg->qos_apw_be0a, 0x00000800);
-	write32(&emi_reg->qos_apw_be1a, 0x00000000);
-	write32(&emi_reg->qos_mmr_be0a, 0x00008000);
-	write32(&emi_reg->qos_mmr_be1a, 0x00020000);
-	write32(&emi_reg->qos_mmr_be1b, 0x00001000);
-	write32(&emi_reg->qos_mmr_be2a, 0x00010000);
-	write32(&emi_reg->qos_mmr_be2b, 0x00000800);
-	write32(&emi_reg->qos_mmr_shf0, 0x08080000);
-	write32(&emi_reg->qos_mmr_shf1, 0x00073030);
-	write32(&emi_reg->qos_mmw_be0a, 0x00040000);
-	write32(&emi_reg->qos_mmw_be1a, 0x00100000);
-	write32(&emi_reg->qos_mmw_be1b, 0x00004000);
-	write32(&emi_reg->qos_mmw_be2a, 0x00080000);
-	write32(&emi_reg->qos_mmw_be2b, 0x00002000);
-	write32(&emi_reg->qos_mmw_shf0, 0x08080000);
-	write32(&emi_reg->qos_mmw_shf1, 0x00074040);
-	write32(&emi_reg->qos_mdhwr_be0a, 0x00400000);
-	write32(&emi_reg->qos_mdhwr_be1a, 0x00200000);
-	write32(&emi_reg->qos_mdhwr_shf0, 0x10100404);
-	write32(&emi_reg->qos_mdhww_be0a, 0x01000000);
-	write32(&emi_reg->qos_mdhww_be1a, 0x00800000);
-	write32(&emi_reg->qos_gpur_be0a, 0x04000000);
-	write32(&emi_reg->qos_gpur_be1a, 0x02000000);
-	write32(&emi_reg->qos_gpur_shf0, 0x60602010);
-	write32(&emi_reg->qos_gpuw_be0a, 0x10000000);
-	write32(&emi_reg->qos_gpuw_be1a, 0x08000000);
-	write32(&emi_reg->qos_arbr_be0a, 0x00000009);
-	write32(&emi_reg->qos_arbr_be1a, 0x04400080);
-	write32(&emi_reg->qos_arbr_shf0, 0x0f170f11);
-	write32(&emi_reg->qos_ctrl1, 0x0303f7f7);
-	write32(&emi_reg->ext_lt_con1_1st, 0x00000166);
-	write32(&emi_reg->ext_lt_con2_1st, 0xffffffff);
-	write32(&emi_reg->ext_lt_con3_1st, 0xffffffff);
-	write32(&emi_reg->ext_lt_con1_2nd, 0x00400166);
-	write32(&emi_reg->ext_lt_con2_2nd, 0xffffffff);
-	write32(&emi_reg->ext_lt_con3_2nd, 0xffffffff);
-	write32(&emi_reg->ext_lt_con1_3rd, 0x00000266);
-	write32(&emi_reg->ext_lt_con2_3rd, 0xffffffff);
-	write32(&emi_reg->ext_lt_con3_3rd, 0xffffffff);
-	write32(&emi_reg->ext_lt_con1_4th, 0x00400266);
-	write32(&emi_reg->ext_lt_con2_4th, 0xffffffff);
-	write32(&emi_reg->ext_lt_con3_4th, 0xffffffff);
-	write32(&emi_reg->prtcl_m0_cyc, 0xffffffff);
-	write32(&emi_reg->prtcl_m0_ctl, 0x001ffc85);
-	write32(&emi_reg->prtcl_m0_msk, 0xffffffff);
-	write32(&emi_reg->prtcl_m1_cyc, 0xffffffff);
-	write32(&emi_reg->prtcl_m1_ctl, 0x001ffc85);
-	write32(&emi_reg->prtcl_m1_msk, 0xffffffff);
-	write32(&emi_reg->prtcl_m2_cyc, 0xffffffff);
-	write32(&emi_reg->prtcl_m2_ctl, 0x001ffc85);
-	write32(&emi_reg->prtcl_m2_msk, 0xffffffff);
-	write32(&emi_reg->prtcl_m3_cyc, 0xffffffff);
-	write32(&emi_reg->prtcl_m3_ctl, 0x001ffc85);
-	write32(&emi_reg->prtcl_m3_msk, 0xffffffff);
-	write32(&emi_reg->prtcl_m4_cyc, 0xffffffff);
-	write32(&emi_reg->prtcl_m4_ctl, 0x001ffc85);
-	write32(&emi_reg->prtcl_m4_msk, 0xffffffff);
-	write32(&emi_reg->prtcl_m5_cyc, 0xffffffff);
-	write32(&emi_reg->prtcl_m5_ctl, 0x001ffc85);
-	write32(&emi_reg->prtcl_m5_msk, 0xffffffff);
-	write32(&emi_reg->prtcl_m6_cyc, 0xffffffff);
-	write32(&emi_reg->prtcl_m6_ctl, 0x001ffc85);
-	write32(&emi_reg->prtcl_m6_msk, 0xffffffff);
-	write32(&emi_reg->prtcl_m7_cyc, 0xffffffff);
-	write32(&emi_reg->prtcl_m7_ctl, 0x001ffc85);
-	write32(&emi_reg->prtcl_m7_msk, 0xffffffff);
-	write32(&emi_reg->dvfs_shf_con, 0x00000000);
-	write32(&emi_reg->mxto0, 0x60606060);
-	write32(&emi_reg->mxto1, 0x60606060);
-	write32(&emi_reg->conk, 0x00000000);
-	write32(&emi_reg->thro_slv_con0, 0x08ffbbff);
-	write32(&emi_reg->thro_slv_con1, 0xffff5b3c);
-	write32(&emi_reg->bwlmte_8th, 0xffff00ff);
-	write32(&emi_reg->bwlmtf_8th, 0x00ffffff);
-	write32(&emi_reg->bwlmtg_8th, 0xffff00ff);
-	write32(&emi_reg->bwlmth_8th, 0x00ffffff);
-	write32(&emi_reg->bwlmtg_7th, 0x00000000);
-	write32(&emi_reg->chn_hash0, 0xC0000000);
-}
-
-static void emi_chn_config(void)
-{
-	struct emi_chn_regs *emi_chn = &ch->emi_chn;
-
-	/* set EMI channel default settings which EMI hardware needs */
-	write32(&emi_chn->cona, 0x0400f051);
-	write32(&emi_chn->conb, 0x00ff6048);
-	write32(&emi_chn->conc, 0x00000004);
-	write32(&emi_chn->mdct, 0x99f08c03);
-	write32(&emi_chn->shf0, 0x9a508c17);
-	write32(&emi_chn->testb, 0x00038137);
-	write32(&emi_chn->testc, 0x38460002);
-	write32(&emi_chn->testd, 0x00000000);
-	write32(&emi_chn->ap_early_cke, 0x000002ff);
-	write32(&emi_chn->dqfr, 0x00003111);
-	write32(&emi_chn->arbi, 0x22607188);
-	write32(&emi_chn->arbi_2nd, 0x22607188);
-	write32(&emi_chn->arbj, 0x3719595e);
-	write32(&emi_chn->arbj_2nd, 0x2719595e);
-	write32(&emi_chn->arbk, 0x64f3ff79);
-	write32(&emi_chn->arbk_2nd, 0x64f3ff79);
-	write32(&emi_chn->slct, 0x011b0868);
-	write32(&emi_chn->arb_rff, 0xa7414222);
-	write32(&emi_chn->drs_mon0, 0x0000f801);
-	write32(&emi_chn->drs_mon1, 0x40000000);
-	write32(&emi_chn->rkarb0, 0x000c802f);
-	write32(&emi_chn->rkarb1, 0xbd3f3f7e);
-	write32(&emi_chn->rkarb2, 0x7e003d7e);
-	write32(&emi_chn->eco3, 0x00000000);
-	write32(&emi_chn->md_pre_mask, 0xaa0148ff);
-	write32(&emi_chn->md_pre_mask_shf, 0xaa6168ff);
-	write32(&emi_chn->md_pre_mask_shf0, 0xaa516cff);
-	write32(&emi_chn->md_pre_mask_shf1, 0xaa0140ff);
-	write32(&emi_chn->qos_mdr_shf0, 0x9f658633);
-}
-
-static void emi_init(void)
-{
-	dramc_set_broadcast(DRAMC_BROADCAST_ON);
-	emi_center_config();
-	emi_chn_config();
-	dramc_set_broadcast(DRAMC_BROADCAST_OFF);
-}
-
-void emi_mdl_init(const struct emi_mdl *emi_con)
-{
-	emi_init();
-
-	write32(&emi_reg->cona, emi_con->cona_val);
-	write32(&emi_reg->conf, emi_con->conf_val);
-	write32(&emi_reg->conh, emi_con->conh_val);
-	for (u8 chn = CHANNEL_A; chn < CHANNEL_MAX; chn++)
-		write32(&ch[chn].emi_chn.cona, emi_con->chn_cona_val);
-}
-
-u32 get_column_num(void)
-{
-	u32 ma_type = read32(&emi_reg->cona);
-	u32 ma_type_r0 = ((ma_type >> 20) & 0x3) + 1;
-	u32 ma_type_r1 = ((ma_type >> 22) & 0x3) + 1;
-
-	ma_type = MIN(ma_type_r0, ma_type_r1);
-
-	return ma_type;
-}
-
-static void emi_sw_setting(void)
-{
-	setbits32(&emi_mpu->mpu_ctrl_d[1], BIT(4));
-	setbits32(&emi_mpu->mpu_ctrl_d[7], BIT(4));
-
-	/* set EMI default bandwidth threshold */
-	write32(&emi_reg->bwct0, 0x05008305);
-	write32(&emi_reg->bwct0_6th, 0x08ff8705);
-	write32(&emi_reg->bwct0_3rd, 0x0dff8a05);
-	setbits32(&emi_reg->thro_ctrl1, 0x3 << 8);
-}
-
-static void dramc_dcm_setting(void)
-{
-	/* set EMI dcm default settgings */
-	write32(&infra_ao_mem->emi_idle_bit_en_0, 0xFFFFFFFF);
-	write32(&infra_ao_mem->emi_idle_bit_en_1, 0xFFFFFFFF);
-	write32(&infra_ao_mem->emi_idle_bit_en_2, 0xFFFFFFFF);
-	write32(&infra_ao_mem->emi_idle_bit_en_3, 0xFFFFFFFF);
-	write32(&infra_ao_mem->emi_m0m1_idle_bit_en_0, 0x01F00000);
-	write32(&infra_ao_mem->emi_m0m1_idle_bit_en_1, 0xC0040180);
-	write32(&infra_ao_mem->emi_m0m1_idle_bit_en_2, 0x00000000);
-	write32(&infra_ao_mem->emi_m0m1_idle_bit_en_3, 0x00000003);
-	write32(&infra_ao_mem->emi_m2m5_idle_bit_en_0, 0x0C000000);
-	write32(&infra_ao_mem->emi_m2m5_idle_bit_en_1, 0x00C00000);
-	write32(&infra_ao_mem->emi_m2m5_idle_bit_en_2, 0x01F08000);
-	write32(&infra_ao_mem->emi_m2m5_idle_bit_en_3, 0x00000000);
-	write32(&infra_ao_mem->emi_m3_idle_bit_en_0, 0x20003040);
-	write32(&infra_ao_mem->emi_m3_idle_bit_en_1, 0x00000000);
-	write32(&infra_ao_mem->emi_m3_idle_bit_en_2, 0x00001000);
-	write32(&infra_ao_mem->emi_m3_idle_bit_en_3, 0x00000000);
-	write32(&infra_ao_mem->emi_m4_idle_bit_en_0, 0x10020F20);
-	write32(&infra_ao_mem->emi_m4_idle_bit_en_1, 0x00019000);
-	write32(&infra_ao_mem->emi_m4_idle_bit_en_2, 0x040A0818);
-	write32(&infra_ao_mem->emi_m4_idle_bit_en_3, 0x00000370);
-	write32(&infra_ao_mem->emi_m6m7_idle_bit_en_0, 0xC001C080);
-	write32(&infra_ao_mem->emi_m6m7_idle_bit_en_1, 0x33000E01);
-	write32(&infra_ao_mem->emi_m6m7_idle_bit_en_2, 0x180067E1);
-	write32(&infra_ao_mem->emi_m6m7_idle_bit_en_3, 0x000C008C);
-	write32(&infra_ao_mem->emi_sram_idle_bit_en_0, 0x020C0008);
-	write32(&infra_ao_mem->emi_sram_idle_bit_en_1, 0x0C00007E);
-	write32(&infra_ao_mem->emi_sram_idle_bit_en_2, 0x80050006);
-	write32(&infra_ao_mem->emi_sram_idle_bit_en_3, 0x00030000);
-
-	write32(&infra_ao_mem->emi_dcm_cfg0, 0x0000000F);
-	write32(&infra_ao_mem->emi_dcm_cfg1, 0x00000000);
-	write32(&infra_ao_mem->emi_dcm_cfg2, 0x001F0044);
-	write32(&infra_ao_mem->top_ck_anchor_cfg, 0x200000FF);
-
-	setbits32(&mt8192_infracfg->mem_dcm_ctrl, BIT(27));
-}
-
-static void dramc_dcm_setting2(void)
-{
-	u32 emi_temp_data;
-
-	write32(&infra_ao_mem->emi_disph_cfg, 0x00000007);
-	write32(&infra_ao_mem->emi_disph_cfg, 0x80000007);
-
-	emi_temp_data = read32(&infra_ao_mem->emi_disph_cfg);
-	emi_temp_data = emi_temp_data & 0xf;
-	setbits32(&emi_reg->chn_hash0, emi_temp_data);
-}
-
-void emi_init2(void)
-{
-	u32 tmp;
-	u32 bc_bak;
-	struct emi_chn_regs *emi_chn = &ch->emi_chn;
-
-	bc_bak = dramc_get_broadcast();
-	dramc_set_broadcast(DRAMC_BROADCAST_ON);
-	setbits32(&emi_chn->conc, 0x1);
-	setbits32(&emi_reg->conm, BIT(10));
-	setbits32(&emi_mpu->mpu_ctrl, BIT(4));
-
-	clrbits32(&emi_chn->rkarb0, 0x1);
-	tmp = read32(&emi_chn->cona) & 0x1;
-	setbits32(&emi_chn->rkarb0, tmp);
-
-	dramc_dcm_setting();
-
-	/* do basic memory read/write for adjusting EMI HW settings */
-	write32((void *)_dram, read32((void *)_dram));
-	write32((void *)(_dram + 0x100), read32((void *)(_dram + 0x100)));
-	write32((void *)(_dram + 0x200), read32((void *)(_dram + 0x200)));
-	write32((void *)(_dram + 0x300), read32((void *)(_dram + 0x300)));
-
-	setbits32(&emi_reg->conn, BIT(22));
-	setbits32(&emi_chn->testc, BIT(2));
-
-	dramc_dcm_setting2();
-
-	setbits32(&emi_reg->conn, BIT(21));
-	setbits32(&emi_chn->testc, BIT(4));
-	write32(&emi_chn->ebg_con, 0x40);
-
-	dramc_set_broadcast(DRAMC_BROADCAST_OFF);
-	emi_sw_setting();
-	dramc_set_broadcast(bc_bak);
-}
-
-size_t sdram_size(void)
-{
-	size_t dram_size = 0x100000000;
-
-	return dram_size;
-}
-
-void mt_set_emi(struct dramc_param *dparam)
-{
-	init_dram(&dparam->dramc_datas);
-}
diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h b/src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h
deleted file mode 100644
index f00101a3a9..0000000000
--- a/src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h
+++ /dev/null
@@ -1,972 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __SOC_MEDIATEK_MT8192_DRAMC_AC_TIMING_H__
-#define __SOC_MEDIATEK_MT8192_DRAMC_AC_TIMING_H__
-
-#include <stdint.h>
-#include <sys/types.h>
-#include <soc/dramc_common_mt8192.h>
-#include <soc/dramc_pi_api.h>
-
-/* Normal Mode and Byte Mode */
-#define AC_TIMING_NUMBER	(DDRFREQ_MAX * 2)
-
-struct ac_timing {
-	u8 cbt_mode, read_dbi;
-	u8 div_mode;
-	u16 freq_group;
-	u16 read_lat, write_lat;
-	u16 dqsinctl, datlat;
-	u16 tras;
-	u16 trp;
-	u16 trpab;
-	u16 trc;
-	u16 trfc;
-	u16 trfcpb;
-	u16 txp;
-	u16 trtp;
-	u16 trcd;
-	u16 twr;
-	u16 twtr;
-	u16 tpbr2pbr;
-	u16 tpbr2act;
-	u16 tr2mrw;
-	u16 tw2mrw;
-	u16 tmrr2mrw;
-	u16 tmrw;
-	u16 tmrd;
-	u16 tmrwckel;
-	u16 tpde;
-	u16 tpdx;
-	u16 tmrri;
-	u16 trrd;
-	u16 trrd_4266;
-	u16 tfaw;
-	u16 tfaw_4266;
-	u16 trtw_odt_off;
-	u16 trtw_odt_on;
-	u16 txrefcnt;
-	u16 tzqcs;
-	u16 xrtw2w_new_mode;
-	u16 xrtw2w_old_mode;
-	u16 xrtw2r_odt_on;
-	u16 xrtw2r_odt_off;
-	u16 xrtr2w_odt_on;
-	u16 xrtr2w_odt_off;
-	u16 xrtr2r_new_mode;
-	u16 xrtr2r_old_mode;
-	u16 tr2mrr;
-	u16 vrcgdis_prdcnt;
-	u16 hwset_mr2_op;
-	u16 hwset_mr13_op;
-	u16 hwset_vrcg_op;
-	u16 trcd_derate;
-	u16 trc_derate;
-	u16 tras_derate;
-	u16 trpab_derate;
-	u16 trp_derate;
-	u16 trrd_derate;
-	u16 trtpd;
-	u16 twtpd;
-	u16 tmrr2w_odt_off;
-	u16 tmrr2w_odt_on;
-	u16 ckeprd;
-	u16 ckelckcnt;
-	u16 zqlat2;
-	u16 tras_05T;
-	u16 trp_05T;
-	u16 trpab_05T;
-	u16 trc_05T;
-	u16 trfc_05T;
-	u16 trfcpb_05T;
-	u16 txp_05T;
-	u16 trtp_05T;
-	u16 trcd_05T;
-	u16 twr_05T;
-	u16 twtr_05T;
-	u16 tpbr2pbr_05T;
-	u16 tpbr2act_05T;
-	u16 tr2mrw_05T;
-	u16 tw2mrw_05T;
-	u16 tmrr2mrw_05T;
-	u16 tmrw_05T;
-	u16 tmrd_05T;
-	u16 tmrwckel_05T;
-	u16 tpde_05T;
-	u16 tpdx_05T;
-	u16 tmrri_05T;
-	u16 trrd_05T;
-	u16 trrd_4266_05T;
-	u16 tfaw_05T;
-	u16 tfaw_4266_05T;
-	u16 trtw_odt_off_05T;
-	u16 trtw_odt_on_05T;
-	u16 trcd_derate_05T;
-	u16 trc_derate_05T;
-	u16 tras_derate_05T;
-	u16 trpab_derate_05T;
-	u16 trp_derate_05T;
-	u16 trrd_derate_05T;
-	u16 trtpd_05T;
-	u16 twtpd_05T;
-};
-
-/* Normal Mode and Byte Mode for each frequency */
-static const struct ac_timing ac_timing_tbl[AC_TIMING_NUMBER] = {
-	{
-		.freq_group = DDRFREQ_2133, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
-		.read_lat = 36, .write_lat =  18, .div_mode =  DIV8_MODE,
-		.tras = 14, .tras_05T = 0,
-		.trp = 8, .trp_05T = 1,
-		.trpab = 10, .trpab_05T = 0,
-		.trc = 23, .trc_05T = 0,
-		.trfc = 137, .trfc_05T = 1,
-		.trfcpb = 63, .trfcpb_05T = 0,
-		.txp = 1, .txp_05T = 0,
-		.trtp = 2, .trtp_05T = 1,
-		.trcd = 10, .trcd_05T = 0,
-		.twr = 15, .twr_05T = 0,
-		.twtr = 10, .twtr_05T = 1,
-		.tpbr2pbr = 41, .tpbr2pbr_05T = 0,
-		.tpbr2act = 0, .tpbr2act_05T = 0,
-		.tr2mrw = 17, .tr2mrw_05T = 0,
-		.tw2mrw = 11, .tw2mrw_05T = 0,
-		.tmrr2mrw = 14, .tmrr2mrw_05T = 0,
-		.tmrw = 6, .tmrw_05T = 0,
-		.tmrd = 8, .tmrd_05T = 0,
-		.tmrwckel = 9, .tmrwckel_05T = 0,
-		.tpde = 1, .tpde_05T = 1,
-		.tpdx = 1, .tpdx_05T = 0,
-		.tmrri = 14, .tmrri_05T = 0,
-		.trrd = 4, .trrd_05T = 1,
-		.trrd_4266 = 3, .trrd_4266_05T = 0,
-		.tfaw = 13, .tfaw_05T = 1,
-		.tfaw_4266 = 8, .tfaw_4266_05T = 0,
-		.trtw_odt_off = 6, .trtw_odt_off_05T = 0,
-		.trtw_odt_on = 8, .trtw_odt_on_05T = 0,
-		.txrefcnt = 154,
-		.tzqcs = 46,
-		.xrtw2w_new_mode = 5,
-		.xrtw2w_old_mode = 6,
-		.xrtw2r_odt_on = 1,
-		.xrtw2r_odt_off = 1,
-		.xrtr2w_odt_on = 7,
-		.xrtr2w_odt_off = 7,
-		.xrtr2r_new_mode = 3,
-		.xrtr2r_old_mode = 7,
-		.tr2mrr = 4,
-		.vrcgdis_prdcnt = 54,
-		.hwset_mr2_op = 63,
-		.hwset_mr13_op = 216,
-		.hwset_vrcg_op = 208,
-		.trcd_derate = 11, .trcd_derate_05T = 0,
-		.trc_derate = 26, .trc_derate_05T = 0,
-		.tras_derate = 15, .tras_derate_05T = 0,
-		.trpab_derate = 11, .trpab_derate_05T = 0,
-		.trp_derate = 9, .trp_derate_05T = 1,
-		.trrd_derate = 5, .trrd_derate_05T = 1,
-		.trtpd = 14, .trtpd_05T = 1,
-		.twtpd = 18, .twtpd_05T = 0,
-		.tmrr2w_odt_off = 10,
-		.tmrr2w_odt_on = 12,
-		.ckeprd = 3,
-		.ckelckcnt = 3,
-		.zqlat2 = 16,
-		.dqsinctl = 7, .datlat = 18
-	},
-	{
-		.freq_group = DDRFREQ_2133, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
-		.read_lat = 40, .write_lat =  18, .div_mode =  DIV8_MODE,
-		.tras = 14, .tras_05T = 0,
-		.trp = 8, .trp_05T = 1,
-		.trpab = 10, .trpab_05T = 0,
-		.trc = 23, .trc_05T = 0,
-		.trfc = 137, .trfc_05T = 1,
-		.trfcpb = 63, .trfcpb_05T = 0,
-		.txp = 1, .txp_05T = 0,
-		.trtp = 2, .trtp_05T = 1,
-		.trcd = 10, .trcd_05T = 0,
-		.twr = 16, .twr_05T = 0,
-		.twtr = 11, .twtr_05T = 1,
-		.tpbr2pbr = 41, .tpbr2pbr_05T = 0,
-		.tpbr2act = 0, .tpbr2act_05T = 0,
-		.tr2mrw = 18, .tr2mrw_05T = 0,
-		.tw2mrw = 11, .tw2mrw_05T = 0,
-		.tmrr2mrw = 15, .tmrr2mrw_05T = 0,
-		.tmrw = 6, .tmrw_05T = 0,
-		.tmrd = 8, .tmrd_05T = 0,
-		.tmrwckel = 9, .tmrwckel_05T = 0,
-		.tpde = 1, .tpde_05T = 1,
-		.tpdx = 1, .tpdx_05T = 0,
-		.tmrri = 14, .tmrri_05T = 0,
-		.trrd = 4, .trrd_05T = 1,
-		.trrd_4266 = 3, .trrd_4266_05T = 0,
-		.tfaw = 13, .tfaw_05T = 1,
-		.tfaw_4266 = 8, .tfaw_4266_05T = 0,
-		.trtw_odt_off = 7, .trtw_odt_off_05T = 0,
-		.trtw_odt_on = 9, .trtw_odt_on_05T = 0,
-		.txrefcnt = 154,
-		.tzqcs = 46,
-		.xrtw2w_new_mode = 5,
-		.xrtw2w_old_mode = 6,
-		.xrtw2r_odt_on = 1,
-		.xrtw2r_odt_off = 1,
-		.xrtr2w_odt_on = 8,
-		.xrtr2w_odt_off = 8,
-		.xrtr2r_new_mode = 3,
-		.xrtr2r_old_mode = 7,
-		.tr2mrr = 4,
-		.vrcgdis_prdcnt = 54,
-		.hwset_mr2_op = 63,
-		.hwset_mr13_op = 216,
-		.hwset_vrcg_op = 208,
-		.trcd_derate = 11, .trcd_derate_05T = 0,
-		.trc_derate = 26, .trc_derate_05T = 0,
-		.tras_derate = 15, .tras_derate_05T = 0,
-		.trpab_derate = 11, .trpab_derate_05T = 0,
-		.trp_derate = 9, .trp_derate_05T = 1,
-		.trrd_derate = 5, .trrd_derate_05T = 1,
-		.trtpd = 15, .trtpd_05T = 1,
-		.twtpd = 19, .twtpd_05T = 0,
-		.tmrr2w_odt_off = 11,
-		.tmrr2w_odt_on = 13,
-		.ckeprd = 3,
-		.ckelckcnt = 3,
-		.zqlat2 = 16,
-		.dqsinctl = 7, .datlat = 18
-	},
-	{
-		.freq_group = DDRFREQ_1600, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
-		.read_lat = 28, .write_lat =  14, .div_mode =  DIV8_MODE,
-		.tras = 8, .tras_05T = 1,
-		.trp = 6, .trp_05T = 0,
-		.trpab = 7, .trpab_05T = 0,
-		.trc = 15, .trc_05T = 0,
-		.trfc = 100, .trfc_05T = 0,
-		.trfcpb = 44, .trfcpb_05T = 0,
-		.txp = 0, .txp_05T = 0,
-		.trtp = 1, .trtp_05T = 1,
-		.trcd = 7, .trcd_05T = 1,
-		.twr = 12, .twr_05T = 1,
-		.twtr = 7, .twtr_05T = 0,
-		.tpbr2pbr = 29, .tpbr2pbr_05T = 0,
-		.tpbr2act = 0, .tpbr2act_05T = 0,
-		.tr2mrw = 13, .tr2mrw_05T = 1,
-		.tw2mrw = 9, .tw2mrw_05T = 0,
-		.tmrr2mrw = 11, .tmrr2mrw_05T = 1,
-		.tmrw = 4, .tmrw_05T = 1,
-		.tmrd = 6, .tmrd_05T = 1,
-		.tmrwckel = 7, .tmrwckel_05T = 1,
-		.tpde = 1, .tpde_05T = 1,
-		.tpdx = 1, .tpdx_05T = 0,
-		.tmrri = 10, .tmrri_05T = 1,
-		.trrd = 3, .trrd_05T = 0,
-		.trrd_4266 = 2, .trrd_4266_05T = 0,
-		.tfaw = 8, .tfaw_05T = 0,
-		.tfaw_4266 = 4, .tfaw_4266_05T = 0,
-		.trtw_odt_off = 4, .trtw_odt_off_05T = 0,
-		.trtw_odt_on = 6, .trtw_odt_on_05T = 0,
-		.txrefcnt = 115,
-		.tzqcs = 34,
-		.xrtw2w_new_mode = 4,
-		.xrtw2w_old_mode = 6,
-		.xrtw2r_odt_on = 1,
-		.xrtw2r_odt_off = 1,
-		.xrtr2w_odt_on = 5,
-		.xrtr2w_odt_off = 5,
-		.xrtr2r_new_mode = 3,
-		.xrtr2r_old_mode = 7,
-		.tr2mrr = 4,
-		.vrcgdis_prdcnt = 40,
-		.hwset_mr2_op = 45,
-		.hwset_mr13_op = 216,
-		.hwset_vrcg_op = 208,
-		.trcd_derate = 8, .trcd_derate_05T = 0,
-		.trc_derate = 17, .trc_derate_05T = 0,
-		.tras_derate = 9, .tras_derate_05T = 1,
-		.trpab_derate = 8, .trpab_derate_05T = 0,
-		.trp_derate = 6, .trp_derate_05T = 1,
-		.trrd_derate = 4, .trrd_derate_05T = 0,
-		.trtpd = 12, .trtpd_05T = 0,
-		.twtpd = 14, .twtpd_05T = 1,
-		.tmrr2w_odt_off = 8,
-		.tmrr2w_odt_on = 10,
-		.ckeprd = 2,
-		.ckelckcnt = 2,
-		.zqlat2 = 12,
-		.dqsinctl = 5, .datlat = 15
-	},
-	{
-		.freq_group = DDRFREQ_1600, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
-		.read_lat = 32, .write_lat =  14, .div_mode =  DIV8_MODE,
-		.tras = 8, .tras_05T = 1,
-		.trp = 6, .trp_05T = 0,
-		.trpab = 7, .trpab_05T = 0,
-		.trc = 15, .trc_05T = 0,
-		.trfc = 100, .trfc_05T = 0,
-		.trfcpb = 44, .trfcpb_05T = 0,
-		.txp = 0, .txp_05T = 0,
-		.trtp = 1, .trtp_05T = 1,
-		.trcd = 7, .trcd_05T = 1,
-		.twr = 12, .twr_05T = 1,
-		.twtr = 8, .twtr_05T = 0,
-		.tpbr2pbr = 29, .tpbr2pbr_05T = 0,
-		.tpbr2act = 0, .tpbr2act_05T = 0,
-		.tr2mrw = 14, .tr2mrw_05T = 1,
-		.tw2mrw = 9, .tw2mrw_05T = 0,
-		.tmrr2mrw = 12, .tmrr2mrw_05T = 1,
-		.tmrw = 4, .tmrw_05T = 1,
-		.tmrd = 6, .tmrd_05T = 1,
-		.tmrwckel = 7, .tmrwckel_05T = 1,
-		.tpde = 1, .tpde_05T = 1,
-		.tpdx = 1, .tpdx_05T = 0,
-		.tmrri = 10, .tmrri_05T = 1,
-		.trrd = 3, .trrd_05T = 0,
-		.trrd_4266 = 2, .trrd_4266_05T = 0,
-		.tfaw = 8, .tfaw_05T = 0,
-		.tfaw_4266 = 4, .tfaw_4266_05T = 0,
-		.trtw_odt_off = 5, .trtw_odt_off_05T = 0,
-		.trtw_odt_on = 7, .trtw_odt_on_05T = 0,
-		.txrefcnt = 115,
-		.tzqcs = 34,
-		.xrtw2w_new_mode = 4,
-		.xrtw2w_old_mode = 6,
-		.xrtw2r_odt_on = 1,
-		.xrtw2r_odt_off = 1,
-		.xrtr2w_odt_on = 6,
-		.xrtr2w_odt_off = 6,
-		.xrtr2r_new_mode = 3,
-		.xrtr2r_old_mode = 7,
-		.tr2mrr = 4,
-		.vrcgdis_prdcnt = 40,
-		.hwset_mr2_op = 45,
-		.hwset_mr13_op = 216,
-		.hwset_vrcg_op = 208,
-		.trcd_derate = 8, .trcd_derate_05T = 0,
-		.trc_derate = 17, .trc_derate_05T = 0,
-		.tras_derate = 9, .tras_derate_05T = 1,
-		.trpab_derate = 8, .trpab_derate_05T = 0,
-		.trp_derate = 6, .trp_derate_05T = 1,
-		.trrd_derate = 4, .trrd_derate_05T = 0,
-		.trtpd = 13, .trtpd_05T = 0,
-		.twtpd = 15, .twtpd_05T = 1,
-		.tmrr2w_odt_off = 9,
-		.tmrr2w_odt_on = 11,
-		.ckeprd = 2,
-		.ckelckcnt = 2,
-		.zqlat2 = 12,
-		.dqsinctl = 5, .datlat = 15
-	},
-	{
-		.freq_group = DDRFREQ_1200, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
-		.read_lat = 24, .write_lat =  12, .div_mode =  DIV8_MODE,
-		.tras = 4, .tras_05T = 1,
-		.trp = 4, .trp_05T = 0,
-		.trpab = 5, .trpab_05T = 0,
-		.trc = 9, .trc_05T = 1,
-		.trfc = 72, .trfc_05T = 1,
-		.trfcpb = 30, .trfcpb_05T = 1,
-		.txp = 0, .txp_05T = 1,
-		.trtp = 1, .trtp_05T = 0,
-		.trcd = 5, .trcd_05T = 1,
-		.twr = 9, .twr_05T = 1,
-		.twtr = 6, .twtr_05T = 1,
-		.tpbr2pbr = 20, .tpbr2pbr_05T = 1,
-		.tpbr2act = 0, .tpbr2act_05T = 0,
-		.tr2mrw = 12, .tr2mrw_05T = 0,
-		.tw2mrw = 8, .tw2mrw_05T = 0,
-		.tmrr2mrw = 10, .tmrr2mrw_05T = 0,
-		.tmrw = 4, .tmrw_05T = 0,
-		.tmrd = 5, .tmrd_05T = 0,
-		.tmrwckel = 6, .tmrwckel_05T = 0,
-		.tpde = 1, .tpde_05T = 1,
-		.tpdx = 1, .tpdx_05T = 0,
-		.tmrri = 8, .tmrri_05T = 0,
-		.trrd = 2, .trrd_05T = 1,
-		.trrd_4266 = 1, .trrd_4266_05T = 1,
-		.tfaw = 4, .tfaw_05T = 1,
-		.tfaw_4266 = 1, .tfaw_4266_05T = 1,
-		.trtw_odt_off = 3, .trtw_odt_off_05T = 0,
-		.trtw_odt_on = 6, .trtw_odt_on_05T = 0,
-		.txrefcnt = 87,
-		.tzqcs = 26,
-		.xrtw2w_new_mode = 4,
-		.xrtw2w_old_mode = 6,
-		.xrtw2r_odt_on = 2,
-		.xrtw2r_odt_off = 2,
-		.xrtr2w_odt_on = 5,
-		.xrtr2w_odt_off = 5,
-		.xrtr2r_new_mode = 3,
-		.xrtr2r_old_mode = 6,
-		.tr2mrr = 4,
-		.vrcgdis_prdcnt = 31,
-		.hwset_mr2_op = 36,
-		.hwset_mr13_op = 24,
-		.hwset_vrcg_op = 16,
-		.trcd_derate = 6, .trcd_derate_05T = 0,
-		.trc_derate = 10, .trc_derate_05T = 1,
-		.tras_derate = 5, .tras_derate_05T = 0,
-		.trpab_derate = 5, .trpab_derate_05T = 1,
-		.trp_derate = 4, .trp_derate_05T = 1,
-		.trrd_derate = 3, .trrd_derate_05T = 0,
-		.trtpd = 10, .trtpd_05T = 1,
-		.twtpd = 12, .twtpd_05T = 0,
-		.tmrr2w_odt_off = 6,
-		.tmrr2w_odt_on = 8,
-		.ckeprd = 2,
-		.ckelckcnt = 2,
-		.zqlat2 = 10,
-		.dqsinctl = 4, .datlat = 13
-	},
-	{
-		.freq_group = DDRFREQ_1200, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
-		.read_lat = 26, .write_lat =  12, .div_mode =  DIV8_MODE,
-		.tras = 4, .tras_05T = 1,
-		.trp = 4, .trp_05T = 0,
-		.trpab = 5, .trpab_05T = 0,
-		.trc = 9, .trc_05T = 1,
-		.trfc = 72, .trfc_05T = 1,
-		.trfcpb = 30, .trfcpb_05T = 1,
-		.txp = 0, .txp_05T = 1,
-		.trtp = 1, .trtp_05T = 0,
-		.trcd = 5, .trcd_05T = 1,
-		.twr = 10, .twr_05T = 0,
-		.twtr = 6, .twtr_05T = 0,
-		.tpbr2pbr = 20, .tpbr2pbr_05T = 1,
-		.tpbr2act = 0, .tpbr2act_05T = 0,
-		.tr2mrw = 12, .tr2mrw_05T = 1,
-		.tw2mrw = 8, .tw2mrw_05T = 0,
-		.tmrr2mrw = 10, .tmrr2mrw_05T = 1,
-		.tmrw = 4, .tmrw_05T = 0,
-		.tmrd = 5, .tmrd_05T = 0,
-		.tmrwckel = 6, .tmrwckel_05T = 0,
-		.tpde = 1, .tpde_05T = 1,
-		.tpdx = 1, .tpdx_05T = 0,
-		.tmrri = 8, .tmrri_05T = 0,
-		.trrd = 2, .trrd_05T = 1,
-		.trrd_4266 = 1, .trrd_4266_05T = 1,
-		.tfaw = 4, .tfaw_05T = 1,
-		.tfaw_4266 = 1, .tfaw_4266_05T = 1,
-		.trtw_odt_off = 4, .trtw_odt_off_05T = 0,
-		.trtw_odt_on = 6, .trtw_odt_on_05T = 0,
-		.txrefcnt = 87,
-		.tzqcs = 26,
-		.xrtw2w_new_mode = 4,
-		.xrtw2w_old_mode = 6,
-		.xrtw2r_odt_on = 1,
-		.xrtw2r_odt_off = 1,
-		.xrtr2w_odt_on = 5,
-		.xrtr2w_odt_off = 5,
-		.xrtr2r_new_mode = 3,
-		.xrtr2r_old_mode = 6,
-		.tr2mrr = 4,
-		.vrcgdis_prdcnt = 31,
-		.hwset_mr2_op = 36,
-		.hwset_mr13_op = 24,
-		.hwset_vrcg_op = 16,
-		.trcd_derate = 6, .trcd_derate_05T = 0,
-		.trc_derate = 10, .trc_derate_05T = 1,
-		.tras_derate = 5, .tras_derate_05T = 0,
-		.trpab_derate = 5, .trpab_derate_05T = 1,
-		.trp_derate = 4, .trp_derate_05T = 1,
-		.trrd_derate = 3, .trrd_derate_05T = 0,
-		.trtpd = 11, .trtpd_05T = 0,
-		.twtpd = 13, .twtpd_05T = 0,
-		.tmrr2w_odt_off = 7,
-		.tmrr2w_odt_on = 9,
-		.ckeprd = 2,
-		.ckelckcnt = 2,
-		.zqlat2 = 10,
-		.dqsinctl = 4, .datlat = 13
-	},
-	{
-		.freq_group = DDRFREQ_933, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
-		.read_lat = 20, .write_lat =  10, .div_mode =  DIV8_MODE,
-		.tras = 1, .tras_05T = 1,
-		.trp = 3, .trp_05T = 0,
-		.trpab = 3, .trpab_05T = 1,
-		.trc = 5, .trc_05T = 0,
-		.trfc = 53, .trfc_05T = 1,
-		.trfcpb = 21, .trfcpb_05T = 0,
-		.txp = 0, .txp_05T = 0,
-		.trtp = 0, .trtp_05T = 1,
-		.trcd = 4, .trcd_05T = 1,
-		.twr = 8, .twr_05T = 1,
-		.twtr = 5, .twtr_05T = 1,
-		.tpbr2pbr = 14, .tpbr2pbr_05T = 0,
-		.tpbr2act = 0, .tpbr2act_05T = 0,
-		.tr2mrw = 10, .tr2mrw_05T = 0,
-		.tw2mrw = 7, .tw2mrw_05T = 0,
-		.tmrr2mrw = 9, .tmrr2mrw_05T = 0,
-		.tmrw = 3, .tmrw_05T = 0,
-		.tmrd = 4, .tmrd_05T = 0,
-		.tmrwckel = 5, .tmrwckel_05T = 0,
-		.tpde = 1, .tpde_05T = 1,
-		.tpdx = 1, .tpdx_05T = 0,
-		.tmrri = 6, .tmrri_05T = 0,
-		.trrd = 1, .trrd_05T = 1,
-		.trrd_4266 = 1, .trrd_4266_05T = 0,
-		.tfaw = 1, .tfaw_05T = 1,
-		.tfaw_4266 = 0, .tfaw_4266_05T = 0,
-		.trtw_odt_off = 3, .trtw_odt_off_05T = 0,
-		.trtw_odt_on = 5, .trtw_odt_on_05T = 0,
-		.txrefcnt = 68,
-		.tzqcs = 19,
-		.xrtw2w_new_mode = 4,
-		.xrtw2w_old_mode = 6,
-		.xrtw2r_odt_on = 2,
-		.xrtw2r_odt_off = 2,
-		.xrtr2w_odt_on = 3,
-		.xrtr2w_odt_off = 3,
-		.xrtr2r_new_mode = 3,
-		.xrtr2r_old_mode = 6,
-		.tr2mrr = 4,
-		.vrcgdis_prdcnt = 24,
-		.hwset_mr2_op = 27,
-		.hwset_mr13_op = 24,
-		.hwset_vrcg_op = 16,
-		.trcd_derate = 5, .trcd_derate_05T = 0,
-		.trc_derate = 6, .trc_derate_05T = 1,
-		.tras_derate = 2, .tras_derate_05T = 0,
-		.trpab_derate = 4, .trpab_derate_05T = 0,
-		.trp_derate = 3, .trp_derate_05T = 1,
-		.trrd_derate = 2, .trrd_derate_05T = 0,
-		.trtpd = 9, .trtpd_05T = 1,
-		.twtpd = 10, .twtpd_05T = 1,
-		.tmrr2w_odt_off = 5,
-		.tmrr2w_odt_on = 7,
-		.ckeprd = 1,
-		.ckelckcnt = 2,
-		.zqlat2 = 7,
-		.dqsinctl = 3, .datlat = 13
-	},
-	{
-		.freq_group = DDRFREQ_933, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
-		.read_lat = 22, .write_lat =  10, .div_mode =  DIV8_MODE,
-		.tras = 1, .tras_05T = 1,
-		.trp = 3, .trp_05T = 0,
-		.trpab = 3, .trpab_05T = 1,
-		.trc = 5, .trc_05T = 0,
-		.trfc = 53, .trfc_05T = 1,
-		.trfcpb = 21, .trfcpb_05T = 0,
-		.txp = 0, .txp_05T = 0,
-		.trtp = 0, .trtp_05T = 1,
-		.trcd = 4, .trcd_05T = 1,
-		.twr = 8, .twr_05T = 0,
-		.twtr = 5, .twtr_05T = 0,
-		.tpbr2pbr = 14, .tpbr2pbr_05T = 0,
-		.tpbr2act = 0, .tpbr2act_05T = 0,
-		.tr2mrw = 10, .tr2mrw_05T = 1,
-		.tw2mrw = 7, .tw2mrw_05T = 0,
-		.tmrr2mrw = 9, .tmrr2mrw_05T = 1,
-		.tmrw = 3, .tmrw_05T = 0,
-		.tmrd = 4, .tmrd_05T = 0,
-		.tmrwckel = 5, .tmrwckel_05T = 0,
-		.tpde = 1, .tpde_05T = 1,
-		.tpdx = 1, .tpdx_05T = 0,
-		.tmrri = 6, .tmrri_05T = 0,
-		.trrd = 1, .trrd_05T = 1,
-		.trrd_4266 = 1, .trrd_4266_05T = 0,
-		.tfaw = 1, .tfaw_05T = 1,
-		.tfaw_4266 = 0, .tfaw_4266_05T = 0,
-		.trtw_odt_off = 3, .trtw_odt_off_05T = 0,
-		.trtw_odt_on = 5, .trtw_odt_on_05T = 0,
-		.txrefcnt = 68,
-		.tzqcs = 19,
-		.xrtw2w_new_mode = 4,
-		.xrtw2w_old_mode = 6,
-		.xrtw2r_odt_on = 2,
-		.xrtw2r_odt_off = 1,
-		.xrtr2w_odt_on = 4,
-		.xrtr2w_odt_off = 4,
-		.xrtr2r_new_mode = 3,
-		.xrtr2r_old_mode = 6,
-		.tr2mrr = 4,
-		.vrcgdis_prdcnt = 24,
-		.hwset_mr2_op = 27,
-		.hwset_mr13_op = 24,
-		.hwset_vrcg_op = 16,
-		.trcd_derate = 5, .trcd_derate_05T = 0,
-		.trc_derate = 6, .trc_derate_05T = 1,
-		.tras_derate = 2, .tras_derate_05T = 0,
-		.trpab_derate = 4, .trpab_derate_05T = 0,
-		.trp_derate = 3, .trp_derate_05T = 1,
-		.trrd_derate = 2, .trrd_derate_05T = 0,
-		.trtpd = 10, .trtpd_05T = 0,
-		.twtpd = 11, .twtpd_05T = 0,
-		.tmrr2w_odt_off = 6,
-		.tmrr2w_odt_on = 8,
-		.ckeprd = 1,
-		.ckelckcnt = 2,
-		.zqlat2 = 7,
-		.dqsinctl = 3, .datlat = 13
-	},
-	{
-		.freq_group = DDRFREQ_800, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
-		.read_lat = 14, .write_lat =  8, .div_mode =  DIV8_MODE,
-		.tras = 0, .tras_05T = 0,
-		.trp = 2, .trp_05T = 1,
-		.trpab = 3, .trpab_05T = 0,
-		.trc = 3, .trc_05T = 0,
-		.trfc = 44, .trfc_05T = 0,
-		.trfcpb = 16, .trfcpb_05T = 0,
-		.txp = 0, .txp_05T = 0,
-		.trtp = 0, .trtp_05T = 1,
-		.trcd = 4, .trcd_05T = 0,
-		.twr = 7, .twr_05T = 1,
-		.twtr = 4, .twtr_05T = 1,
-		.tpbr2pbr = 11, .tpbr2pbr_05T = 0,
-		.tpbr2act = 0, .tpbr2act_05T = 0,
-		.tr2mrw = 8, .tr2mrw_05T = 1,
-		.tw2mrw = 6, .tw2mrw_05T = 1,
-		.tmrr2mrw = 7, .tmrr2mrw_05T = 0,
-		.tmrw = 3, .tmrw_05T = 0,
-		.tmrd = 3, .tmrd_05T = 1,
-		.tmrwckel = 4, .tmrwckel_05T = 1,
-		.tpde = 1, .tpde_05T = 1,
-		.tpdx = 1, .tpdx_05T = 0,
-		.tmrri = 5, .tmrri_05T = 1,
-		.trrd = 1, .trrd_05T = 0,
-		.trrd_4266 = 0, .trrd_4266_05T = 1,
-		.tfaw = 0, .tfaw_05T = 0,
-		.tfaw_4266 = 0, .tfaw_4266_05T = 0,
-		.trtw_odt_off = 1, .trtw_odt_off_05T = 0,
-		.trtw_odt_on = 4, .trtw_odt_on_05T = 0,
-		.txrefcnt = 58,
-		.tzqcs = 16,
-		.xrtw2w_new_mode = 4,
-		.xrtw2w_old_mode = 6,
-		.xrtw2r_odt_on = 3,
-		.xrtw2r_odt_off = 3,
-		.xrtr2w_odt_on = 3,
-		.xrtr2w_odt_off = 3,
-		.xrtr2r_new_mode = 3,
-		.xrtr2r_old_mode = 6,
-		.tr2mrr = 4,
-		.vrcgdis_prdcnt = 20,
-		.hwset_mr2_op = 18,
-		.hwset_mr13_op = 24,
-		.hwset_vrcg_op = 16,
-		.trcd_derate = 4, .trcd_derate_05T = 0,
-		.trc_derate = 4, .trc_derate_05T = 0,
-		.tras_derate = 0, .tras_derate_05T = 1,
-		.trpab_derate = 3, .trpab_derate_05T = 1,
-		.trp_derate = 2, .trp_derate_05T = 1,
-		.trrd_derate = 1, .trrd_derate_05T = 1,
-		.trtpd = 7, .trtpd_05T = 1,
-		.twtpd = 9, .twtpd_05T = 1,
-		.tmrr2w_odt_off = 3,
-		.tmrr2w_odt_on = 5,
-		.ckeprd = 1,
-		.ckelckcnt = 2,
-		.zqlat2 = 6,
-		.dqsinctl = 2, .datlat = 10
-	},
-	{
-		.freq_group = DDRFREQ_800, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
-		.read_lat = 16, .write_lat =  8, .div_mode =  DIV8_MODE,
-		.tras = 0, .tras_05T = 0,
-		.trp = 2, .trp_05T = 1,
-		.trpab = 3, .trpab_05T = 0,
-		.trc = 3, .trc_05T = 0,
-		.trfc = 44, .trfc_05T = 0,
-		.trfcpb = 16, .trfcpb_05T = 0,
-		.txp = 0, .txp_05T = 0,
-		.trtp = 0, .trtp_05T = 1,
-		.trcd = 4, .trcd_05T = 0,
-		.twr = 7, .twr_05T = 0,
-		.twtr = 4, .twtr_05T = 0,
-		.tpbr2pbr = 11, .tpbr2pbr_05T = 0,
-		.tpbr2act = 0, .tpbr2act_05T = 0,
-		.tr2mrw = 9, .tr2mrw_05T = 0,
-		.tw2mrw = 6, .tw2mrw_05T = 1,
-		.tmrr2mrw = 7, .tmrr2mrw_05T = 1,
-		.tmrw = 3, .tmrw_05T = 0,
-		.tmrd = 3, .tmrd_05T = 1,
-		.tmrwckel = 4, .tmrwckel_05T = 1,
-		.tpde = 1, .tpde_05T = 1,
-		.tpdx = 1, .tpdx_05T = 0,
-		.tmrri = 5, .tmrri_05T = 1,
-		.trrd = 1, .trrd_05T = 0,
-		.trrd_4266 = 0, .trrd_4266_05T = 1,
-		.tfaw = 0, .tfaw_05T = 0,
-		.tfaw_4266 = 0, .tfaw_4266_05T = 0,
-		.trtw_odt_off = 2, .trtw_odt_off_05T = 0,
-		.trtw_odt_on = 4, .trtw_odt_on_05T = 0,
-		.txrefcnt = 58,
-		.tzqcs = 16,
-		.xrtw2w_new_mode = 4,
-		.xrtw2w_old_mode = 6,
-		.xrtw2r_odt_on = 3,
-		.xrtw2r_odt_off = 2,
-		.xrtr2w_odt_on = 3,
-		.xrtr2w_odt_off = 3,
-		.xrtr2r_new_mode = 3,
-		.xrtr2r_old_mode = 6,
-		.tr2mrr = 4,
-		.vrcgdis_prdcnt = 20,
-		.hwset_mr2_op = 18,
-		.hwset_mr13_op = 24,
-		.hwset_vrcg_op = 16,
-		.trcd_derate = 4, .trcd_derate_05T = 0,
-		.trc_derate = 4, .trc_derate_05T = 0,
-		.tras_derate = 0, .tras_derate_05T = 1,
-		.trpab_derate = 3, .trpab_derate_05T = 1,
-		.trp_derate = 2, .trp_derate_05T = 1,
-		.trrd_derate = 1, .trrd_derate_05T = 1,
-		.trtpd = 8, .trtpd_05T = 0,
-		.twtpd = 9, .twtpd_05T = 1,
-		.tmrr2w_odt_off = 4,
-		.tmrr2w_odt_on = 6,
-		.ckeprd = 1,
-		.ckelckcnt = 2,
-		.zqlat2 = 6,
-		.dqsinctl = 2, .datlat = 10
-	},
-	{
-		.freq_group = DDRFREQ_600, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
-		.read_lat = 14, .write_lat =  8, .div_mode =  DIV8_MODE,
-		.tras = 0, .tras_05T = 0,
-		.trp = 1, .trp_05T = 1,
-		.trpab = 2, .trpab_05T = 0,
-		.trc = 0, .trc_05T = 1,
-		.trfc = 30, .trfc_05T = 1,
-		.trfcpb = 9, .trfcpb_05T = 1,
-		.txp = 0, .txp_05T = 0,
-		.trtp = 0, .trtp_05T = 1,
-		.trcd = 3, .trcd_05T = 0,
-		.twr = 6, .twr_05T = 1,
-		.twtr = 4, .twtr_05T = 1,
-		.tpbr2pbr = 7, .tpbr2pbr_05T = 0,
-		.tpbr2act = 0, .tpbr2act_05T = 0,
-		.tr2mrw = 8, .tr2mrw_05T = 1,
-		.tw2mrw = 6, .tw2mrw_05T = 1,
-		.tmrr2mrw = 7, .tmrr2mrw_05T = 0,
-		.tmrw = 3, .tmrw_05T = 0,
-		.tmrd = 3, .tmrd_05T = 0,
-		.tmrwckel = 4, .tmrwckel_05T = 0,
-		.tpde = 1, .tpde_05T = 1,
-		.tpdx = 1, .tpdx_05T = 0,
-		.tmrri = 4, .tmrri_05T = 0,
-		.trrd = 1, .trrd_05T = 0,
-		.trrd_4266 = 0, .trrd_4266_05T = 1,
-		.tfaw = 0, .tfaw_05T = 0,
-		.tfaw_4266 = 0, .tfaw_4266_05T = 0,
-		.trtw_odt_off = 1, .trtw_odt_off_05T = 0,
-		.trtw_odt_on = 4, .trtw_odt_on_05T = 0,
-		.txrefcnt = 44,
-		.tzqcs = 12,
-		.xrtw2w_new_mode = 4,
-		.xrtw2w_old_mode = 6,
-		.xrtw2r_odt_on = 3,
-		.xrtw2r_odt_off = 3,
-		.xrtr2w_odt_on = 3,
-		.xrtr2w_odt_off = 3,
-		.xrtr2r_new_mode = 3,
-		.xrtr2r_old_mode = 6,
-		.tr2mrr = 4,
-		.vrcgdis_prdcnt = 16,
-		.hwset_mr2_op = 18,
-		.hwset_mr13_op = 24,
-		.hwset_vrcg_op = 16,
-		.trcd_derate = 3, .trcd_derate_05T = 0,
-		.trc_derate = 1, .trc_derate_05T = 0,
-		.tras_derate = 0, .tras_derate_05T = 0,
-		.trpab_derate = 2, .trpab_derate_05T = 0,
-		.trp_derate = 1, .trp_derate_05T = 1,
-		.trrd_derate = 1, .trrd_derate_05T = 0,
-		.trtpd = 7, .trtpd_05T = 1,
-		.twtpd = 8, .twtpd_05T = 1,
-		.tmrr2w_odt_off = 3,
-		.tmrr2w_odt_on = 5,
-		.ckeprd = 1,
-		.ckelckcnt = 2,
-		.zqlat2 = 5,
-		.dqsinctl = 2, .datlat = 9
-	},
-	{
-		.freq_group = DDRFREQ_600, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
-		.read_lat = 16, .write_lat =  8, .div_mode =  DIV8_MODE,
-		.tras = 0, .tras_05T = 0,
-		.trp = 1, .trp_05T = 1,
-		.trpab = 2, .trpab_05T = 0,
-		.trc = 0, .trc_05T = 1,
-		.trfc = 30, .trfc_05T = 1,
-		.trfcpb = 9, .trfcpb_05T = 1,
-		.txp = 0, .txp_05T = 0,
-		.trtp = 0, .trtp_05T = 1,
-		.trcd = 3, .trcd_05T = 0,
-		.twr = 6, .twr_05T = 0,
-		.twtr = 4, .twtr_05T = 1,
-		.tpbr2pbr = 7, .tpbr2pbr_05T = 0,
-		.tpbr2act = 0, .tpbr2act_05T = 0,
-		.tr2mrw = 9, .tr2mrw_05T = 0,
-		.tw2mrw = 6, .tw2mrw_05T = 1,
-		.tmrr2mrw = 7, .tmrr2mrw_05T = 1,
-		.tmrw = 3, .tmrw_05T = 0,
-		.tmrd = 3, .tmrd_05T = 0,
-		.tmrwckel = 4, .tmrwckel_05T = 0,
-		.tpde = 1, .tpde_05T = 1,
-		.tpdx = 1, .tpdx_05T = 0,
-		.tmrri = 4, .tmrri_05T = 0,
-		.trrd = 1, .trrd_05T = 0,
-		.trrd_4266 = 0, .trrd_4266_05T = 1,
-		.tfaw = 0, .tfaw_05T = 0,
-		.tfaw_4266 = 0, .tfaw_4266_05T = 0,
-		.trtw_odt_off = 2, .trtw_odt_off_05T = 0,
-		.trtw_odt_on = 5, .trtw_odt_on_05T = 0,
-		.txrefcnt = 44,
-		.tzqcs = 12,
-		.xrtw2w_new_mode = 4,
-		.xrtw2w_old_mode = 6,
-		.xrtw2r_odt_on = 3,
-		.xrtw2r_odt_off = 2,
-		.xrtr2w_odt_on = 3,
-		.xrtr2w_odt_off = 3,
-		.xrtr2r_new_mode = 3,
-		.xrtr2r_old_mode = 6,
-		.tr2mrr = 4,
-		.vrcgdis_prdcnt = 16,
-		.hwset_mr2_op = 18,
-		.hwset_mr13_op = 24,
-		.hwset_vrcg_op = 16,
-		.trcd_derate = 3, .trcd_derate_05T = 0,
-		.trc_derate = 1, .trc_derate_05T = 0,
-		.tras_derate = 0, .tras_derate_05T = 0,
-		.trpab_derate = 2, .trpab_derate_05T = 0,
-		.trp_derate = 1, .trp_derate_05T = 1,
-		.trrd_derate = 1, .trrd_derate_05T = 0,
-		.trtpd = 8, .trtpd_05T = 0,
-		.twtpd = 9, .twtpd_05T = 0,
-		.tmrr2w_odt_off = 4,
-		.tmrr2w_odt_on = 6,
-		.ckeprd = 1,
-		.ckelckcnt = 2,
-		.zqlat2 = 5,
-		.dqsinctl = 2, .datlat = 9
-	},
-	{
-		.freq_group = DDRFREQ_400, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
-		.read_lat = 14, .write_lat =  8, .div_mode =  DIV4_MODE,
-		.tras = 1, .tras_05T = 0,
-		.trp = 2, .trp_05T = 0,
-		.trpab = 3, .trpab_05T = 0,
-		.trc = 3, .trc_05T = 0,
-		.trfc = 44, .trfc_05T = 0,
-		.trfcpb = 16, .trfcpb_05T = 0,
-		.txp = 0, .txp_05T = 0,
-		.trtp = 3, .trtp_05T = 0,
-		.trcd = 4, .trcd_05T = 0,
-		.twr = 12, .twr_05T = 0,
-		.twtr = 10, .twtr_05T = 0,
-		.tpbr2pbr = 11, .tpbr2pbr_05T = 0,
-		.tpbr2act = 0, .tpbr2act_05T = 0,
-		.tr2mrw = 16, .tr2mrw_05T = 0,
-		.tw2mrw = 13, .tw2mrw_05T = 0,
-		.tmrr2mrw = 14, .tmrr2mrw_05T = 0,
-		.tmrw = 6, .tmrw_05T = 0,
-		.tmrd = 6, .tmrd_05T = 0,
-		.tmrwckel = 8, .tmrwckel_05T = 0,
-		.tpde = 3, .tpde_05T = 0,
-		.tpdx = 3, .tpdx_05T = 0,
-		.tmrri = 7, .tmrri_05T = 0,
-		.trrd = 1, .trrd_05T = 0,
-		.trrd_4266 = 1, .trrd_4266_05T = 0,
-		.tfaw = 0, .tfaw_05T = 0,
-		.tfaw_4266 = 0, .tfaw_4266_05T = 0,
-		.trtw_odt_off = 6, .trtw_odt_off_05T = 0,
-		.trtw_odt_on = 11, .trtw_odt_on_05T = 0,
-		.txrefcnt = 58,
-		.tzqcs = 16,
-		.xrtw2w_new_mode = 9,
-		.xrtw2w_old_mode = 10,
-		.xrtw2r_odt_on = 7,
-		.xrtw2r_odt_off = 5,
-		.xrtr2w_odt_on = 9,
-		.xrtr2w_odt_off = 9,
-		.xrtr2r_new_mode = 6,
-		.xrtr2r_old_mode = 8,
-		.tr2mrr = 8,
-		.vrcgdis_prdcnt = 20,
-		.hwset_mr2_op = 18,
-		.hwset_mr13_op = 24,
-		.hwset_vrcg_op = 16,
-		.trcd_derate = 4, .trcd_derate_05T = 0,
-		.trc_derate = 4, .trc_derate_05T = 0,
-		.tras_derate = 1, .tras_derate_05T = 0,
-		.trpab_derate = 3, .trpab_derate_05T = 0,
-		.trp_derate = 2, .trp_derate_05T = 0,
-		.trrd_derate = 2, .trrd_derate_05T = 0,
-		.trtpd = 15, .trtpd_05T = 0,
-		.twtpd = 15, .twtpd_05T = 0,
-		.tmrr2w_odt_off = 10,
-		.tmrr2w_odt_on = 12,
-		.ckeprd = 2,
-		.ckelckcnt = 3,
-		.zqlat2 = 6,
-		.dqsinctl = 5, .datlat = 15
-	},
-	{
-		.freq_group = DDRFREQ_400, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
-		.read_lat = 16, .write_lat =  8, .div_mode =  DIV4_MODE,
-		.tras = 1, .tras_05T = 0,
-		.trp = 2, .trp_05T = 0,
-		.trpab = 3, .trpab_05T = 0,
-		.trc = 3, .trc_05T = 0,
-		.trfc = 44, .trfc_05T = 0,
-		.trfcpb = 16, .trfcpb_05T = 0,
-		.txp = 0, .txp_05T = 0,
-		.trtp = 3, .trtp_05T = 0,
-		.trcd = 4, .trcd_05T = 0,
-		.twr = 12, .twr_05T = 0,
-		.twtr = 10, .twtr_05T = 0,
-		.tpbr2pbr = 11, .tpbr2pbr_05T = 0,
-		.tpbr2act = 0, .tpbr2act_05T = 0,
-		.tr2mrw = 17, .tr2mrw_05T = 0,
-		.tw2mrw = 13, .tw2mrw_05T = 0,
-		.tmrr2mrw = 15, .tmrr2mrw_05T = 0,
-		.tmrw = 6, .tmrw_05T = 0,
-		.tmrd = 6, .tmrd_05T = 0,
-		.tmrwckel = 8, .tmrwckel_05T = 0,
-		.tpde = 3, .tpde_05T = 0,
-		.tpdx = 3, .tpdx_05T = 0,
-		.tmrri = 7, .tmrri_05T = 0,
-		.trrd = 1, .trrd_05T = 0,
-		.trrd_4266 = 1, .trrd_4266_05T = 0,
-		.tfaw = 0, .tfaw_05T = 0,
-		.tfaw_4266 = 0, .tfaw_4266_05T = 0,
-		.trtw_odt_off = 7, .trtw_odt_off_05T = 0,
-		.trtw_odt_on = 12, .trtw_odt_on_05T = 0,
-		.txrefcnt = 58,
-		.tzqcs = 16,
-		.xrtw2w_new_mode = 9,
-		.xrtw2w_old_mode = 10,
-		.xrtw2r_odt_on = 6,
-		.xrtw2r_odt_off = 4,
-		.xrtr2w_odt_on = 10,
-		.xrtr2w_odt_off = 10,
-		.xrtr2r_new_mode = 6,
-		.xrtr2r_old_mode = 9,
-		.tr2mrr = 8,
-		.vrcgdis_prdcnt = 20,
-		.hwset_mr2_op = 18,
-		.hwset_mr13_op = 24,
-		.hwset_vrcg_op = 16,
-		.trcd_derate = 4, .trcd_derate_05T = 0,
-		.trc_derate = 4, .trc_derate_05T = 0,
-		.tras_derate = 1, .tras_derate_05T = 0,
-		.trpab_derate = 3, .trpab_derate_05T = 0,
-		.trp_derate = 2, .trp_derate_05T = 0,
-		.trrd_derate = 2, .trrd_derate_05T = 0,
-		.trtpd = 16, .trtpd_05T = 0,
-		.twtpd = 15, .twtpd_05T = 0,
-		.tmrr2w_odt_off = 11,
-		.tmrr2w_odt_on = 13,
-		.ckeprd = 2,
-		.ckelckcnt = 3,
-		.zqlat2 = 6,
-		.dqsinctl = 5, .datlat = 15
-	},
-};
-
-#endif  /* __SOC_MEDIATEK_MT8192_DRAMC_AC_TIMING_H__ */
diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_common_mt8192.h b/src/soc/mediatek/mt8192/include/soc/dramc_common_mt8192.h
deleted file mode 100644
index b5c7889803..0000000000
--- a/src/soc/mediatek/mt8192/include/soc/dramc_common_mt8192.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __SOC_MEDIATEK_MT8192_DRAMC_COMMON_MT8192_H__
-#define __SOC_MEDIATEK_MT8192_DRAMC_COMMON_MT8192_H__
-
-enum {
-	FSP_0 = 0,
-	FSP_1,
-	FSP_MAX,
-};
-
-typedef enum {
-	DRAM_DFS_SHU0 = 0,
-	DRAM_DFS_SHU1,
-	DRAM_DFS_SHU2,
-	DRAM_DFS_SHU3,
-	DRAM_DFS_SHU4,
-	DRAM_DFS_SHU5,
-	DRAM_DFS_SHU6,
-	DRAM_DFS_SHU_MAX
-} dram_dfs_shu;
-
-typedef enum {
-	ODT_OFF = 0,
-	ODT_ON,
-	ODT_MAX
-} dram_odt_state;
-
-typedef enum {
-	DBI_OFF = 0,
-	DBI_ON
-} dbi_mode;
-
-enum {
-	CKE_FIXOFF = 0,
-	CKE_FIXON,
-	CKE_DYNAMIC
-};
-
-enum {
-	CA_NUM_LP4 = 6,
-	DQ_DATA_WIDTH = 16,
-	DQS_BIT_NUMBER = 8,
-	DQS_NUMBER = (DQ_DATA_WIDTH / DQS_BIT_NUMBER),
-};
-#define BYTE_NUM		DQS_NUMBER
-
-/* DONOT change the sequence of pinmux */
-typedef enum {
-	PINMUX_DSC = 0,
-	PINMUX_LPBK,
-	PINMUX_EMCP,
-	PINMUX_MAX
-} dram_pinmux_type;
-
-enum {
-	CBT_R0_R1_NORMAL = 0,
-	CBT_R0_R1_BYTE,
-	CBT_R0_NORMAL_R1_BYTE,
-	CBT_R0_BYTE_R1_NORMAL
-};
-
-#endif	/* __SOC_MEDIATEK_MT8192_DRAMC_COMMON_MT8192_H__ */
diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h
deleted file mode 100644
index 2dee0445c3..0000000000
--- a/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h
+++ /dev/null
@@ -1,352 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __SOC_MEDIATEK_MT8192_DRAMC_PI_API_H__
-#define __SOC_MEDIATEK_MT8192_DRAMC_PI_API_H__
-
-#include <console/console.h>
-#include <delay.h>
-#include <device/mmio.h>
-#include <stdint.h>
-#include <types.h>
-
-#include <soc/addressmap.h>
-#include <soc/dramc_common_mt8192.h>
-#include <soc/dramc_register_bits_def.h>
-#include <soc/emi.h>
-
-#define dramc_err(_x_...) printk(BIOS_ERR, _x_)
-#define dramc_info(_x_...) printk(BIOS_INFO, _x_)
-#if CONFIG(DEBUG_DRAM)
-#define dramc_dbg(_x_...) printk(BIOS_INFO, _x_)
-#else
-#define dramc_dbg(_x_...)
-#endif
-
-#define DRAMC_BROADCAST_ON	0x7f
-#define DRAMC_BROADCAST_OFF	0x0
-
-#define TX_DQ_UI_TO_PI_TAP		64
-#define TX_PHASE_DQ_UI_TO_PI_TAP	32
-#define LP4_TX_VREF_DATA_NUM		50
-#define LP4_TX_VREF_PASS_CONDITION	0
-#define TX_PASS_WIN_CRITERIA		7
-#define LP4_TX_VREF_BOUNDARY_NOT_READY 0xff
-#define REG_SHU_OFFSET_WIDTH		0x700
-#define SHU_OFFSET			(REG_SHU_OFFSET_WIDTH / 4)
-
-#define DQS_LEVEL_UNKNOWN		0xff
-
-typedef enum {
-	DDRFREQ_400,
-	DDRFREQ_600,
-	DDRFREQ_800,
-	DDRFREQ_933,
-	DDRFREQ_1200,
-	DDRFREQ_1600,
-	DDRFREQ_2133,
-	DDRFREQ_MAX,
-} dram_freq_grp;
-
-typedef enum {
-	CALI_SEQ0 = 0,
-	CALI_SEQ1,
-	CALI_SEQ2,
-	CALI_SEQ3,
-	CALI_SEQ4,
-	CALI_SEQ5,
-	CALI_SEQ6,
-	CALI_SEQ_MAX
-} dram_cali_seq;
-
-typedef enum {
-	DIV8_MODE = 0,
-	DIV4_MODE,
-	UNKNOWN_MODE,
-} dram_div_mode;
-
-typedef enum {
-	VREF_CALI_OFF = 0,
-	VREF_CALI_ON,
-} vref_cali_mode;
-
-typedef enum {
-	DRVP = 0,
-	DRVN,
-	ODTP,
-	ODTN,
-	IMP_DRV_MAX
-} imp_drv_type;
-
-typedef enum {
-	RX_WIN_RD_DQC = 0,
-	RX_WIN_TEST_ENG,
-} rx_cali_type;
-
-typedef enum TX_CAL_TYPE {
-	TX_DQ_DQS_MOVE_DQ_ONLY,
-	TX_DQ_DQS_MOVE_DQM_ONLY,
-	TX_DQ_DQS_MOVE_DQ_DQM,
-} tx_cali_type;
-
-typedef enum {
-	DCM_OFF = 0,
-	DCM_ON,
-} dcm_state;
-
-typedef enum {
-	CBT_LOW_FREQ = 0,
-	CBT_HIGH_FREQ,
-	CBT_UNKNOWN_FREQ = 0xff,
-} cbt_freq;
-
-typedef enum {
-	IN_CBT,
-	OUT_CBT,
-} cbt_state;
-
-enum {
-	PHYPLL_MODE = 0,
-	CLRPLL_MODE,
-};
-
-enum {
-	DUTYSCAN_K_DQ,
-	DUTYSCAN_K_DQM,
-};
-
-typedef enum {
-	O1_OFF,
-	O1_ON,
-} o1_state;
-
-typedef enum {
-	SINGLE_RANK_DDR = 1,
-	DUAL_RANK_DDR
-} ddr_rank_num;
-
-enum {
-	DQS_8PH_DEGREE_0 = 0,
-	DQS_8PH_DEGREE_180,
-	DQS_8PH_DEGREE_45,
-
-	DQS_8PH_DEGREE_MAX,
-};
-
-struct dram_impedance {
-	u32 result[ODT_MAX][IMP_DRV_MAX];
-};
-
-struct mr_values {
-	u8 mr01[FSP_MAX];
-	u8 mr02[FSP_MAX];
-	u8 mr03[FSP_MAX];
-	u8 mr04[RANK_MAX];
-	u8 mr11[FSP_MAX];
-	u8 mr12[CHANNEL_MAX][RANK_MAX][FSP_MAX];
-	u8 mr13[RANK_MAX];
-	u8 mr14[CHANNEL_MAX][RANK_MAX][FSP_MAX];
-	u8 mr18[CHANNEL_MAX][RANK_MAX];
-	u8 mr19[CHANNEL_MAX][RANK_MAX];
-	u8 mr20[FSP_MAX];
-	u8 mr21[FSP_MAX];
-	u8 mr22[FSP_MAX];
-	u8 mr23[CHANNEL_MAX][RANK_MAX];
-	u8 mr26[RANK_MAX];
-	u8 mr30[RANK_MAX];
-	u8 mr51[FSP_MAX];
-};
-
-struct ddr_cali {
-	u8 chn;
-	u8 rank;
-	/*
-	 * frequency set point:
-	 *	0 means lower,un-terminated freq;
-	 *	1 means higher,terminated freq
-	 */
-	u8 fsp;
-	u8 density;
-	u8 *pll_mode;
-	u32 frequency;
-	u32 vcore_voltage;
-	dram_dfs_shu shu;
-	ddr_rank_num support_ranks;
-	dbi_mode w_dbi[FSP_MAX];
-	vref_cali_mode vref_cali;
-	dram_odt_state odt_onoff;
-	dram_freq_grp freq_group;
-	dram_div_mode div_mode;
-	dram_pinmux_type pinmux_type;
-	dram_cbt_mode cbt_mode[RANK_MAX];
-	struct dram_impedance impedance;
-	struct mr_values *mr_value;
-	const struct emi_mdl *emi_config;
-	const struct sdram_params *params;
-};
-
-struct reg_bak {
-	u32 *addr;
-	u32 value;
-};
-
-typedef struct _ana_top_config {
-	u8 dll_async_en;
-	u8 all_slave_en;
-	u8 rank_mode;
-	u8 dll_idle_mode;
-	u8 aphy_comb_en;
-	u8 tx_odt_dis;
-	u8 new_8x_mode;
-} ana_top_config;
-
-typedef struct ana_dvfs_core_config {
-	u8 ckr;
-	u8 dq_p2s_ratio;
-	u8 ca_p2s_ratio;
-	u8 dq_ca_open;
-	u8 dq_semi_open;
-	u8 ca_semi_open;
-	u8 ca_full_rate;
-	u8 dq_ckdiv4_en;
-	u8 ca_ckdiv4_en;
-	u8 ca_prediv_en;
-	u8 ph8_dly;
-	u8 semi_open_ca_pick_mck_ratio;
-	u8 dq_aamck_div;
-	u8 ca_admck_div;
-	u8 dq_track_ca_en;
-	u32 pll_freq;
-} ana_dvfs_core;
-
-typedef struct lp4_dram_config {
-	u8 ex_row_en[RANK_MAX];
-	u8 mr_wl;
-	u8 dbi_wr;
-	u8 dbi_rd;
-	u8 lp4y_en;
-	u8 work_fsp;
-} dram_config;
-
-typedef struct _dvfs_group_config {
-	u32 data_rate;
-	u8 dqsien_mode;
-	u8 dq_p2s_ratio;
-	u8 ckr;
-} dvfs_group_config;
-
-struct gating_config {
-	u8 gat_track_en;
-	u8 rx_gating_mode;
-	u8 rx_gating_track_mode;
-	u8 valid_lat_value;
-};
-
-typedef struct _dramc_subsys_config {
-	dram_freq_grp freq_group;
-	ana_top_config *a_cfg;
-	ana_dvfs_core *dvfs_core;
-	dram_config *lp4_init;
-	dvfs_group_config *dfs_gp;
-	struct gating_config *gat_c;
-} dramc_subsys_config;
-
-typedef struct _reg_transfer {
-	u32 *addr;
-	u8 offset;
-} reg_transfer;
-
-void emi_init2(void);
-u32 get_column_num(void);
-u32 get_row_width_from_emi(u32 rank);
-u8 dramc_mode_reg_read(u8 chn, u8 mr_idx);
-u8 dramc_mode_reg_read_by_rank(u8 chn, u8 rank, u8 mr_idx);
-void dramc_mode_reg_write_by_rank(const struct ddr_cali *cali,
-	u8 chn, u8 rank, u8 mr_idx, u8 value);
-void after_calib(const struct ddr_cali *cali);
-void init_dram(const struct dramc_data *dparam);
-void global_option_init(struct ddr_cali *cali);
-u32 dramc_get_broadcast(void);
-void dramc_set_broadcast(u32 onoff);
-void dramc_sw_impedance_cal(dram_odt_state odt, struct dram_impedance *imp);
-void dramc_sw_impedance_save_register(const struct ddr_cali *cali);
-void dfs_init_for_calibration(const struct ddr_cali *cali);
-void dramc_auto_refresh_switch(u8 chn, bool flag);
-void dramc_runtime_config(const struct ddr_cali *cali);
-void emi_mdl_init(const struct emi_mdl *emi_con);
-void cke_fix_onoff(const struct ddr_cali *cali, u8 chn, u8 rank, int option);
-void enable_phy_dcm_shuffle(dcm_state enable, u8 shuffle_save);
-void enable_phy_dcm_non_shuffle(dcm_state enable);
-void dramc_8_phase_cal(const struct ddr_cali *cali);
-void dramc_duty_calibration(const struct sdram_params *params);
-void dramc_write_leveling(const struct ddr_cali *cali,
-			  u8 dqs_final_delay[RANK_MAX][DQS_NUMBER]);
-void dramc_rx_dqs_gating_cal(const struct ddr_cali *cali, u8 *txdly_min, u8 *txdly_max);
-void dramc_rx_dqs_gating_post_process(const struct ddr_cali *cali,
-	u8 txdly_min, u8 txdly_max);
-void dramc_rx_datlat_cal(const struct ddr_cali *cali);
-void dramc_dual_rank_rx_datlat_cal(const struct ddr_cali *cali);
-void dramc_cmd_bus_training(const struct ddr_cali *cali);
-void dramc_rx_window_perbit_cal(const struct ddr_cali *cali, rx_cali_type type);
-void dramc_tx_window_perbit_cal(const struct ddr_cali *cali, tx_cali_type cal_type,
-	const u8 dqs_final_delay[RANK_MAX][DQS_NUMBER], bool vref_scan_enable);
-void dramc_tx_oe_calibration(const struct ddr_cali *cali);
-dram_freq_grp get_freq_group(const struct ddr_cali *cali);
-dram_odt_state get_odt_state(const struct ddr_cali *cali);
-u8 get_fsp(const struct ddr_cali *cali);
-dram_dfs_shu get_shu(const struct ddr_cali *cali);
-dram_freq_grp get_highest_freq_group(void);
-dram_cbt_mode get_cbt_mode(const struct ddr_cali *cali);
-u32 get_frequency(const struct ddr_cali *cali);
-vref_cali_mode get_vref_cali(const struct ddr_cali *cali);
-dram_div_mode get_div_mode(const struct ddr_cali *cali);
-dbi_mode get_write_dbi(const struct ddr_cali *cali);
-dram_dfs_shu get_shu_save_by_k_shu(dram_cali_seq k_seq);
-dram_freq_grp get_freq_group_by_shu_save(dram_dfs_shu shu);
-dram_pinmux_type get_pinmux_type(const struct ddr_cali *cali);
-u32 get_frequency_by_shu(dram_dfs_shu shu);
-u32 get_vcore_value(const struct ddr_cali *cali);
-void set_cali_datas(struct ddr_cali *cali,
-	const struct dramc_data *dparam, dram_cali_seq k_seq);
-u8 get_mck2ui_div_shift(const struct ddr_cali *cali);
-void tx_picg_setting(const struct ddr_cali *cali);
-void xrtrtr_shu_setting(const struct ddr_cali *cali);
-void cbt_switch_freq(const struct ddr_cali *cali, cbt_freq freq);
-void enable_dfs_hw_mode_clk(void);
-void dramc_dfs_direct_jump_rg_mode(const struct ddr_cali *cali, u8 shu_level);
-void dramc_dfs_direct_jump_sram_shu_rg_mode(const struct ddr_cali *cali,
-	dram_dfs_shu shu_level);
-void dramc_save_result_to_shuffle(dram_dfs_shu src, dram_dfs_shu dst);
-void dramc_load_shuffle_to_dramc(dram_dfs_shu src, dram_dfs_shu dst);
-void dvfs_settings(const struct ddr_cali *cali);
-void dramc_dqs_precalculation_preset(const struct ddr_cali *cali);
-void freq_jump_ratio_calculation(const struct ddr_cali *cali);
-void dramc_hmr4_presetting(const struct ddr_cali *cali);
-void dramc_enable_perbank_refresh(bool en);
-void dramc_modified_refresh_mode(void);
-void dramc_cke_debounce(const struct ddr_cali *cali);
-void dramc_hw_dqsosc(const struct ddr_cali *cali, u8 chn);
-void xrtwtw_shu_setting(const struct ddr_cali *cali);
-void enable_write_DBI_after_calibration(const struct ddr_cali *cali);
-void dramc_set_mr13_vrcg_to_normal(const struct ddr_cali *cali);
-void ana_init(const struct ddr_cali *cali, dramc_subsys_config *subsys);
-void dig_static_setting(const struct ddr_cali *cali, dramc_subsys_config *subsys);
-void dig_config_shuf(const struct ddr_cali *cali, dramc_subsys_config *subsys);
-void resetb_pull_dn(void);
-void dramc_subsys_pre_config(dram_freq_grp freq_group, dramc_subsys_config *subsys);
-void single_end_dramc_post_config(u8 lp4y_en);
-void dram_configure(dram_freq_grp freq_group, dram_config *tr);
-void ana_clk_div_config(ana_dvfs_core *tr, dvfs_group_config *dfs);
-void apply_write_dbi_power_improve(bool onoff);
-void dramc_write_dbi_onoff(u8 onoff);
-void cbt_delay_ca_clk(u8 chn, u8 rank, s32 iDelay);
-void dramc_cmd_ui_delay_setting(u8 chn, u8 value);
-void dramc_dqsosc_set_mr18_mr19(const struct ddr_cali *cali,
-	u16 *osc_thrd_inc, u16 *osc_thrd_dec);
-void dqsosc_shu_settings(const struct ddr_cali *cali,
-	u16 *osc_thrd_inc, u16 *osc_thrd_dec);
-void shift_dq_ui(const struct ddr_cali *cali, u8 rk, s8 shift_ui);
-void shuffle_dfs_to_fsp1(const struct ddr_cali *cali);
-u8 get_cbt_vref_pinmux_value(const struct ddr_cali *cali, u8 range, u8 vref_lev);
-void o1_path_on_off(const struct ddr_cali *cali, o1_state o1);
-
-#endif /* __SOC_MEDIATEK_MT8192_DRAMC_PI_API_H__ */
diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_register.h b/src/soc/mediatek/mt8192/include/soc/dramc_register.h
deleted file mode 100644
index f7b62646e3..0000000000
--- a/src/soc/mediatek/mt8192/include/soc/dramc_register.h
+++ /dev/null
@@ -1,1818 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __SOC_MEDIATEK_MT8192_DRAMC_REGISTER_H__
-#define __SOC_MEDIATEK_MT8192_DRAMC_REGISTER_H__
-
-#include <soc/addressmap.h>
-#include <soc/dpm.h>
-#include <stdint.h>
-
-struct dramc_nao_regs {
-	u32 testmode;
-	u32 rsvd_0[4];
-	u32 rdqc_cmp;
-	u32 rdqc_dqm_cmp;
-	u32 rsvd_1[2];
-	u32 dmmonitor;
-	u32 rsvd_2[2];
-	u32 initk_pat0;
-	u32 initk_pat1;
-	u32 initk_pat2;
-	u32 initk_pat3;
-	u32 initk_pat4;
-	u32 rsvd_3[3];
-	u32 spcmdresp3;
-	u32 cbt_wlev_status2;
-	u32 rsvd_4[10];
-	u32 misc_statusa;
-	u32 special_status;
-	u32 spcmdresp;
-	u32 mrr_status;
-	u32 mrr_status2;
-	u32 mrrdata0;
-	u32 mrrdata1;
-	u32 mrrdata2;
-	u32 mrrdata3;
-	u32 ref_status;
-	u32 rsvd_5[2];
-	u32 wck_status;
-	u32 rsvd_6[3];
-	u32 tcmdo1lat;
-	u32 cbt_wlev_status1;
-	u32 cbt_wlev_status;
-	u32 spcmdresp2;
-	u32 cbt_wlev_atk_result0;
-	u32 cbt_wlev_atk_result1;
-	u32 cbt_wlev_atk_result2;
-	u32 cbt_wlev_atk_result3;
-	u32 cbt_wlev_atk_result4;
-	u32 cbt_wlev_atk_result5;
-	u32 cbt_wlev_atk_result6;
-	u32 cbt_wlev_atk_result7;
-	u32 cbt_wlev_atk_result8;
-	u32 cbt_wlev_atk_result9;
-	u32 cbt_wlev_atk_result10;
-	u32 cbt_wlev_atk_result11;
-	u32 cbt_wlev_atk_result12;
-	u32 cbt_wlev_atk_result13;
-	u32 rsvd_7[1];
-	u32 hwmrr_push2pop_cnt;
-	u32 hwmrr_status;
-	u32 hw_refrate_mon;
-	u32 hw_refrate_mon2;
-	u32 hw_refrate_mon3;
-	u32 testrpt;
-	u32 cmp_err;
-	u32 test_abit_status1;
-	u32 test_abit_status2;
-	u32 test_abit_status3;
-	u32 test_abit_status4;
-	u32 test_abit_status5;
-	u32 test_abit_status6;
-	u32 test_abit_status7;
-	u32 test_abit_status8;
-	u32 test_rf_error_flag0;
-	u32 test_rf_error_flag1;
-	u32 test_rf_error_cnt1;
-	u32 test_rf_error_cnt2;
-	u32 test_rf_error_cnt3;
-	u32 test_rf_error_cnt4;
-	u32 test_rf_error_cnt5;
-	u32 test_rf_error_cnt6;
-	u32 test_rf_error_cnt7;
-	u32 test_rf_error_cnt8;
-	u32 test_loop_cnt;
-	u32 rsvd_8[3];
-	u32 sref_dly_cnt;
-	u32 rsvd_9[31];
-	u32 tx_atk_set0;
-	u32 tx_atk_set1;
-	u32 rsvd_10[2];
-	u32 tx_atk_result0;
-	u32 tx_atk_result1;
-	u32 tx_atk_result2;
-	u32 tx_atk_result3;
-	u32 tx_atk_result4;
-	u32 tx_atk_result5;
-	u32 tx_atk_result6;
-	u32 tx_atk_result7;
-	u32 tx_atk_result8;
-	u32 rsvd_11[3];
-	u32 tx_atk_dbg_bit_status1;
-	u32 tx_atk_dbg_bit_status2;
-	u32 tx_atk_dbg_bit_status3;
-	u32 tx_atk_dbg_bit_status4;
-	u32 rsvd_12[34];
-	u32 lp5_pdx_pde_mon;
-	u32 lp5_pdx_pde_max_mon;
-	u32 dram_clk_en_0_old_counter;
-	u32 aphypi_cg_ck_old_counter;
-	u32 ckeo_pre_old_counter;
-	u32 cke1o_pre_old_counter;
-	u32 dram_clk_en_0_new_counter;
-	u32 aphypi_cg_ck_new_counter;
-	u32 ckeo_pre_new_counter;
-	u32 cke1o_pre_new_counter;
-	u32 refresh_pop_counter;
-	u32 freerun_26m_counter;
-	u32 dramc_idle_counter;
-	u32 r2r_page_hit_counter;
-	u32 r2r_page_miss_counter;
-	u32 r2r_interbank_counter;
-	u32 r2w_page_hit_counter;
-	u32 r2w_page_miss_counter;
-	u32 r2w_interbank_counter;
-	u32 w2r_page_hit_counter;
-	u32 w2r_page_miss_counter;
-	u32 w2r_interbank_counter;
-	u32 w2w_page_hit_counter;
-	u32 w2w_page_miss_counter;
-	u32 w2w_interbank_counter;
-	u32 rk0_pre_standby_counter;
-	u32 rk0_pre_powerdown_counter;
-	u32 rk0_act_standby_counter;
-	u32 rk0_act_powerdown_counter;
-	u32 rk1_pre_standby_counter;
-	u32 rk1_pre_powerdown_counter;
-	u32 rk1_act_standby_counter;
-	u32 rk1_act_powerdown_counter;
-	u32 rk2_pre_standby_counter;
-	u32 rk2_pre_powerdown_counter;
-	u32 rk2_act_standby_counter;
-	u32 rk2_act_powerdown_counter;
-	u32 dq0_toggle_counter;
-	u32 dq1_toggle_counter;
-	u32 dq2_toggle_counter;
-	u32 dq3_toggle_counter;
-	u32 dq0_toggle_counter_r;
-	u32 dq1_toggle_counter_r;
-	u32 dq2_toggle_counter_r;
-	u32 dq3_toggle_counter_r;
-	u32 read_bytes_counter;
-	u32 write_bytes_counter;
-	u32 max_sref_req_to_ack_latency_counter;
-	u32 rsvd_13[2];
-	u32 dramc_idle_dcm_counter;
-	u32 ddrphy_clk_en_counter;
-	u32 ddrphy_clk_en_comb_counter;
-	u32 rsvd_14[1];
-	u32 ebg_counter_cnt0;
-	u32 ebg_counter_cnt1;
-	u32 ebg_counter_cnt2;
-	u32 rsvd_15[1];
-	u32 lat_counter_cmd0;
-	u32 lat_counter_cmd1;
-	u32 lat_counter_cmd2;
-	u32 lat_counter_cmd3;
-	u32 lat_counter_cmd4;
-	u32 lat_counter_cmd5;
-	u32 lat_counter_cmd6;
-	u32 lat_counter_cmd7;
-	u32 lat_counter_aver;
-	u32 lat_counter_num;
-	u32 lat_counter_block_ale;
-	u32 rsvd_16[70];
-	u32 dramc_loop_bak_adr;
-	u32 dramc_loop_bak_rk;
-	u32 rsvd_17[1];
-	u32 dramc_loop_bak_wdat0;
-	u32 dramc_loop_bak_wdat1;
-	u32 dramc_loop_bak_wdat2;
-	u32 dramc_loop_bak_wdat3;
-	u32 dramc_loop_bak_wdat4;
-	u32 dramc_loop_bak_wdat5;
-	u32 dramc_loop_bak_wdat6;
-	u32 dramc_loop_bak_wdat7;
-	u32 rsvd_18[52];
-	u32 rk0_dqsosc_status;
-	u32 rk0_dqsosc_delta;
-	u32 rk0_dqsosc_delta2;
-	u32 rsvd_19[1];
-	u32 rk0_current_tx_setting1;
-	u32 rk0_current_tx_setting2;
-	u32 rk0_current_tx_setting3;
-	u32 rk0_current_tx_setting4;
-	u32 rk0_dummy_rd_data0;
-	u32 rk0_dummy_rd_data1;
-	u32 rk0_dummy_rd_data2;
-	u32 rk0_dummy_rd_data3;
-	u32 rk0_dummy_rd_data4;
-	u32 rk0_dummy_rd_data5;
-	u32 rk0_dummy_rd_data6;
-	u32 rk0_dummy_rd_data7;
-	u32 rsvd_20[8];
-	u32 rk0_pi_dq_cal;
-	u32 rsvd_21[1];
-	u32 rk0_pi_dqm_cal;
-	u32 rsvd_22[37];
-	u32 rk1_dqsosc_status;
-	u32 rk1_dqsosc_delta;
-	u32 rk1_dqsosc_delta2;
-	u32 rsvd_23[1];
-	u32 rk1_current_tx_setting1;
-	u32 rk1_current_tx_setting2;
-	u32 rk1_current_tx_setting3;
-	u32 rk1_current_tx_setting4;
-	u32 rk1_dummy_rd_data0;
-	u32 rk1_dummy_rd_data1;
-	u32 rk1_dummy_rd_data2;
-	u32 rk1_dummy_rd_data3;
-	u32 rk1_dummy_rd_data4;
-	u32 rk1_dummy_rd_data5;
-	u32 rk1_dummy_rd_data6;
-	u32 rk1_dummy_rd_data7;
-	u32 rsvd_24[8];
-	u32 rk1_pi_dq_cal;
-	u32 rsvd_25[1];
-	u32 rk1_pi_dqm_cal;
-	u32 rsvd_26[101];
-	u32 mr_backup_00_rk0_fsp0;
-	u32 mr_backup_01_rk0_fsp0;
-	u32 mr_backup_02_rk0_fsp0;
-	u32 mr_backup_03_rk0_fsp0;
-	u32 mr_backup_04_rk0_fsp0;
-	u32 mr_backup_05_rk0_fsp0;
-	u32 mr_backup_06_rk0_fsp0;
-	u32 mr_backup_07_rk0_fsp0;
-	u32 mr_backup_08_rk0_fsp0;
-	u32 mr_backup_09_rk0_fsp0;
-	u32 rsvd_27[2];
-	u32 mr_backup_00_rk0_fsp1;
-	u32 mr_backup_01_rk0_fsp1;
-	u32 mr_backup_02_rk0_fsp1;
-	u32 mr_backup_03_rk0_fsp1;
-	u32 mr_backup_04_rk0_fsp1;
-	u32 rsvd_28[7];
-	u32 mr_backup_00_rk0_fsp2;
-	u32 mr_backup_01_rk0_fsp2;
-	u32 mr_backup_02_rk0_fsp2;
-	u32 mr_backup_03_rk0_fsp2;
-	u32 rsvd_29[100];
-	u32 mr_backup_00_rk1_fsp0;
-	u32 mr_backup_01_rk1_fsp0;
-	u32 mr_backup_02_rk1_fsp0;
-	u32 mr_backup_03_rk1_fsp0;
-	u32 mr_backup_04_rk1_fsp0;
-	u32 mr_backup_05_rk1_fsp0;
-	u32 mr_backup_06_rk1_fsp0;
-	u32 mr_backup_07_rk1_fsp0;
-	u32 mr_backup_08_rk1_fsp0;
-	u32 mr_backup_09_rk1_fsp0;
-	u32 rsvd_30[2];
-	u32 mr_backup_00_rk1_fsp1;
-	u32 mr_backup_01_rk1_fsp1;
-	u32 mr_backup_02_rk1_fsp1;
-	u32 mr_backup_03_rk1_fsp1;
-	u32 mr_backup_04_rk1_fsp1;
-	u32 rsvd_31[7];
-	u32 mr_backup_00_rk1_fsp2;
-	u32 mr_backup_01_rk1_fsp2;
-	u32 mr_backup_02_rk1_fsp2;
-	u32 mr_backup_03_rk1_fsp2;
-};
-
-struct ddrphy_nao_regs {
-	u32 misc_sta_extlb0;
-	u32 misc_sta_extlb1;
-	u32 misc_sta_extlb2;
-	u32 rsvd_0[1];
-	u32 misc_dma_debug0;
-	u32 misc_dma_debug1;
-	u32 misc_retry_dbg0;
-	u32 misc_retry_dbg1;
-	u32 misc_retry_dbg2;
-	u32 misc_rdsel_track_dbg;
-	u32 rsvd_1[22];
-	u32 misc_dq_rxdly_trro0;
-	u32 misc_dq_rxdly_trro1;
-	u32 misc_dq_rxdly_trro2;
-	u32 misc_dq_rxdly_trro3;
-	u32 misc_dq_rxdly_trro4;
-	u32 misc_dq_rxdly_trro5;
-	u32 misc_dq_rxdly_trro6;
-	u32 misc_dq_rxdly_trro7;
-	u32 misc_dq_rxdly_trro8;
-	u32 misc_dq_rxdly_trro9;
-	u32 misc_dq_rxdly_trro10;
-	u32 misc_dq_rxdly_trro11;
-	u32 misc_dq_rxdly_trro12;
-	u32 misc_dq_rxdly_trro13;
-	u32 misc_dq_rxdly_trro14;
-	u32 misc_dq_rxdly_trro15;
-	u32 misc_dq_rxdly_trro16;
-	u32 misc_dq_rxdly_trro17;
-	u32 misc_dq_rxdly_trro18;
-	u32 misc_dq_rxdly_trro19;
-	u32 misc_dq_rxdly_trro20;
-	u32 misc_dq_rxdly_trro21;
-	u32 misc_dq_rxdly_trro22;
-	u32 misc_dq_rxdly_trro23;
-	u32 misc_dq_rxdly_trro24;
-	u32 misc_dq_rxdly_trro25;
-	u32 misc_dq_rxdly_trro26;
-	u32 misc_dq_rxdly_trro27;
-	u32 misc_dq_rxdly_trro28;
-	u32 misc_dq_rxdly_trro29;
-	u32 misc_dq_rxdly_trro30;
-	u32 misc_dq_rxdly_trro31;
-	u32 rsvd_2[20];
-	u32 misc_ca_rxdly_trro20;
-	u32 misc_ca_rxdly_trro21;
-	u32 misc_ca_rxdly_trro22;
-	u32 misc_ca_rxdly_trro23;
-	u32 misc_ca_rxdly_trro24;
-	u32 misc_ca_rxdly_trro25;
-	u32 misc_ca_rxdly_trro26;
-	u32 misc_ca_rxdly_trro27;
-	u32 misc_ca_rxdly_trro28;
-	u32 misc_ca_rxdly_trro29;
-	u32 misc_ca_rxdly_trro30;
-	u32 misc_ca_rxdly_trro31;
-	u32 misc_dqo1;
-	u32 misc_cao1;
-	u32 misc_ad_rx_dq_o1;
-	u32 misc_ad_rx_cmd_o1;
-	u32 misc_phy_rgs_dq;
-	u32 misc_phy_rgs_cmd;
-	u32 misc_phy_rgs_stben_b0;
-	u32 misc_phy_rgs_stben_b1;
-	u32 misc_phy_rgs_stben_cmd;
-	u32 misc_phy_picg_mon_s0;
-	u32 misc_phy_picg_mon_s1;
-	u32 misc_phy_picg_mon_s2;
-	u32 misc_phy_picg_mon_s3;
-	u32 misc_phy_picg_mon_s4;
-	u32 misc_phy_picg_mon_s5;
-	u32 misc_phy_picg_mon_s6;
-	u32 misc_phy_picg_mon_s7;
-	u32 misc_phy_picg_mon_s8;
-	u32 misc_mbist_status;
-	u32 misc_mbist_status2;
-	u32 misc_impcal_status1;
-	u32 misc_impcal_status2;
-	u32 misc_impcal_status3;
-	u32 misc_impcal_status4;
-	u32 misc_impcal_status5;
-	u32 misc_impcal_status6;
-	u32 misc_impcal_status7;
-	u32 misc_impcal_status8;
-	u32 rsvd_3[1];
-	u32 misc_impcal_status9;
-	u32 misc_sta_toglb0;
-	u32 misc_sta_toglb1;
-	u32 rsvd_4[5];
-	u32 misc_sta_extlb_dbg0;
-	u32 misc_sta_extlb_dbg1;
-	u32 misc_sta_extlb_dbg2;
-	u32 misc_sta_extlb_dbg3;
-	u32 misc_duty_toggle_cnt;
-	u32 misc_duty_dqs0_err_cnt;
-	u32 misc_duty_dq_err_cnt0;
-	u32 misc_duty_dqs1_err_cnt;
-	u32 misc_duty_dq_err_cnt1;
-	u32 misc_duty_dqs2_err_cnt;
-	u32 misc_duty_dq_err_cnt2;
-	u32 misc_duty_dqs3_err_cnt;
-	u32 misc_duty_dq_err_cnt3;
-	u32 misc_jmeter_st0;
-	u32 misc_jmeter_st1;
-	u32 misc_emi_lpbk0;
-	u32 misc_emi_lpbk1;
-	u32 misc_emi_lpbk2;
-	u32 misc_emi_lpbk3;
-	u32 misc_emi_lpbk4;
-	u32 misc_emi_lpbk5;
-	u32 misc_emi_lpbk6;
-	u32 misc_emi_lpbk7;
-	u32 misc_ft_status0;
-	u32 misc_ft_status1;
-	u32 misc_ft_status2;
-	u32 misc_ft_status3;
-	u32 misc_ft_status4;
-	u32 misc_sta_toglb2;
-	u32 misc_sta_toglb3;
-	u32 misc_sta_extlb3;
-	u32 misc_sta_extlb4;
-	u32 misc_sta_extlb5;
-	u32 rsvd_5[90];
-	u32 debug_aphy_rx_ctl;
-	u32 rsvd_6[3];
-	u32 gating_err_infor;
-	u32 debug_dqsien_b0;
-	u32 debug_dqsien_b1;
-	u32 debug_dqsien_ca;
-	u32 gating_err_latch_dly_b0_rk0;
-	u32 gating_err_latch_dly_b1_rk0;
-	u32 gating_err_latch_dly_ca_rk0;
-	u32 rsvd_7[1];
-	u32 gating_err_latch_dly_b0_rk1;
-	u32 gating_err_latch_dly_b1_rk1;
-	u32 gating_err_latch_dly_ca_rk1;
-	u32 rsvd_8[1];
-	u32 debug_rodt_ctl;
-	u32 rsvd_9[47];
-	u32 cal_dqsg_cnt_b0;
-	u32 cal_dqsg_cnt_b1;
-	u32 cal_dqsg_cnt_ca;
-	u32 dvfs_status;
-	u32 rx_autok_status0;
-	u32 rx_autok_status1;
-	u32 rx_autok_status2;
-	u32 rx_autok_status3;
-	u32 rx_autok_status4;
-	u32 rx_autok_status5;
-	u32 rx_autok_status6;
-	u32 rx_autok_status7;
-	u32 rx_autok_status8;
-	u32 rx_autok_status9;
-	u32 rx_autok_status10;
-	u32 rx_autok_status11;
-	u32 rx_autok_status12;
-	u32 rx_autok_status13;
-	u32 rx_autok_status14;
-	u32 rx_autok_status15;
-	u32 rx_autok_status16;
-	u32 rx_autok_status17;
-	u32 rx_autok_status18;
-	u32 rx_autok_status19;
-	u32 rx_autok_status20;
-	u32 rsvd_10[39];
-	u32 dqsien_autok_b0_rk0_status0;
-	u32 dqsien_autok_b0_rk0_status1;
-	u32 dqsien_autok_b0_rk0_dbg_status0;
-	u32 dqsien_autok_b0_rk0_dbg_status1;
-	u32 dqsien_autok_b0_rk0_dbg_status2;
-	u32 dqsien_autok_b0_rk0_dbg_status3;
-	u32 dqsien_autok_b0_rk0_dbg_status4;
-	u32 dqsien_autok_b0_rk0_dbg_status5;
-	u32 dqsien_autok_b0_rk1_status0;
-	u32 dqsien_autok_b0_rk1_status1;
-	u32 dqsien_autok_b0_rk1_dbg_status0;
-	u32 dqsien_autok_b0_rk1_dbg_status1;
-	u32 dqsien_autok_b0_rk1_dbg_status2;
-	u32 dqsien_autok_b0_rk1_dbg_status3;
-	u32 dqsien_autok_b0_rk1_dbg_status4;
-	u32 dqsien_autok_b0_rk1_dbg_status5;
-	u32 dqsien_autok_b1_rk0_status0;
-	u32 dqsien_autok_b1_rk0_status1;
-	u32 dqsien_autok_b1_rk0_dbg_status0;
-	u32 dqsien_autok_b1_rk0_dbg_status1;
-	u32 dqsien_autok_b1_rk0_dbg_status2;
-	u32 dqsien_autok_b1_rk0_dbg_status3;
-	u32 dqsien_autok_b1_rk0_dbg_status4;
-	u32 dqsien_autok_b1_rk0_dbg_status5;
-	u32 dqsien_autok_b1_rk1_status0;
-	u32 dqsien_autok_b1_rk1_status1;
-	u32 dqsien_autok_b1_rk1_dbg_status0;
-	u32 dqsien_autok_b1_rk1_dbg_status1;
-	u32 dqsien_autok_b1_rk1_dbg_status2;
-	u32 dqsien_autok_b1_rk1_dbg_status3;
-	u32 dqsien_autok_b1_rk1_dbg_status4;
-	u32 dqsien_autok_b1_rk1_dbg_status5;
-	u32 dqsien_autok_ca_rk0_status0;
-	u32 dqsien_autok_ca_rk0_status1;
-	u32 dqsien_autok_ca_rk0_dbg_status0;
-	u32 dqsien_autok_ca_rk0_dbg_status1;
-	u32 dqsien_autok_ca_rk0_dbg_status2;
-	u32 dqsien_autok_ca_rk0_dbg_status3;
-	u32 dqsien_autok_ca_rk0_dbg_status4;
-	u32 dqsien_autok_ca_rk0_dbg_status5;
-	u32 rsvd_11[24];
-	u32 dqsien_autok_ca_rk1_status0;
-	u32 dqsien_autok_ca_rk1_status1;
-	u32 dqsien_autok_ca_rk1_dbg_status0;
-	u32 dqsien_autok_ca_rk1_dbg_status1;
-	u32 dqsien_autok_ca_rk1_dbg_status2;
-	u32 dqsien_autok_ca_rk1_dbg_status3;
-	u32 dqsien_autok_ca_rk1_dbg_status4;
-	u32 dqsien_autok_ca_rk1_dbg_status5;
-	u32 dqsien_autok_ctrl_status;
-	u32 ad_dline_mon;
-	u32 dline_mon_track_dbg;
-	u32 misc_dutycal_status;
-	u32 misc_dbg_db_imp_message0;
-	u32 misc_dbg_db_imp_message1;
-	u32 misc_dbg_db_imp_message2;
-	u32 misc_dbg_db_imp_message3;
-	u32 misc_dbg_db_imp_message4;
-	u32 misc_dbg_db_imp_message5;
-	u32 misc_dbg_db_imp_message6;
-	u32 misc_dbg_db_imp_message7;
-	u32 misc_dbg_db_imp_message8;
-	u32 misc_dbg_db_imp_message9;
-	u32 misc_dbg_db_imp_message10;
-	u32 misc_dbg_db_imp_message11;
-	u32 rsvd_12[40];
-	u32 misc_dma_sram_mbist;
-	u32 rsvd_13[7];
-	u32 misc_aphy_obs0;
-	u32 misc_aphy_obs1;
-	u32 misc_aphy_obs2;
-	u32 misc_aphy_obs3;
-	u32 misc_aphy_obs4;
-	u32 misc_aphy_obs5;
-	u32 misc_aphy_obs6;
-	u32 misc_aphy_obs7;
-	u32 misc_aphy_obs8;
-};
-
-struct dramc_ao_rk {
-	u32 rk_test2_a1;
-	u32 rk_dummy_rd_wdata0;
-	u32 rk_dummy_rd_wdata1;
-	u32 rk_dummy_rd_wdata2;
-	u32 rk_dummy_rd_wdata3;
-	u32 rk_dummy_rd_adr;
-	u32 rsvd_0[15];
-	u32 rk_dummy_rd_adr2;
-	u32 rsvd_1[4];
-	u32 rk_sref_dpd_tck_rk_ctrl;
-	u32 rsvd_2[9];
-	u32 rk_dqsosc;
-	u32 rsvd_3[91];
-};
-
-struct dramc_ao_shu_rk {
-	u32 shurk_selph_dq0;
-	u32 shurk_selph_dq1;
-	u32 shurk_selph_dq2;
-	u32 shurk_selph_dq3;
-	u32 shurk_dqs2dq_cal1;
-	u32 shurk_dqs2dq_cal2;
-	u32 shurk_dqs2dq_cal3;
-	u32 shurk_dqs2dq_cal4;
-	u32 shurk_dqs2dq_cal5;
-	u32 shurk_pi;
-	u32 shurk_dqsosc;
-	u32 shurk_dqsosc_thrd;
-	u32 shurk_aphy_tx_picg_ctrl;
-	u32 rsvd_25[3];
-	u32 shurk_wck_wr_mck;
-	u32 shurk_wck_rd_mck;
-	u32 shurk_wck_fs_mck;
-	u32 shurk_wck_wr_ui;
-	u32 shurk_wck_rd_ui;
-	u32 shurk_wck_fs_ui;
-	u32 rsvd_26[2];
-	u32 shurk_cke_ctrl;
-	u32 rsvd_27[103];
-};
-
-struct dramc_ao_regs {
-	u32 ddrcommon0;
-	u32 rsvd_0[2];
-	u32 sa_reserve;
-	u32 rsvd_1[59];
-	u32 nonshu_rsv;
-	u32 test2_a0;
-	u32 test2_a2;
-	u32 test2_a3;
-	u32 test2_a4;
-	u32 dummy_rd;
-	u32 dummy_rd_intv;
-	u32 bus_mon1;
-	u32 dramc_dbg_sel1;
-	u32 dramc_dbg_sel2;
-	u32 swcmd_en;
-	u32 swcmd_ctrl0;
-	u32 swcmd_ctrl1;
-	u32 swcmd_ctrl2;
-	u32 rddqcgolden1;
-	u32 rddqcgolden;
-	u32 rtmrw_ctrl0;
-	u32 rtmrw_ctrl1;
-	u32 rtmrw_ctrl2;
-	u32 rtmrw_ctrl3;
-	u32 cbt_wlev_ctrl0;
-	u32 cbt_wlev_ctrl1;
-	u32 cbt_wlev_ctrl2;
-	u32 cbt_wlev_ctrl3;
-	u32 cbt_wlev_ctrl4;
-	u32 cbt_wlev_atk_ctrl0;
-	u32 cbt_wlev_atk_ctrl1;
-	u32 sref_dpd_ctrl;
-	u32 cfc_ctrl;
-	u32 dllfrz_ctrl;
-	u32 mpc_ctrl;
-	u32 hw_mrr_fun;
-	u32 scheduler_com;
-	u32 rsvd_2[4];
-	u32 actiming_ctrl;
-	u32 rsvd_3[3];
-	u32 zq_set0;
-	u32 zq_set1;
-	u32 rsvd_4[2];
-	u32 tx_tracking_set0;
-	u32 rsvd_5[3];
-	u32 tx_retry_set0;
-	u32 rsvd_6[1];
-	u32 mpc_option;
-	u32 rsvd_7[1];
-	u32 mrr_bit_mux1;
-	u32 mrr_bit_mux2;
-	u32 mrr_bit_mux3;
-	u32 mrr_bit_mux4;
-	u32 rsvd_8[6];
-	u32 shuctrl;
-	u32 dramc_pd_ctrl;
-	u32 dcm_ctrl0;
-	u32 ckectrl;
-	u32 dvfs_ctrl0;
-	u32 shuctrl1;
-	u32 dvfs_timing_ctrl1;
-	u32 shuctrl3;
-	u32 dvfs_timing_ctrl3;
-	u32 cmd_dec_ctrl0;
-	u32 hmr4;
-	u32 bypass_fspop;
-	u32 rkcfg;
-	u32 slp4_testmode;
-	u32 dq_mux_set0;
-	u32 dbiwr_protect;
-	u32 tx_set0;
-	u32 tx_cg_set0;
-	u32 rx_set0;
-	u32 rx_cg_set0;
-	u32 dqsoscr;
-	u32 dramctrl;
-	u32 misctl0;
-	u32 perfctl0;
-	u32 arbctl;
-	u32 datascr;
-	u32 clkar;
-	u32 refctrl0;
-	u32 refctrl1;
-	u32 ref_bounce1;
-	u32 ref_bounce2;
-	u32 rsvd_9[1];
-	u32 refpend1;
-	u32 refpend2;
-	u32 refque_cnt;
-	u32 scsmctrl;
-	u32 scsmctrl_cg;
-	u32 refctrl2;
-	u32 tx_freq_ratio_old_mode0;
-	u32 tx_freq_ratio_old_mode1;
-	u32 tx_freq_ratio_old_mode2;
-	u32 wdt_rst;
-	u32 seda_loop_bak_err_pat_b01;
-	u32 seda_loop_bak_err_pat_b23;
-	u32 seda_loop_bak_err_pat_b45;
-	u32 seda_loop_bak_err_pat_b67;
-	u32 seda_loop_bak_set;
-	u32 rsvd_10[3];
-	u32 dbg_cmddec_cmdsel0;
-	u32 dbg_cmddec_cmdsel1;
-	u32 dbg_cmddec_cmdsel2;
-	u32 dbg_cmddec_cmdsel3;
-	u32 dbg_cmddec_cmdsel4;
-	u32 rtswcmd_cnt;
-	u32 refctrl3;
-	u32 rsvd_11[1];
-	u32 dramc_irq_en;
-	u32 dramc_irq_clear;
-	u32 irq_rsv1;
-	u32 irq_rsv2;
-	u32 refcnt_fr_clk1;
-	u32 refcnt_fr_clk2;
-	u32 refcnt_fr_clk3;
-	u32 refcnt_fr_clk4;
-	u32 refcnt_fr_clk5;
-	u32 refcnt_fr_clk6;
-	u32 refcnt_fr_clk7;
-	u32 rsvd_12[1];
-	u32 dcm_sub_ctrl;
-	u32 rsvd_13[3];
-	u32 cbt_wlev_ctrl5;
-	u32 rsvd_14[3];
-	u32 dram_clk_ctrl;
-	u32 rsvd_15[115];
-	struct dramc_ao_rk rk[RANK_MAX];
-	u32 rsvd_19[256];
-	u32 wdt_dbg_signal;
-	u32 rsvd_20[1];
-	u32 selfref_hwsave_flag;
-	u32 rsvd_21[125];
-	u32 dramc_irq_status1;
-	u32 dramc_irq_status2;
-	u32 rsvd_22[2];
-	u32 dramc_irq_info1;
-	u32 dramc_irq_info1a;
-	u32 rsvd_23[2];
-	u32 dramc_irq_info2;
-	u32 dramc_irq_info3;
-	u32 dramc_irq_info4;
-	u32 dramc_irq_info5;
-	u32 rsvd_24[180];
-	struct dramc_ao_shu_rk shu_rk[RANK_MAX];
-	u32 shu_matype;
-	u32 shu_common0;
-	u32 shu_sref_ctrl;
-	u32 shu_scheduler;
-	u32 shu_dcm_ctrl0;
-	u32 shu_hmr4_dvfs_ctrl0;
-	u32 shu_selph_ca1;
-	u32 shu_selph_ca2;
-	u32 shu_selph_ca3;
-	u32 shu_selph_ca4;
-	u32 shu_selph_ca5;
-	u32 shu_selph_ca6;
-	u32 shu_selph_ca7;
-	u32 shu_selph_ca8;
-	u32 shu_hwset_mr2;
-	u32 shu_hwset_mr13;
-	u32 shu_hwset_vrcg;
-	u32 shu_actim0;
-	u32 shu_actim1;
-	u32 shu_actim2;
-	u32 shu_actim3;
-	u32 shu_actim4;
-	u32 shu_actim5;
-	u32 shu_actim6;
-	u32 shu_actim_xrt;
-	u32 shu_ac_time_05t;
-	u32 shu_ac_derating0;
-	u32 shu_ac_derating1;
-	u32 shu_ac_derating_05t;
-	u32 shu_actiming_conf;
-	u32 shu_ckectrl;
-	u32 shu_selph_dqs0;
-	u32 shu_selph_dqs1;
-	u32 shu_wodt;
-	u32 shu_tx_set0;
-	u32 shu_rx_cg_set0;
-	u32 shu_dqsosc_set0;
-	u32 shu_dqsoscr;
-	u32 shu_tx_rankctl;
-	u32 shu_zq_set0;
-	u32 shu_conf0;
-	u32 shu_misc;
-	u32 shu_new_xrw2w_ctrl;
-	u32 shu_aphy_tx_picg_ctrl;
-	u32 shu_freq_ratio_set0;
-	u32 shu_freq_ratio_set1;
-	u32 shu_freq_ratio_set2;
-	u32 shureg_rsv;
-	u32 shu_wckctrl;
-	u32 shu_wckctrl_1;
-	u32 rsvd_28[2];
-	u32 shu_rx_set0;
-	u32 shu_ref0;
-	u32 rsvd_29[2];
-	u32 shu_lp5_cmd;
-	u32 shu_lp5_sact;
-	u32 shu_actim7;
-};
-
-struct emi_regs {
-	u32 cona;
-	u32 conp;
-	u32 conb;
-	u32 conq;
-	u32 conc;
-	u32 conr;
-	u32 cond;
-	u32 conp_2nd;
-	u32 cone;
-	u32 conq_2nd;
-	u32 conf;
-	u32 conr_2nd;
-	u32 cong;
-	u32 conb_3rd;
-	u32 conh;
-	u32 conh_2nd;
-	u32 coni;
-	u32 conb_4th;
-	u32 conj;
-	u32 conb_5th;
-	u32 conk;
-	u32 conb_6th;
-	u32 rsvd_0[1];
-	u32 conb_7th;
-	u32 conm;
-	u32 conb_8th;
-	u32 conn;
-	u32 conc_3rd;
-	u32 cono;
-	u32 conc_4th;
-	u32 mdct;
-	u32 mdct_2nd;
-	u32 rsvd_1[1];
-	u32 conc_5th;
-	u32 rsvd_2[1];
-	u32 conc_6th;
-	u32 rsvd_3[1];
-	u32 conc_7th;
-	u32 rsvd_4[1];
-	u32 conc_8th;
-	u32 rsvd_5[9];
-	u32 cong_3rd;
-	u32 cong_4th;
-	u32 cong_5th;
-	u32 iocl;
-	u32 iocl_2nd;
-	u32 iocm;
-	u32 iocm_2nd;
-	u32 rsvd_6[1];
-	u32 cong_6th;
-	u32 testb;
-	u32 rsvd_7[1];
-	u32 testc;
-	u32 cong_7th;
-	u32 testd;
-	u32 rsvd_8[1];
-	u32 arba;
-	u32 rsvd_9[1];
-	u32 arbb;
-	u32 rsvd_10[1];
-	u32 arbc;
-	u32 rsvd_11[1];
-	u32 arbd;
-	u32 rsvd_12[1];
-	u32 arbe;
-	u32 rsvd_13[1];
-	u32 arbf;
-	u32 cong_8th;
-	u32 arbg;
-	u32 rsvd_14[1];
-	u32 arbh;
-	u32 conp_3rd;
-	u32 arbi;
-	u32 arbi_2nd;
-	u32 rsvd_15[1];
-	u32 arbj_2nd;
-	u32 arbk;
-	u32 arbk_2nd;
-	u32 slct;
-	u32 rsvd_16[1];
-	u32 mpud0_st;
-	u32 mpud1_st;
-	u32 mpud2_st;
-	u32 mpud3_st;
-	u32 mpud4_st;
-	u32 mpud5_st;
-	u32 mpud6_st;
-	u32 mpud7_st;
-	u32 mpud8_st;
-	u32 mpud9_st;
-	u32 mpud10_st;
-	u32 mpud11_st;
-	u32 mpud12_st;
-	u32 mpud13_st;
-	u32 mpud14_st;
-	u32 mpud15_st;
-	u32 mpud16_st;
-	u32 mpud17_st;
-	u32 mpud18_st;
-	u32 mpud19_st;
-	u32 mpud20_st;
-	u32 mpud21_st;
-	u32 mpud22_st;
-	u32 mpud23_st;
-	u32 mpud24_st;
-	u32 mpud25_st;
-	u32 mpud26_st;
-	u32 mpud27_st;
-	u32 mpud28_st;
-	u32 mpud29_st;
-	u32 mpud30_st;
-	u32 mpud31_st;
-	u32 conp_4th;
-	u32 conp_5th;
-	u32 conp_6th;
-	u32 rsvd_17[1];
-	u32 mpus;
-	u32 conp_8th;
-	u32 mput;
-	u32 mput_2nd;
-	u32 d0_st2;
-	u32 d1_st2;
-	u32 d2_st2;
-	u32 d3_st2;
-	u32 d4_st2;
-	u32 d5_st2;
-	u32 d6_st2;
-	u32 d7_st2;
-	u32 d8_st2;
-	u32 d9_st2;
-	u32 d10_st2;
-	u32 d11_st2;
-	u32 d12_st2;
-	u32 d13_st2;
-	u32 d14_st2;
-	u32 d15_st2;
-	u32 d16_st2;
-	u32 d17_st2;
-	u32 d18_st2;
-	u32 d19_st2;
-	u32 d20_st2;
-	u32 d21_st2;
-	u32 d22_st2;
-	u32 d23_st2;
-	u32 d24_st2;
-	u32 d25_st2;
-	u32 d26_st2;
-	u32 d27_st2;
-	u32 d28_st2;
-	u32 d29_st2;
-	u32 d30_st2;
-	u32 d31_st2;
-	u32 rsvd_18[33];
-	u32 prtcl_m0_cyc;
-	u32 rsvd_19[1];
-	u32 prtcl_m0_ctl;
-	u32 rsvd_20[1];
-	u32 prtcl_m0_msk;
-	u32 rsvd_21[13];
-	u32 prtcl_m1_cyc;
-	u32 rsvd_22[1];
-	u32 prtcl_m1_ctl;
-	u32 rsvd_23[1];
-	u32 prtcl_m1_msk;
-	u32 rsvd_24[13];
-	u32 prtcl_m2_cyc;
-	u32 rsvd_25[1];
-	u32 prtcl_m2_ctl;
-	u32 rsvd_26[1];
-	u32 prtcl_m2_msk;
-	u32 rsvd_27[12];
-	u32 prtcl_m3_cyc;
-	u32 prtcl_m3_ctl;
-	u32 prtcl_m3_msk;
-	u32 rsvd_28[6];
-	u32 prtcl_m4_cyc;
-	u32 bmen;
-	u32 bstp;
-	u32 bcnt;
-	u32 prtcl_m4_ctl;
-	u32 tact;
-	u32 prtcl_m4_msk;
-	u32 tsct;
-	u32 rsvd_29[1];
-	u32 wact;
-	u32 rsvd_30[1];
-	u32 wsct;
-	u32 rsvd_31[1];
-	u32 bact;
-	u32 rsvd_32[1];
-	u32 bsct;
-	u32 rsvd_33[1];
-	u32 msel;
-	u32 rsvd_34[1];
-	u32 tsct2;
-	u32 prtcl_m5_cyc;
-	u32 tsct3;
-	u32 prtcl_m5_ctl;
-	u32 wsct2;
-	u32 prtcl_m5_msk;
-	u32 wsct3;
-	u32 wsct4;
-	u32 msel2;
-	u32 rsvd_35[1];
-	u32 msel3;
-	u32 rsvd_36[1];
-	u32 msel4;
-	u32 rsvd_37[1];
-	u32 msel5;
-	u32 rsvd_38[1];
-	u32 msel6;
-	u32 rsvd_39[1];
-	u32 msel7;
-	u32 rsvd_40[1];
-	u32 msel8;
-	u32 prtcl_m6_cyc;
-	u32 msel9;
-	u32 prtcl_m6_ctl;
-	u32 msel10;
-	u32 prtcl_m6_msk;
-	u32 bmid0;
-	u32 bmid1;
-	u32 bmid2;
-	u32 bmid3;
-	u32 bmid4;
-	u32 bmid5;
-	u32 bmid6;
-	u32 bmid7;
-	u32 bmid8;
-	u32 bmid9;
-	u32 bmid10;
-	u32 rsvd_41[1];
-	u32 bmen1;
-	u32 rsvd_42[1];
-	u32 bmen2;
-	u32 rsvd_43[3];
-	u32 bmrw0;
-	u32 bmrw1;
-	u32 ttype1;
-	u32 rsvd_44[1];
-	u32 ttype2;
-	u32 prtcl_m7_cyc;
-	u32 ttype3;
-	u32 prtcl_m7_ctl;
-	u32 ttype4;
-	u32 prtcl_m7_msk;
-	u32 ttype5;
-	u32 rsvd_45[1];
-	u32 ttype6;
-	u32 rsvd_46[1];
-	u32 ttype7;
-	u32 rsvd_47[1];
-	u32 ttype8;
-	u32 rsvd_48[1];
-	u32 ttype9;
-	u32 rsvd_49[1];
-	u32 ttype10;
-	u32 rsvd_50[1];
-	u32 ttype11;
-	u32 rsvd_51[1];
-	u32 ttype12;
-	u32 rsvd_52[1];
-	u32 ttype13;
-	u32 rsvd_53[1];
-	u32 ttype14;
-	u32 rsvd_54[1];
-	u32 ttype15;
-	u32 rsvd_55[1];
-	u32 ttype16;
-	u32 rsvd_56[1];
-	u32 ttype17;
-	u32 rsvd_57[1];
-	u32 ttype18;
-	u32 rsvd_58[1];
-	u32 ttype19;
-	u32 rsvd_59[1];
-	u32 ttype20;
-	u32 rsvd_60[1];
-	u32 ttype21;
-	u32 rsvd_61[3];
-	u32 bwct0;
-	u32 bwct1;
-	u32 bwct2;
-	u32 bwct3;
-	u32 bwct4;
-	u32 bwst0;
-	u32 bwst1;
-	u32 rsvd_62[1];
-	u32 ex_con;
-	u32 ex_st0;
-	u32 ex_st1;
-	u32 ex_st2;
-	u32 wp_adr;
-	u32 wp_adr_2nd;
-	u32 wp_ctrl;
-	u32 rsvd_63[1];
-	u32 chker;
-	u32 chker_type;
-	u32 chker_adr;
-	u32 chker_adr_2nd;
-	u32 rsvd_64[7];
-	u32 thro_slv_con0;
-	u32 rsvd_65[1];
-	u32 thro_slv_con1;
-	u32 mxto0;
-	u32 mxto1;
-	u32 rsvd_66[4];
-	u32 conq_3rd;
-	u32 conq_4th;
-	u32 conq_5th;
-	u32 conq_6th;
-	u32 rsvd_67[4];
-	u32 conq_7th;
-	u32 conq_8th;
-	u32 conr_3rd;
-	u32 conr_4th;
-	u32 rsvd_68[9];
-	u32 conr_5th;
-	u32 rsvd_69[2];
-	u32 bwct0_2nd;
-	u32 rsvd_70[25];
-	u32 conr_6th;
-	u32 conr_7th;
-	u32 shf0;
-	u32 dvfs_shf_con;
-	u32 shf1;
-	u32 clua;
-	u32 rsvd_71[10];
-	u32 conr_8th;
-	u32 rsvd_72[1];
-	u32 ltct0_2nd;
-	u32 ltct1_2nd;
-	u32 ltct2_2nd;
-	u32 ltct3_2nd;
-	u32 rsvd_73[4];
-	u32 bwct0_3rd;
-	u32 bwlmte_8th;
-	u32 rsvd_74[1];
-	u32 bwlmtf_8th;
-	u32 bwct0_4th;
-	u32 bwlmtg_8th;
-	u32 rsvd_75[1];
-	u32 bwlmth_8th;
-	u32 rsvd_76[5];
-	u32 chn_hash0;
-	u32 rsvd_77[2];
-	u32 bwct0_5th;
-	u32 rsvd_78[5];
-	u32 bwct0_6th;
-	u32 rsvd_79[11];
-	u32 snst;
-	u32 rsvd_80[1];
-	u32 slva;
-	u32 rsvd_81[7];
-	u32 thro_os0;
-	u32 thro_os1;
-	u32 thro_os2;
-	u32 thro_os3;
-	u32 thro_ctrl0;
-	u32 thro_prd0;
-	u32 thro_prd1;
-	u32 thro_lat0;
-	u32 thro_lat1;
-	u32 thro_lat2;
-	u32 thro_lat3;
-	u32 thro_lat4;
-	u32 thro_lat5;
-	u32 thro_lat6;
-	u32 thro_ctrl1;
-	u32 thro_prd2;
-	u32 rsvd_82[5];
-	u32 thro_lat7;
-	u32 thro_lat8;
-	u32 thro_prd3;
-	u32 rsvd_83[4];
-	u32 bwlmta;
-	u32 bwlmtb;
-	u32 rsvd_84[2];
-	u32 bwlmte;
-	u32 bwlmtf;
-	u32 rsvd_85[2];
-	u32 conb_2nd;
-	u32 conc_2nd;
-	u32 cong_2nd;
-	u32 rsvd_86[1];
-	u32 thro_lat9;
-	u32 thro_lat10;
-	u32 thro_lat11;
-	u32 thro_lat12;
-	u32 thro_lat13;
-	u32 thro_lat14;
-	u32 rsvd_87[2];
-	u32 bwlmte_2nd;
-	u32 bwlmtf_2nd;
-	u32 bwlmtg_2nd;
-	u32 rsvd_88[13];
-	u32 bwlmte_4th;
-	u32 bwlmtf_4th;
-	u32 rsvd_89[2];
-	u32 bwlmte_5th;
-	u32 bwlmtf_5th;
-	u32 bwlmtg_5th;
-	u32 rsvd_90[7];
-	u32 bwlmtg_7th;
-	u32 rsvd_91[12];
-	u32 axi_bist_adr0;
-	u32 axi_bist_adr1;
-	u32 axi_bist_adr2;
-	u32 rsvd_92[22];
-	u32 thro_lat27;
-	u32 thro_lat28;
-	u32 thro_lat29;
-	u32 thro_lat30;
-	u32 rsvd_93[64];
-	u32 thro_lat31;
-	u32 thro_lat32;
-	u32 thro_lat33;
-	u32 thro_lat34;
-	u32 thro_lat35;
-	u32 thro_lat36;
-	u32 rsvd_94[4];
-	u32 thro_lat41;
-	u32 thro_lat42;
-	u32 rsvd_95[12];
-	u32 thro_lat55;
-	u32 thro_lat56;
-	u32 rsvd_96[12];
-	u32 thro_lat69;
-	u32 thro_lat70;
-	u32 rsvd_97[12];
-	u32 thro_lat83;
-	u32 thro_lat84;
-	u32 rsvd_98[12];
-	u32 thro_lat97;
-	u32 thro_lat98;
-	u32 rsvd_99[12];
-	u32 thro_lat111;
-	u32 thro_lat112;
-	u32 rsvd_100[1];
-	u32 thro_prd5;
-	u32 rsvd_101[12];
-	u32 thro_lat113;
-	u32 thro_lat114;
-	u32 thro_lat115;
-	u32 thro_lat116;
-	u32 thro_lat117;
-	u32 thro_lat118;
-	u32 thro_lat119;
-	u32 thro_lat120;
-	u32 rsvd_102[4];
-	u32 thro_lat125;
-	u32 thro_lat126;
-	u32 rsvd_103[16];
-	u32 thro_lat139;
-	u32 thro_lat140;
-	u32 rsvd_104[1];
-	u32 qos_mdr_be0a;
-	u32 rsvd_105[1];
-	u32 qos_mdr_be1a;
-	u32 rsvd_106[1];
-	u32 qos_mdr_shf0;
-	u32 qos_mdr_shf1;
-	u32 qos_mdw_be0a;
-	u32 rsvd_107[1];
-	u32 qos_mdw_be1a;
-	u32 rsvd_108[1];
-	u32 qos_mdw_shf0;
-	u32 qos_mdw_shf1;
-	u32 qos_apr_be0a;
-	u32 rsvd_109[1];
-	u32 qos_apr_be1a;
-	u32 rsvd_110[1];
-	u32 qos_apr_shf0;
-	u32 qos_apw_be0a;
-	u32 rsvd_111[1];
-	u32 qos_apw_be1a;
-	u32 rsvd_112[1];
-	u32 qos_mmr_be0a;
-	u32 rsvd_113[1];
-	u32 qos_mmr_be1a;
-	u32 qos_mmr_be1b;
-	u32 qos_mmr_be2a;
-	u32 qos_mmr_be2b;
-	u32 qos_mmr_shf0;
-	u32 qos_mmr_shf1;
-	u32 qos_mmw_be0a;
-	u32 rsvd_114[1];
-	u32 qos_mmw_be1a;
-	u32 qos_mmw_be1b;
-	u32 qos_mmw_be2a;
-	u32 qos_mmw_be2b;
-	u32 qos_mmw_shf0;
-	u32 qos_mmw_shf1;
-	u32 qos_mdhwr_be0a;
-	u32 rsvd_115[1];
-	u32 qos_mdhwr_be1a;
-	u32 rsvd_116[1];
-	u32 qos_mdhwr_shf0;
-	u32 qos_mdhww_be0a;
-	u32 rsvd_117[1];
-	u32 qos_mdhww_be1a;
-	u32 rsvd_118[1];
-	u32 qos_gpur_be0a;
-	u32 rsvd_119[1];
-	u32 qos_gpur_be1a;
-	u32 rsvd_120[1];
-	u32 qos_gpur_shf0;
-	u32 qos_gpuw_be0a;
-	u32 rsvd_121[1];
-	u32 qos_gpuw_be1a;
-	u32 rsvd_122[1];
-	u32 qos_arbr_be0a;
-	u32 rsvd_123[1];
-	u32 qos_arbr_be1a;
-	u32 rsvd_124[1];
-	u32 qos_arbr_shf0;
-	u32 qos_ctrl1;
-	u32 rsvd_125[3];
-	u32 ext_lt_con1_1st;
-	u32 ext_lt_con2_1st;
-	u32 ext_lt_con3_1st;
-	u32 rsvd_126[1];
-	u32 ext_lt_con1_2nd;
-	u32 ext_lt_con2_2nd;
-	u32 ext_lt_con3_2nd;
-	u32 rsvd_127[1];
-	u32 ext_lt_con1_3rd;
-	u32 ext_lt_con2_3rd;
-	u32 ext_lt_con3_3rd;
-	u32 rsvd_128[1];
-	u32 ext_lt_con1_4th;
-	u32 ext_lt_con2_4th;
-	u32 ext_lt_con3_4th;
-};
-
-struct phy_ao_rk {
-	u32 shu_r0_b0_txdly0;
-	u32 shu_r0_b0_txdly1;
-	u32 shu_r0_b0_txdly2;
-	u32 shu_r0_b0_txdly3;
-	u32 shu_r0_b0_txdly4;
-	u32 shu_r0_b0_rxdly0;
-	u32 shu_r0_b0_rxdly1;
-	u32 shu_r0_b0_rxdly2;
-	u32 shu_r0_b0_rxdly3;
-	u32 shu_r0_b0_rxdly4;
-	u32 shu_r0_b0_rxdly5;
-	u32 shu_rk_b0_dq1;
-	u32 shu_b0_phy_vref_sel;
-	u32 shu_r0_b0_dq0;
-	u32 shu_r0_b0_ini_uipi;
-	u32 shu_r0_b0_next_ini_uipi;
-	u32 shu_dqsien_mck_ui_dly;
-	u32 shu_rk_b0_dqsien_pi_dly;
-	u32 shu_rk_b0_rodten_mck_ui_dly;
-	u32 shu_rk_b0_dq0;
-	u32 rsvd_0[4];
-	u32 shu_rk_b0_bist_ctrl;
-	u32 rsvd_1[7];
-};
-
-struct phy_ao_shu_byte {
-	struct phy_ao_rk rk[RANK_MAX];
-	u32 shu_b0_dq0;
-	u32 shu_b0_dq3;
-	u32 shu_b0_dq4;
-	u32 shu_b0_dq5;
-	u32 shu_b0_dq6;
-	u32 shu_b0_dq1;
-	u32 shu_b0_dq2;
-	u32 shu_b0_dq10;
-	u32 shu_b0_dq11;
-	u32 shu_b0_dq7;
-	u32 shu_b0_dq8;
-	u32 shu_b0_dq9;
-	u32 shu_b0_dq12;
-	u32 shu_b0_dll0;
-	u32 shu_b0_dll1;
-	u32 shu_b0_dll2;
-	u32 shu_b0_rank_selph_ui_dly;
-	u32 shu_b0_dll_arpi2;
-	u32 shu_b0_dll_arpi3;
-	u32 shu_b0_txduty;
-	u32 shu_b0_vref;
-	u32 shu_b0_dq13;
-	u32 shu_b0_dq14;
-	u32 b0_shu_midpi_ctrl;
-	u32 rsvd_16[8];
-};
-
-struct phy_ao_rx_dvs_byte {
-	struct {
-		u32 rk_b0_rxdvs0;
-		u32 rk_b0_rxdvs1;
-		u32 rk_b0_rxdvs2;
-		u32 rk_b0_rxdvs3;
-		u32 rk_b0_rxdvs4;
-		u32 rsvd[27];
-	} rk[RANK_MAX];
-	u32 b0_lp_ctrl0;
-	u32 b0_rxdvs0;
-	u32 b0_rxdvs1;
-	u32 b0_dll_arpi0;
-	u32 b0_dll_arpi1;
-	u32 b0_dll_arpi4;
-	u32 b0_dll_arpi5;
-	u32 b0_dq2;
-	u32 b0_dq3;
-	u32 b0_dq4;
-	u32 b0_dq5;
-	u32 b0_dq6;
-	u32 b0_dq7;
-	u32 b0_dq8;
-	u32 b0_dq9;
-	u32 b0_dq10;
-	u32 b0_dq11;
-	u32 b0_phy2;
-	u32 b0_phy3;
-	u32 b0_tx_mck;
-	u32 rsvd_3[12];
-};
-
-struct phy_ao_ca_rk {
-	u32 shu_r0_ca_txdly0;
-	u32 shu_r0_ca_txdly1;
-	u32 shu_r0_ca_txdly2;
-	u32 shu_r0_ca_txdly3;
-	u32 shu_r0_ca_txdly4;
-	u32 shu_r0_ca_rxdly0;
-	u32 shu_r0_ca_rxdly1;
-	u32 shu_r0_ca_rxdly2;
-	u32 shu_r0_ca_rxdly6;
-	u32 shu_r0_ca_rxdly3;
-	u32 shu_r0_ca_rxdly4;
-	u32 shu_r0_ca_rxdly5;
-	u32 shu_r0_ca_rxdly7;
-	u32 shu_r0_ca_cmd0;
-	u32 shu_r0_ca_ini_uipi;
-	u32 shu_r0_ca_next_ini_uipi;
-	u32 shu_rk_ca_dqsien_mck_ui_dly;
-	u32 shu_rk_ca_dqsien_pi_dly;
-	u32 shu_rk_ca_rodten_mck_ui_dly;
-	u32 shu_rk_ca_cmd0;
-	u32 shu_rk_ca_cmd1;
-	u32 shu_ca_phy_vref_sel;
-	u32 rsvd[10];
-};
-
-struct phy_ao_misc_rk {
-	u32 misc_shu_rk_dqsctl;
-	u32 misc_shu_rk_dqsien_picg_ctrl;
-	u32 misc_shu_rk_dqscal;
-	u32 rsvd[29];
-};
-
-struct ddrphy_ao_regs {
-	u32 phypll0;
-	u32 phypll1;
-	u32 phypll2;
-	u32 rsvd_0[5];
-	u32 clrpll0;
-	u32 rsvd_1[15];
-	struct phy_ao_rx_dvs_byte dvs_b[BYTE_NUM];
-	u32 rk_ca_rxdvs0;
-	u32 rk_ca_rxdvs1;
-	u32 rk_ca_rxdvs2;
-	u32 rk_ca_rxdvs3;
-	u32 rk_ca_rxdvs4;
-	u32 rsvd_6[59];
-	u32 ca_lp_ctrl0;
-	u32 ca_rxdvs0;
-	u32 ca_rxdvs1;
-	u32 ca_dll_arpi0;
-	u32 ca_dll_arpi1;
-	u32 ca_dll_arpi4;
-	u32 ca_dll_arpi5;
-	u32 ca_cmd2;
-	u32 ca_cmd3;
-	u32 ca_cmd4;
-	u32 ca_cmd5;
-	u32 ca_cmd6;
-	u32 ca_cmd7;
-	u32 ca_cmd8;
-	u32 ca_cmd9;
-	u32 ca_cmd10;
-	u32 ca_cmd11;
-	u32 ca_phy2;
-	u32 ca_phy3;
-	u32 ca_tx_mck;
-	u32 rsvd_7[12];
-	u32 misc_stbcal;
-	u32 misc_stbcal1;
-	u32 misc_stbcal2;
-	u32 misc_cg_ctrl0;
-	u32 misc_cg_ctrl1;
-	u32 misc_cg_ctrl2;
-	u32 misc_cg_ctrl3;
-	u32 rsvd_8[1];
-	u32 misc_cg_ctrl5;
-	u32 misc_cg_ctrl7;
-	u32 misc_cg_ctrl9;
-	u32 misc_cg_ctrl10;
-	u32 misc_dvfsctl;
-	u32 misc_dvfsctl2;
-	u32 misc_dvfsctl3;
-	u32 misc_ckmux_sel;
-	u32 misc_clk_ctrl;
-	u32 misc_dqsg_retry1;
-	u32 misc_rdsel_track;
-	u32 misc_pre_tdqsck1;
-	u32 misc_cdc_ctrl;
-	u32 misc_lp_ctrl;
-	u32 misc_rg_dfs_ctrl;
-	u32 misc_ddr_reserve;
-	u32 misc_imp_ctrl1;
-	u32 misc_impcal;
-	u32 misc_impcal1;
-	u32 misc_impedamce_ctrl1;
-	u32 misc_impedamce_ctrl2;
-	u32 misc_impedamce_ctrl3;
-	u32 misc_impedamce_ctrl4;
-	u32 misc_peripher_ctrl2;
-	u32 misc_apb;
-	u32 misc_extlb0;
-	u32 misc_extlb1;
-	u32 misc_extlb2;
-	u32 misc_extlb3;
-	u32 misc_extlb4;
-	u32 misc_extlb5;
-	u32 misc_extlb6;
-	u32 misc_extlb7;
-	u32 misc_extlb8;
-	u32 misc_extlb9;
-	u32 misc_extlb10;
-	u32 misc_extlb11;
-	u32 misc_extlb12;
-	u32 misc_extlb13;
-	u32 misc_extlb14;
-	u32 misc_extlb15;
-	u32 misc_extlb16;
-	u32 misc_extlb17;
-	u32 misc_extlb18;
-	u32 misc_extlb19;
-	u32 misc_extlb20;
-	u32 misc_extlb21;
-	u32 misc_extlb22;
-	u32 misc_extlb23;
-	u32 misc_extlb_rx0;
-	u32 misc_extlb_rx1;
-	u32 misc_extlb_rx2;
-	u32 misc_extlb_rx3;
-	u32 misc_extlb_rx4;
-	u32 misc_extlb_rx5;
-	u32 misc_extlb_rx6;
-	u32 misc_extlb_rx7;
-	u32 misc_extlb_rx8;
-	u32 misc_extlb_rx9;
-	u32 misc_extlb_rx10;
-	u32 misc_extlb_rx11;
-	u32 misc_extlb_rx12;
-	u32 misc_extlb_rx13;
-	u32 misc_extlb_rx14;
-	u32 misc_extlb_rx15;
-	u32 misc_extlb_rx16;
-	u32 misc_extlb_rx17;
-	u32 misc_extlb_rx18;
-	u32 misc_extlb_rx19;
-	u32 misc_extlb_rx20;
-	u32 misc_sram_dma0;
-	u32 misc_sram_dma1;
-	u32 misc_sram_dma2;
-	u32 misc_dutyscan1;
-	u32 misc_miock_jit_mtr;
-	u32 misc_jmeter;
-	u32 misc_dvfs_emi_clk;
-	u32 misc_rx_in_gate_en_ctrl;
-	u32 misc_rx_in_buff_en_ctrl;
-	u32 misc_ctrl0;
-	u32 misc_ctrl1;
-	u32 misc_ctrl2;
-	u32 misc_ctrl3;
-	u32 misc_ctrl4;
-	u32 misc_ctrl5;
-	u32 misc_ctrl6;
-	u32 misc_vref_ctrl;
-	u32 misc_shu_opt;
-	u32 misc_rxdvs0;
-	u32 misc_rxdvs2;
-	u32 misc_dqsien_autok_cfg0;
-	u32 misc_dline_mon_cfg;
-	u32 misc_rx_autok_cfg0;
-	u32 misc_rx_autok_cfg1;
-	u32 rsvd_9[2];
-	u32 misc_dbg_irq_ctrl0;
-	u32 misc_dbg_irq_ctrl1;
-	u32 misc_dbg_irq_ctrl2;
-	u32 misc_dbg_irq_ctrl3;
-	u32 misc_dbg_irq_ctrl4;
-	u32 misc_dbg_irq_ctrl5;
-	u32 misc_dbg_irq_ctrl6;
-	u32 misc_dbg_irq_ctrl7;
-	u32 misc_dbg_irq_ctrl8;
-	u32 misc_dbg_irq_ctrl9;
-	u32 rsvd_10[2];
-	u32 misc_dq_se_pinmux_ctrl0;
-	u32 misc_dq_se_pinmux_ctrl1;
-	u32 rsvd_11[2];
-	u32 misc_bist_lpbk_ctrl0;
-	u32 rsvd_12[15];
-	u32 shu_phypll0;
-	u32 shu_phypll1;
-	u32 shu_phypll2;
-	u32 shu_phypll3;
-	u32 shu_phypll4;
-	u32 shu_phypll5;
-	u32 shu_phypll6;
-	u32 shu_phypll7;
-	u32 shu_clrpll0;
-	u32 shu_clrpll1;
-	u32 shu_clrpll2;
-	u32 shu_clrpll3;
-	u32 shu_clrpll4;
-	u32 shu_clrpll5;
-	u32 shu_clrpll6;
-	u32 shu_clrpll7;
-	u32 shu_pll0;
-	u32 shu_pll1;
-	u32 shu_pll2;
-	u32 rsvd_13[5];
-	struct phy_ao_shu_byte byte[BYTE_NUM];
-	struct phy_ao_ca_rk ca_rk[RANK_MAX];
-	u32 shu_ca_cmd0;
-	u32 shu_ca_cmd3;
-	u32 shu_ca_cmd4;
-	u32 shu_ca_cmd5;
-	u32 shu_ca_cmd6;
-	u32 shu_ca_cmd1;
-	u32 shu_ca_cmd2;
-	u32 shu_ca_cmd10;
-	u32 shu_ca_cmd11;
-	u32 shu_ca_cmd7;
-	u32 shu_ca_cmd8;
-	u32 shu_ca_cmd9;
-	u32 shu_ca_cmd12;
-	u32 shu_ca_dll0;
-	u32 shu_ca_dll1;
-	u32 shu_ca_dll2;
-	u32 shu_ca_rank_selph_ui_dly;
-	u32 shu_ca_dll_arpi2;
-	u32 shu_ca_dll_arpi3;
-	u32 shu_ca_txduty;
-	u32 shu_ca_vref;
-	u32 shu_ca_cmd13;
-	u32 shu_ca_cmd14;
-	u32 ca_shu_midpi_ctrl;
-	u32 rsvd_21[8];
-	struct phy_ao_misc_rk misc_rk[RANK_MAX];
-	u32 misc_shu_drving7;
-	u32 misc_shu_drving8;
-	u32 misc_shu_impedamce_offset1;
-	u32 misc_shu_impedamce_offset2;
-	u32 misc_shu_impedamce_offset3;
-	u32 misc_shu_impedamce_offset4;
-	u32 misc_shu_impedamce_offset5;
-	u32 misc_shu_impedamce_offset6;
-	u32 misc_shu_impedamce_offset7;
-	u32 misc_shu_impedamce_offset8;
-	u32 misc_shu_impedamce_offset9;
-	u32 misc_shu_impedamce_upd_dis1;
-	u32 shu_misc_sw_impcal;
-	u32 misc_shu_stbcal;
-	u32 misc_shu_stbcal1;
-	u32 misc_shu_dvfsdll;
-	u32 misc_shu_rankctl;
-	u32 misc_shu_phy_rx_ctrl;
-	u32 misc_shu_odtctrl;
-	u32 misc_shu_rodtenstb;
-	u32 misc_shu_rodtenstb1;
-	u32 misc_shu_dqsg_retry1;
-	u32 misc_shu_rdat;
-	u32 misc_shu_rdat1;
-	u32 shu_misc_clk_ctrl0;
-	u32 shu_misc_impcal1;
-	u32 shu_misc_drving1;
-	u32 shu_misc_drving2;
-	u32 shu_misc_drving3;
-	u32 shu_misc_drving4;
-	u32 shu_misc_drving5;
-	u32 shu_misc_drving6;
-	u32 shu_misc_duty_scan;
-	u32 shu_misc_dma;
-	u32 shu_misc_rvref;
-	u32 shu_misc_rx_pipe_ctrl;
-	u32 shu_misc_tx_pipe_ctrl;
-	u32 shu_misc_emi_ctrl;
-	u32 shu_misc_rank_sel_stb;
-	u32 shu_misc_rdsel_track;
-	u32 shu_misc_pre_tdqsck;
-	u32 shu_misc_async_fifo_ctrl;
-	u32 misc_shu_rx_selph_mode;
-	u32 misc_shu_rank_sel_lat;
-	u32 misc_shu_dline_mon_ctrl;
-	u32 misc_shu_dline_mon_cnt;
-	u32 misc_shu_midpi_ctrl;
-	u32 rsvd_23[1];
-	u32 misc_shu_rx_cg_ctrl;
-	u32 misc_shu_cg_ctrl0;
-	u32 rsvd_24[470];
-	u32 misc_stberr_all;
-	u32 misc_stberr_rk0_r;
-	u32 misc_stberr_rk0_f;
-	u32 misc_stberr_rk1_r;
-	u32 misc_stberr_rk1_f;
-	u32 rsvd_25[3];
-	u32 misc_ddr_reserve_state;
-	u32 rsvd_26[3];
-	u32 misc_irq_status0;
-	u32 misc_irq_status1;
-	u32 misc_irq_status2;
-	u32 rsvd_27[49];
-	u32 misc_dbg_db_message0;
-	u32 misc_dbg_db_message1;
-	u32 misc_dbg_db_message2;
-	u32 misc_dbg_db_message3;
-	u32 misc_dbg_db_message4;
-	u32 misc_dbg_db_message5;
-	u32 misc_dbg_db_message6;
-	u32 misc_dbg_db_message7;
-};
-
-struct emi_chn_regs {
-	u32 cona;
-	u32 rsvd_0[1];
-	u32 conb;
-	u32 rsvd_1[1];
-	u32 conc;
-	u32 rsvd_2[1];
-	u32 mdct;
-	u32 rsvd_3[1];
-	u32 ebg_con;
-	u32 rsvd_4[9];
-	u32 testb;
-	u32 rsvd_5[1];
-	u32 testc;
-	u32 rsvd_6[1];
-	u32 testd;
-	u32 rsvd_7[9];
-	u32 md_pre_mask;
-	u32 rsvd_8[1];
-	u32 md_pre_mask_shf;
-	u32 rsvd_9[1];
-	u32 ap_early_cke;
-	u32 rsvd_10[1];
-	u32 dqfr;
-	u32 rsvd_11[41];
-	u32 arbi;
-	u32 arbi_2nd;
-	u32 arbj;
-	u32 arbj_2nd;
-	u32 arbk;
-	u32 arbk_2nd;
-	u32 slct;
-	u32 arb_rff;
-	u32 rsvd_12[3];
-	u32 drs_mon0;
-	u32 drs_mon1;
-	u32 rsvd_13[15];
-	u32 rkarb0;
-	u32 rkarb1;
-	u32 rkarb2;
-	u32 rsvd_14[144];
-	u32 eco3;
-	u32 rsvd_15[1];
-	u32 md_pre_mask_shf0;
-	u32 md_pre_mask_shf1;
-	u32 qos_mdr_shf0;
-	u32 rsvd_16[192];
-	u32 shf0;
-};
-
-struct emi_mpu_regs {
-	u32 mpu_ctrl;
-	u32 rsvd[511];
-	u32 mpu_ctrl_d[16];
-};
-
-struct infra_ao_mem_regs {
-	u32 rsvd_0[10];
-	u32 emi_dcm_cfg0;
-	u32 emi_dcm_cfg1;
-	u32 emi_dcm_cfg2;
-	u32 emi_dcm_cfg3;
-	u32 top_ck_anchor_cfg;
-	u32 rsvd_2[5];
-	u32 emi_disph_cfg;
-	u32 rsvd_3[43];
-	u32 emi_idle_bit_en_0;
-	u32 emi_idle_bit_en_1;
-	u32 emi_idle_bit_en_2;
-	u32 emi_idle_bit_en_3;
-	u32 emi_m0m1_idle_bit_en_0;
-	u32 emi_m0m1_idle_bit_en_1;
-	u32 emi_m0m1_idle_bit_en_2;
-	u32 emi_m0m1_idle_bit_en_3;
-	u32 emi_m2m5_idle_bit_en_0;
-	u32 emi_m2m5_idle_bit_en_1;
-	u32 emi_m2m5_idle_bit_en_2;
-	u32 emi_m2m5_idle_bit_en_3;
-	u32 emi_m3_idle_bit_en_0;
-	u32 emi_m3_idle_bit_en_1;
-	u32 emi_m3_idle_bit_en_2;
-	u32 emi_m3_idle_bit_en_3;
-	u32 emi_m4_idle_bit_en_0;
-	u32 emi_m4_idle_bit_en_1;
-	u32 emi_m4_idle_bit_en_2;
-	u32 emi_m4_idle_bit_en_3;
-	u32 emi_m6m7_idle_bit_en_0;
-	u32 emi_m6m7_idle_bit_en_1;
-	u32 emi_m6m7_idle_bit_en_2;
-	u32 emi_m6m7_idle_bit_en_3;
-	u32 emi_sram_idle_bit_en_0;
-	u32 emi_sram_idle_bit_en_1;
-	u32 emi_sram_idle_bit_en_2;
-	u32 emi_sram_idle_bit_en_3;
-};
-
-struct dramc_channel_regs {
-	union {
-		struct dramc_ao_regs ao;
-		uint8_t raw_ao_regs[0x4000];
-	};
-	union {
-		struct dramc_nao_regs nao;
-		uint8_t raw_nao_regs[0x1000];
-	};
-	union {
-		struct emi_chn_regs emi_chn;
-		uint8_t raw_emi_regs[0x1000];
-	};
-	union {
-		struct ddrphy_nao_regs phy_nao;
-		uint8_t raw_ddrphy_nao_regs[0x2000];
-	};
-	union {
-		struct ddrphy_ao_regs phy_ao;
-		uint8_t raw_ddrphy_ao_regs[0x8000];
-	};
-};
-
-static struct dramc_channel_regs *const ch = (void *)DRAMC_CHA_AO_BASE;
-#endif /* __SOC_MEDIATEK_MT8192_DRAMC_REGISTER_H__ */
diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_register_bits_def.h b/src/soc/mediatek/mt8192/include/soc/dramc_register_bits_def.h
deleted file mode 100644
index 82ae8b587c..0000000000
--- a/src/soc/mediatek/mt8192/include/soc/dramc_register_bits_def.h
+++ /dev/null
@@ -1,2837 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __SOC_MEDIATEK_MT8192_DRAMC_MACRO_DEF_H__
-#define __SOC_MEDIATEK_MT8192_DRAMC_MACRO_DEF_H__
-
-/* DDRPHY_REG_PHYPLL1 */
-DEFINE_BIT(PHYPLL1_RG_RPHYPLL_TSTOP_EN, 0)
-DEFINE_BIT(PHYPLL1_RG_RPHYPLL_TST_EN, 4)
-
-/* DDRPHY_REG_SHU_PHYPLL0 */
-DEFINE_BITFIELD(SHU_PHYPLL0_RG_RPHYPLL_RESERVED, 15, 0)
-DEFINE_BITFIELD(SHU_PHYPLL0_RG_RPHYPLL_ICHP, 25, 24)
-
-/* DDRPHY_REG_SHU_CLRPLL0 */
-DEFINE_BITFIELD(SHU_CLRPLL0_RG_RCLRPLL_RESERVED, 15, 0)
-DEFINE_BITFIELD(SHU_CLRPLL0_RG_RCLRPLL_ICHP, 25, 24)
-
-/* DDRPHY_REG_SHU_PHYPLL2 */
-DEFINE_BITFIELD(SHU_PHYPLL2_RG_RPHYPLL_POSDIV, 2, 0)
-DEFINE_BITFIELD(SHU_PHYPLL2_RG_RPHYPLL_PREDIV, 19, 18)
-
-/* DDRPHY_REG_SHU_CLRPLL2 */
-DEFINE_BITFIELD(SHU_CLRPLL2_RG_RCLRPLL_POSDIV, 2, 0)
-DEFINE_BITFIELD(SHU_CLRPLL2_RG_RCLRPLL_PREDIV, 19, 18)
-
-/* DDRPHY_REG_SHU_PHYPLL1 */
-DEFINE_BIT(SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN, 0)
-DEFINE_BIT(SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW_CHG, 1)
-DEFINE_BITFIELD(SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW, 31, 16)
-
-/* DDRPHY_REG_SHU_CLRPLL1 */
-DEFINE_BIT(SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN, 0)
-DEFINE_BIT(SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW_CHG, 1)
-DEFINE_BITFIELD(SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW, 31, 16)
-
-/* DDRPHY_REG_SHU_PLL1 */
-DEFINE_BIT(SHU_PLL1_RG_RPHYPLLGP_CK_SEL, 0)
-DEFINE_BIT(SHU_PLL1_R_SHU_AUTO_PLL_MUX, 4)
-
-/* DDRPHY_REG_SHU_PHYPLL3 */
-DEFINE_BIT(SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL, 0)
-DEFINE_BIT(SHU_PHYPLL3_RG_RPHYPLL_FBKSEL, 6)
-DEFINE_BITFIELD(SHU_PHYPLL3_RG_RPHYPLL_RST_DLY, 9, 8)
-DEFINE_BIT(SHU_PHYPLL3_RG_RPHYPLL_LVROD_EN, 12)
-DEFINE_BIT(SHU_PHYPLL3_RG_RPHYPLL_MONCK_EN, 16)
-
-/* DDRPHY_REG_SHU_CLRPLL3 */
-DEFINE_BIT(SHU_CLRPLL3_RG_RCLRPLL_DIV_CK_SEL, 0)
-DEFINE_BIT(SHU_CLRPLL3_RG_RCLRPLL_FBKSEL, 6)
-DEFINE_BITFIELD(SHU_CLRPLL3_RG_RCLRPLL_RST_DLY, 9, 8)
-DEFINE_BIT(SHU_CLRPLL3_RG_RCLRPLL_LVROD_EN, 12)
-DEFINE_BIT(SHU_CLRPLL3_RG_RCLRPLL_MONCK_EN, 16)
-
-/* DDRPHY_REG_SHU_MISC_CLK_CTRL0 */
-DEFINE_BIT(SHU_MISC_CLK_CTRL0_M_CK_OPENLOOP_MODE_SEL, 4)
-
-/* DDRPHY_REG_SHU_B0_DQ14 */
-DEFINE_BIT(SHU_B0_DQ14_RG_TX_ARWCK_MCKIO_SEL_B0, 2)
-DEFINE_BITFIELD(SHU_B0_DQ14_RG_TX_ARDQ_SER_MODE_B0, 5, 4)
-DEFINE_BIT(SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0, 11)
-DEFINE_BITFIELD(SHU_B0_DQ14_RG_TX_ARDQ_MCKIO_SEL_B0, 23, 16)
-
-/* DDRPHY_REG_SHU_B1_DQ14 */
-DEFINE_BIT(SHU_B1_DQ14_RG_TX_ARWCK_MCKIO_SEL_B1, 2)
-DEFINE_BITFIELD(SHU_B1_DQ14_RG_TX_ARDQ_SER_MODE_B1, 5, 4)
-DEFINE_BIT(SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1, 11)
-DEFINE_BITFIELD(SHU_B1_DQ14_RG_TX_ARDQ_MCKIO_SEL_B1, 23, 16)
-
-/* DDRPHY_REG_SHU_B0_DQ6 */
-DEFINE_BITFIELD(SHU_B0_DQ6_RG_ARPI_CAP_SEL_B0, 18, 12)
-DEFINE_BIT(SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0, 20)
-DEFINE_BIT(SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0, 21)
-DEFINE_BITFIELD(SHU_B0_DQ6_RG_ARPI_HYST_SEL_B0, 23, 22)
-DEFINE_BIT(SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0, 29)
-
-/* DDRPHY_REG_SHU_B1_DQ6 */
-DEFINE_BITFIELD(SHU_B1_DQ6_RG_ARPI_CAP_SEL_B1, 18, 12)
-DEFINE_BIT(SHU_B1_DQ6_RG_ARPI_SOPEN_EN_B1, 20)
-DEFINE_BIT(SHU_B1_DQ6_RG_ARPI_OPEN_EN_B1, 21)
-DEFINE_BITFIELD(SHU_B1_DQ6_RG_ARPI_HYST_SEL_B1, 23, 22)
-DEFINE_BIT(SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1, 29)
-
-/* DDRPHY_REG_SHU_CA_CMD11 */
-DEFINE_BIT(SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA, 0)
-DEFINE_BIT(SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_LAT_EN_CA, 1)
-DEFINE_BIT(SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_LAT_EN_CA, 2)
-DEFINE_BITFIELD(SHU_CA_CMD11_RG_RX_ARCA_DES_MODE_CA, 17, 16)
-DEFINE_BITFIELD(SHU_CA_CMD11_RG_RX_ARCA_BW_SEL_CA, 19, 18)
-
-/* DDRPHY_REG_SHU_B0_DQ11 */
-DEFINE_BIT(SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0, 0)
-DEFINE_BIT(SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0, 1)
-DEFINE_BIT(SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0, 2)
-DEFINE_BIT(SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0, 7)
-DEFINE_BITFIELD(SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0, 17, 16)
-DEFINE_BITFIELD(SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0, 19, 18)
-
-/* DDRPHY_REG_SHU_B1_DQ11 */
-DEFINE_BIT(SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1, 0)
-DEFINE_BIT(SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1, 1)
-DEFINE_BIT(SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1, 2)
-DEFINE_BIT(SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1, 7)
-DEFINE_BITFIELD(SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1, 17, 16)
-DEFINE_BITFIELD(SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1, 19, 18)
-
-/* DDRPHY_REG_SHU_CA_CMD14 */
-DEFINE_BITFIELD(SHU_CA_CMD14_RG_TX_ARCA_SER_MODE_CA, 5, 4)
-DEFINE_BIT(SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_CG_EN_CA, 11)
-DEFINE_BITFIELD(SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA, 23, 16)
-
-/* DDRPHY_REG_SHU_CA_CMD6 */
-DEFINE_BITFIELD(SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA, 5, 0)
-DEFINE_BITFIELD(SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA, 18, 12)
-DEFINE_BIT(SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA, 20)
-DEFINE_BIT(SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA, 21)
-DEFINE_BITFIELD(SHU_CA_CMD6_RG_ARPI_HYST_SEL_CA, 23, 22)
-DEFINE_BIT(SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA, 26)
-DEFINE_BIT(SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA, 27)
-DEFINE_BIT(SHU_CA_CMD6_RG_RX_ARCMD_RANK_SEL_SER_MODE, 29)
-
-/* DDRPHY_REG_SHU_B0_DLL1 */
-DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_UDIV_EN_B0, 4)
-DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_TRACKING_CA_EN_B0, 6)
-DEFINE_BITFIELD(SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0, 9, 8)
-DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PS_EN_B0, 10)
-DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PSJP_EN_B0, 11)
-DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PHDIV_B0, 12)
-DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0, 13)
-DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PHDET_IN_SWAP_B0, 14)
-DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0, 16)
-DEFINE_BITFIELD(SHU_B0_DLL1_RG_ARDLL_PGAIN_B0, 23, 20)
-DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0, 24)
-
-/* DDRPHY_REG_SHU_B1_DLL1 */
-DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1, 4)
-DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_TRACKING_CA_EN_B1, 6)
-DEFINE_BITFIELD(SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1, 9, 8)
-DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PS_EN_B1, 10)
-DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1, 11)
-DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PHDIV_B1, 12)
-DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1, 13)
-DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1, 14)
-DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1, 16)
-DEFINE_BITFIELD(SHU_B1_DLL1_RG_ARDLL_PGAIN_B1, 23, 20)
-DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1, 24)
-
-/* DDRPHY_REG_SHU_CA_DLL1 */
-DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA, 4)
-DEFINE_BITFIELD(SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA, 9, 8)
-DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PS_EN_CA, 10)
-DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA, 11)
-DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PHDIV_CA, 12)
-DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA, 13)
-DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA, 14)
-DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 16)
-DEFINE_BITFIELD(SHU_CA_DLL1_RG_ARDLL_PGAIN_CA, 23, 20)
-DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA, 24)
-
-/* DDRPHY_REG_SHU_B0_DQ1 */
-DEFINE_BIT(SHU_B0_DQ1_RG_ARPI_MIDPI_EN_B0, 0)
-DEFINE_BIT(SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0, 2)
-DEFINE_BITFIELD(SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0, 12, 8)
-DEFINE_BITFIELD(SHU_B0_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B0, 17, 16)
-DEFINE_BIT(SHU_B0_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B0, 26)
-DEFINE_BIT(SHU_B0_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B0, 27)
-DEFINE_BIT(SHU_B0_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B0, 31)
-
-/* DDRPHY_REG_SHU_B1_DQ1 */
-DEFINE_BIT(SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1, 0)
-DEFINE_BIT(SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1, 2)
-DEFINE_BITFIELD(SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1, 12, 8)
-DEFINE_BITFIELD(SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1, 17, 16)
-DEFINE_BIT(SHU_B1_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B1, 26)
-DEFINE_BIT(SHU_B1_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B1, 27)
-DEFINE_BIT(SHU_B1_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B1, 31)
-
-/* DDRPHY_REG_SHU_CA_DLL_ARPI3 */
-DEFINE_BIT(SHU_CA_DLL_ARPI3_RG_ARPI_CLKIEN_EN, 11)
-DEFINE_BIT(SHU_CA_DLL_ARPI3_RG_ARPI_CMD_EN, 13)
-DEFINE_BIT(SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN, 15)
-DEFINE_BIT(SHU_CA_DLL_ARPI3_RG_ARPI_CS_EN, 16)
-DEFINE_BIT(SHU_CA_DLL_ARPI3_RG_ARPI_FB_EN_CA, 17)
-DEFINE_BIT(SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA, 19)
-
-/* DDRPHY_REG_SHU_CA_CMD13 */
-DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCA_IO_ODT_DIS_CA, 0)
-DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCA_FRATE_EN_CA, 1)
-DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA, 2)
-DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_CG_EN_CA, 7)
-DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCS_OE_ODTEN_CG_EN_CA, 16)
-DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA, 17)
-DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA, 24)
-DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA, 25)
-
-/* DDRPHY_REG_SHU_CA_CMD1 */
-DEFINE_BIT(SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA, 0)
-DEFINE_BIT(SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA, 1)
-DEFINE_BIT(SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA, 2)
-DEFINE_BITFIELD(SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA, 12, 8)
-DEFINE_BITFIELD(SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA, 17, 16)
-DEFINE_BIT(SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA, 27)
-DEFINE_BIT(SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA, 31)
-
-/* DDRPHY_REG_SHU_CA_DLL_ARPI2 */
-DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA, 10)
-DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN, 11)
-DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_CMD, 13)
-DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLK, 15)
-DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_CS, 16)
-DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA, 17)
-DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA, 19)
-DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA, 27)
-DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA, 31)
-
-/* DDRPHY_REG_CA_DLL_ARPI5 */
-DEFINE_BITFIELD(CA_DLL_ARPI5_RG_ARDLL_MON_SEL_CA, 7, 4)
-DEFINE_BIT(CA_DLL_ARPI5_RG_ARDLL_DIV_DEC_CA, 8)
-DEFINE_BIT(CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_CA, 25)
-DEFINE_BIT(CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_CA, 26)
-DEFINE_BIT(CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA, 28)
-DEFINE_BITFIELD(CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA, 31, 29)
-
-/* DDRPHY_REG_B0_DLL_ARPI5 */
-DEFINE_BITFIELD(B0_DLL_ARPI5_RG_ARDLL_MON_SEL_B0, 7, 4)
-DEFINE_BIT(B0_DLL_ARPI5_RG_ARDLL_DIV_DEC_B0, 8)
-DEFINE_BIT(B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B0, 25)
-DEFINE_BIT(B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B0, 26)
-DEFINE_BIT(B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0, 28)
-DEFINE_BITFIELD(B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0, 31, 29)
-
-/* DDRPHY_REG_B1_DLL_ARPI5 */
-DEFINE_BITFIELD(B1_DLL_ARPI5_RG_ARDLL_MON_SEL_B1, 7, 4)
-DEFINE_BIT(B1_DLL_ARPI5_RG_ARDLL_DIV_DEC_B1, 8)
-DEFINE_BIT(B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B1, 25)
-DEFINE_BIT(B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B1, 26)
-DEFINE_BIT(B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1, 28)
-DEFINE_BITFIELD(B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1, 31, 29)
-
-/* DDRPHY_REG_CA_DLL_ARPI1 */
-DEFINE_BIT(CA_DLL_ARPI1_RG_ARPI_CLKIEN_JUMP_EN, 11)
-DEFINE_BIT(CA_DLL_ARPI1_RG_ARPI_CMD_JUMP_EN, 13)
-DEFINE_BIT(CA_DLL_ARPI1_RG_ARPI_CLK_JUMP_EN, 15)
-DEFINE_BIT(CA_DLL_ARPI1_RG_ARPI_CS_JUMP_EN, 16)
-DEFINE_BIT(CA_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_CA, 17)
-DEFINE_BIT(CA_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_CA, 19)
-DEFINE_BIT(CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT, 20)
-DEFINE_BIT(CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA, 21)
-
-/* DDRPHY_REG_B0_DLL_ARPI1 */
-DEFINE_BIT(B0_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B0, 11)
-DEFINE_BIT(B0_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B0, 13)
-DEFINE_BIT(B0_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B0, 14)
-DEFINE_BIT(B0_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B0, 15)
-DEFINE_BIT(B0_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B0, 17)
-DEFINE_BIT(B0_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B0, 19)
-DEFINE_BIT(B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0_REG_OPT, 20)
-DEFINE_BIT(B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0, 21)
-
-/* DDRPHY_REG_B1_DLL_ARPI1 */
-DEFINE_BIT(B1_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B1, 11)
-DEFINE_BIT(B1_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B1, 13)
-DEFINE_BIT(B1_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B1, 14)
-DEFINE_BIT(B1_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B1, 15)
-DEFINE_BIT(B1_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B1, 17)
-DEFINE_BIT(B1_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B1, 19)
-DEFINE_BIT(B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1_REG_OPT, 20)
-DEFINE_BIT(B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1, 21)
-
-/* DDRPHY_REG_SHU_CA_DLL0 */
-DEFINE_BITFIELD(SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA, 15, 12)
-DEFINE_BITFIELD(SHU_CA_DLL0_RG_ARDLL_GAIN_CA, 23, 20)
-DEFINE_BIT(SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA, 25)
-DEFINE_BIT(SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA, 26)
-DEFINE_BIT(SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA, 27)
-
-/* DDRPHY_REG_SHU_B0_DLL0 */
-DEFINE_BITFIELD(SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0, 15, 12)
-DEFINE_BITFIELD(SHU_B0_DLL0_RG_ARDLL_GAIN_B0, 23, 20)
-DEFINE_BIT(SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0, 25)
-DEFINE_BIT(SHU_B0_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B0, 26)
-DEFINE_BIT(SHU_B0_DLL0_RG_ARDLL_GEAR2_PSJP_B0, 27)
-
-/* DDRPHY_REG_SHU_B1_DLL0 */
-DEFINE_BITFIELD(SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1, 15, 12)
-DEFINE_BITFIELD(SHU_B1_DLL0_RG_ARDLL_GAIN_B1, 23, 20)
-DEFINE_BIT(SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1, 25)
-DEFINE_BIT(SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1, 26)
-DEFINE_BIT(SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1, 27)
-
-/* DDRPHY_REG_SHU_B0_DLL_ARPI3 */
-DEFINE_BIT(SHU_B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0, 11)
-DEFINE_BIT(SHU_B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0, 13)
-DEFINE_BIT(SHU_B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0, 14)
-DEFINE_BIT(SHU_B0_DLL_ARPI3_RG_ARPI_DQS_EN_B0, 15)
-DEFINE_BIT(SHU_B0_DLL_ARPI3_RG_ARPI_FB_EN_B0, 17)
-DEFINE_BIT(SHU_B0_DLL_ARPI3_RG_ARPI_MCTL_EN_B0, 19)
-
-/* DDRPHY_REG_SHU_B1_DLL_ARPI3 */
-DEFINE_BIT(SHU_B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1, 11)
-DEFINE_BIT(SHU_B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1, 13)
-DEFINE_BIT(SHU_B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1, 14)
-DEFINE_BIT(SHU_B1_DLL_ARPI3_RG_ARPI_DQS_EN_B1, 15)
-DEFINE_BIT(SHU_B1_DLL_ARPI3_RG_ARPI_FB_EN_B1, 17)
-DEFINE_BIT(SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1, 19)
-
-/* DDRPHY_REG_SHU_CA_CMD2 */
-DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_TX_CG_SYNC_DIS_CA, 0)
-DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_TX_CG_CA_EN_CA, 4)
-DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_TX_CG_CLK_EN_CA, 5)
-DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_TX_CG_CS_EN_CA, 6)
-DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_FORCE_CLK_CA, 8)
-DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_CA_FORCE_CA, 9)
-DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CA_CA, 10)
-DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CLK_CA, 11)
-DEFINE_BIT(SHU_CA_CMD2_RG_ARPISM_MCK_SEL_CA_SHU, 12)
-DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_PD_MCTL_SEL_CA, 13)
-DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA, 16)
-DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA, 17)
-
-/* DDRPHY_REG_SHU_B0_DQ2 */
-DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B0, 0)
-DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_TX_CG_DQ_EN_B0, 4)
-DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_TX_CG_DQS_EN_B0, 5)
-DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_TX_CG_DQM_EN_B0, 6)
-DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B0, 8)
-DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B0, 9)
-DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B0, 10)
-DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B0, 11)
-DEFINE_BIT(SHU_B0_DQ2_RG_ARPISM_MCK_SEL_B0_SHU, 12)
-DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_PD_MCTL_SEL_B0, 13)
-DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0, 16)
-DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0, 17)
-
-/* DDRPHY_REG_SHU_B1_DQ2 */
-DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B1, 0)
-DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_TX_CG_DQ_EN_B1, 4)
-DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_TX_CG_DQS_EN_B1, 5)
-DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_TX_CG_DQM_EN_B1, 6)
-DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B1, 8)
-DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B1, 9)
-DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B1, 10)
-DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1, 11)
-DEFINE_BIT(SHU_B1_DQ2_RG_ARPISM_MCK_SEL_B1_SHU, 12)
-DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_PD_MCTL_SEL_B1, 13)
-DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1, 16)
-DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1, 17)
-
-/* DDRPHY_REG_SHU_B0_DQ7 */
-DEFINE_BITFIELD(SHU_B0_DQ7_R_DMRANKRXDVS_B0, 3, 0)
-DEFINE_BIT(SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0, 6)
-DEFINE_BIT(SHU_B0_DQ7_R_DMDQMDBI_SHU_B0, 7)
-DEFINE_BITFIELD(SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0, 11, 8)
-DEFINE_BIT(SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0, 12)
-DEFINE_BIT(SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0, 13)
-DEFINE_BIT(SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0, 14)
-DEFINE_BIT(SHU_B0_DQ7_R_DMRODTEN_B0, 15)
-DEFINE_BIT(SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0, 16)
-DEFINE_BIT(SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 17)
-DEFINE_BIT(SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 18)
-DEFINE_BIT(SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 19)
-DEFINE_BIT(SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0, 20)
-DEFINE_BIT(SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0, 24)
-DEFINE_BITFIELD(SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0, 27, 25)
-DEFINE_BIT(SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0, 28)
-DEFINE_BITFIELD(SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0, 31, 29)
-
-/* DDRPHY_REG_SHU_B1_DQ7 */
-DEFINE_BITFIELD(SHU_B1_DQ7_R_DMRANKRXDVS_B1, 3, 0)
-DEFINE_BIT(SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1, 6)
-DEFINE_BIT(SHU_B1_DQ7_R_DMDQMDBI_SHU_B1, 7)
-DEFINE_BITFIELD(SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1, 11, 8)
-DEFINE_BIT(SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1, 12)
-DEFINE_BIT(SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1, 13)
-DEFINE_BIT(SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1, 14)
-DEFINE_BIT(SHU_B1_DQ7_R_DMRODTEN_B1, 15)
-DEFINE_BIT(SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1, 16)
-DEFINE_BIT(SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 17)
-DEFINE_BIT(SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 18)
-DEFINE_BIT(SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 19)
-DEFINE_BIT(SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1, 20)
-DEFINE_BIT(SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1, 24)
-DEFINE_BITFIELD(SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1, 27, 25)
-DEFINE_BIT(SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1, 28)
-DEFINE_BITFIELD(SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1, 31, 29)
-
-/* DDRPHY_REG_SHU_CA_CMD7 */
-DEFINE_BIT(SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW, 17)
-DEFINE_BIT(SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW, 19)
-DEFINE_BIT(SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK, 20)
-
-/* DDRPHY_REG_CA_CMD6 */
-DEFINE_BIT(CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN, 6)
-DEFINE_BITFIELD(CA_CMD6_RG_RX_ARCMD_BIAS_VREF_SEL, 15, 14)
-DEFINE_BIT(CA_CMD6_RG_RX_ARCMD_DDR4_SEL, 16)
-DEFINE_BIT(CA_CMD6_RG_TX_ARCMD_DDR4_SEL, 17)
-DEFINE_BIT(CA_CMD6_RG_RX_ARCMD_DDR3_SEL, 18)
-DEFINE_BIT(CA_CMD6_RG_TX_ARCMD_DDR3_SEL, 19)
-DEFINE_BIT(CA_CMD6_RG_TX_ARCMD_LP4_SEL, 21)
-
-/* DDRPHY_REG_B0_DQ6 */
-DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B0, 6)
-DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0, 7)
-DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_O1_SEL_B0, 9)
-DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_BIAS_EN_B0, 12)
-DEFINE_BITFIELD(B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0, 15, 14)
-DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_DDR4_SEL_B0, 16)
-DEFINE_BIT(B0_DQ6_RG_TX_ARDQ_DDR4_SEL_B0, 17)
-DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_DDR3_SEL_B0, 18)
-DEFINE_BIT(B0_DQ6_RG_TX_ARDQ_DDR3_SEL_B0, 19)
-DEFINE_BIT(B0_DQ6_RG_TX_ARDQ_LP4_SEL_B0, 21)
-DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B0, 28)
-DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0, 31)
-
-/* DDRPHY_REG_B1_DQ6 */
-DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B1, 6)
-DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1, 7)
-DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_O1_SEL_B1, 9)
-DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_BIAS_EN_B1, 12)
-DEFINE_BITFIELD(B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1, 15, 14)
-DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_DDR4_SEL_B1, 16)
-DEFINE_BIT(B1_DQ6_RG_TX_ARDQ_DDR4_SEL_B1, 17)
-DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_DDR3_SEL_B1, 18)
-DEFINE_BIT(B1_DQ6_RG_TX_ARDQ_DDR3_SEL_B1, 19)
-DEFINE_BIT(B1_DQ6_RG_TX_ARDQ_LP4_SEL_B1, 21)
-DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B1, 28)
-DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1, 31)
-
-/* DDRPHY_REG_CA_CMD2 */
-DEFINE_BIT(CA_CMD2_RG_TX_ARCLK_ODTEN_DIS_CA, 0)
-DEFINE_BIT(CA_CMD2_RG_TX_ARCLK_OE_DIS_CA, 1)
-DEFINE_BIT(CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA, 2)
-DEFINE_BIT(CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA, 3)
-DEFINE_BIT(CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA, 14)
-DEFINE_BIT(CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA, 15)
-DEFINE_BIT(CA_CMD2_RG_TX_ARCMD_ODTEN_DIS_CA, 20)
-DEFINE_BIT(CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 21)
-DEFINE_BIT(CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 22)
-DEFINE_BITFIELD(CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 31, 24)
-
-/* DDRPHY_REG_B0_DQ2 */
-DEFINE_BIT(B0_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B0, 0)
-DEFINE_BIT(B0_DQ2_RG_TX_ARDQS0_OE_DIS_B0, 1)
-DEFINE_BIT(B0_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B0, 2)
-DEFINE_BIT(B0_DQ2_RG_TX_ARDQS_OE_TIE_EN_B0, 3)
-DEFINE_BIT(B0_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B0, 8)
-DEFINE_BIT(B0_DQ2_RG_TX_ARWCK_OE_TIE_EN_B0, 9)
-DEFINE_BIT(B0_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B0, 10)
-DEFINE_BIT(B0_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B0, 11)
-DEFINE_BIT(B0_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B0, 12)
-DEFINE_BIT(B0_DQ2_RG_TX_ARDQM0_OE_DIS_B0, 13)
-DEFINE_BIT(B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0, 14)
-DEFINE_BIT(B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0, 15)
-DEFINE_BIT(B0_DQ2_RG_TX_ARDQ_ODTEN_DIS_B0, 20)
-DEFINE_BIT(B0_DQ2_RG_TX_ARDQ_OE_DIS_B0, 21)
-DEFINE_BIT(B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0, 22)
-DEFINE_BITFIELD(B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0, 31, 24)
-
-/* DDRPHY_REG_B1_DQ2 */
-DEFINE_BIT(B1_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B1, 0)
-DEFINE_BIT(B1_DQ2_RG_TX_ARDQS0_OE_DIS_B1, 1)
-DEFINE_BIT(B1_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B1, 2)
-DEFINE_BIT(B1_DQ2_RG_TX_ARDQS_OE_TIE_EN_B1, 3)
-DEFINE_BIT(B1_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B1, 8)
-DEFINE_BIT(B1_DQ2_RG_TX_ARWCK_OE_TIE_EN_B1, 9)
-DEFINE_BIT(B1_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B1, 10)
-DEFINE_BIT(B1_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B1, 11)
-DEFINE_BIT(B1_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B1, 12)
-DEFINE_BIT(B1_DQ2_RG_TX_ARDQM0_OE_DIS_B1, 13)
-DEFINE_BIT(B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1, 14)
-DEFINE_BIT(B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1, 15)
-DEFINE_BIT(B1_DQ2_RG_TX_ARDQ_ODTEN_DIS_B1, 20)
-DEFINE_BIT(B1_DQ2_RG_TX_ARDQ_OE_DIS_B1, 21)
-DEFINE_BIT(B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1, 22)
-DEFINE_BITFIELD(B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1, 31, 24)
-
-/* DDRPHY_REG_CA_CMD3 */
-DEFINE_BIT(CA_CMD3_RG_TX_ARCMD_EN, 2)
-DEFINE_BIT(CA_CMD3_RG_ARCMD_RESETB, 3)
-
-/* DDRPHY_REG_B0_DQ3 */
-DEFINE_BIT(B0_DQ3_RG_RX_ARDQ_SMT_EN_B0, 1)
-DEFINE_BIT(B0_DQ3_RG_TX_ARDQ_EN_B0, 2)
-DEFINE_BIT(B0_DQ3_RG_ARDQ_RESETB_B0, 3)
-DEFINE_BIT(B0_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B0, 5)
-DEFINE_BIT(B0_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B0, 7)
-DEFINE_BIT(B0_DQ3_RG_RX_ARDQ_STBENCMP_EN_B0, 10)
-
-/* DDRPHY_REG_B1_DQ3 */
-DEFINE_BIT(B1_DQ3_RG_RX_ARDQ_SMT_EN_B1, 1)
-DEFINE_BIT(B1_DQ3_RG_TX_ARDQ_EN_B1, 2)
-DEFINE_BIT(B1_DQ3_RG_ARDQ_RESETB_B1, 3)
-DEFINE_BIT(B1_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B1, 5)
-DEFINE_BIT(B1_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B1, 7)
-DEFINE_BIT(B1_DQ3_RG_RX_ARDQ_STBENCMP_EN_B1, 10)
-
-/* DDRPHY_REG_SHU_B0_DQ13 */
-DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0, 0)
-DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0, 2)
-DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0, 3)
-DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0, 7)
-DEFINE_BITFIELD(SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0, 13, 12)
-DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0, 15)
-DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0, 16)
-DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0, 17)
-DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0, 18)
-DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0, 24)
-DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0, 25)
-
-/* DDRPHY_REG_SHU_B1_DQ13 */
-DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1, 0)
-DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1, 2)
-DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1, 3)
-DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1, 7)
-DEFINE_BITFIELD(SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1, 13, 12)
-DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1, 15)
-DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1, 16)
-DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1, 17)
-DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1, 18)
-DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1, 24)
-DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1, 25)
-
-/* DDRPHY_REG_SHU_B0_DQ10 */
-DEFINE_BIT(SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0, 0)
-DEFINE_BIT(SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0, 1)
-DEFINE_BIT(SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B0, 2)
-DEFINE_BIT(SHU_B0_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B0, 3)
-DEFINE_BIT(SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0, 4)
-DEFINE_BITFIELD(SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0, 10, 8)
-DEFINE_BIT(SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0, 15)
-DEFINE_BITFIELD(SHU_B0_DQ10_RG_RX_ARDQS_BW_SEL_B0, 19, 18)
-
-/* DDRPHY_REG_SHU_B1_DQ10 */
-DEFINE_BIT(SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1, 0)
-DEFINE_BIT(SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1, 1)
-DEFINE_BIT(SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B1, 2)
-DEFINE_BIT(SHU_B1_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B1, 3)
-DEFINE_BIT(SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1, 4)
-DEFINE_BITFIELD(SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1, 10, 8)
-DEFINE_BIT(SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1, 15)
-DEFINE_BITFIELD(SHU_B1_DQ10_RG_RX_ARDQS_BW_SEL_B1, 19, 18)
-
-/* DDRPHY_REG_SHU_CA_CMD10 */
-DEFINE_BIT(SHU_CA_CMD10_RG_RX_ARCLK_DQSIEN_RANK_SEL_LAT_EN_CA, 2)
-DEFINE_BIT(SHU_CA_CMD10_RG_RX_ARCLK_RANK_SEL_LAT_EN_CA, 3)
-DEFINE_BIT(SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA, 15)
-DEFINE_BITFIELD(SHU_CA_CMD10_RG_RX_ARCLK_BW_SEL_CA, 19, 18)
-
-/* DDRPHY_REG_B0_DQ5 */
-DEFINE_BITFIELD(B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0, 13, 8)
-DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 16)
-DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0, 17)
-DEFINE_BITFIELD(B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0, 23, 20)
-DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_EYE_EN_B0, 24)
-DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0, 25)
-DEFINE_BIT(B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0, 31)
-
-/* DDRPHY_REG_B1_DQ5 */
-DEFINE_BITFIELD(B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1, 13, 8)
-DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 16)
-DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1, 17)
-DEFINE_BITFIELD(B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1, 23, 20)
-DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_EYE_EN_B1, 24)
-DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1, 25)
-DEFINE_BIT(B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1, 31)
-
-/* DDRPHY_REG_CA_CMD9 */
-DEFINE_BIT(CA_CMD9_RG_RX_ARCMD_STBEN_RESETB, 0)
-DEFINE_BIT(CA_CMD9_RG_RX_ARCLK_STBEN_RESETB, 4)
-
-/* DDRPHY_REG_B0_DQ9 */
-DEFINE_BIT(B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 0)
-DEFINE_BIT(B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 4)
-DEFINE_BIT(B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0, 5)
-DEFINE_BIT(B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0, 6)
-DEFINE_BIT(B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0, 7)
-DEFINE_BITFIELD(B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0, 15, 8)
-DEFINE_BITFIELD(B0_DQ9_R_DMDQSIEN_VALID_LAT_B0, 18, 16)
-DEFINE_BITFIELD(B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0, 22, 20)
-DEFINE_BITFIELD(B0_DQ9_R_DMRXDVS_VALID_LAT_B0, 26, 24)
-DEFINE_BITFIELD(B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0, 30, 28)
-
-/* DDRPHY_REG_B1_DQ9 */
-DEFINE_BIT(B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 0)
-DEFINE_BIT(B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 4)
-DEFINE_BIT(B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1, 5)
-DEFINE_BIT(B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1, 6)
-DEFINE_BIT(B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1, 7)
-DEFINE_BITFIELD(B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1, 15, 8)
-DEFINE_BITFIELD(B1_DQ9_R_DMDQSIEN_VALID_LAT_B1, 18, 16)
-DEFINE_BITFIELD(B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1, 22, 20)
-DEFINE_BITFIELD(B1_DQ9_R_DMRXDVS_VALID_LAT_B1, 26, 24)
-DEFINE_BITFIELD(B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1, 30, 28)
-
-/* DDRPHY_REG_CA_CMD8 */
-DEFINE_BIT(CA_CMD8_RG_RX_ARCLK_SER_RST_MODE, 13)
-DEFINE_BIT(CA_CMD8_RG_ARDLL_RESETB_CA, 15)
-
-/* DDRPHY_REG_B0_DQ8 */
-DEFINE_BIT(B0_DQ8_RG_RX_ARDQS_SER_RST_MODE_B0, 13)
-DEFINE_BIT(B0_DQ8_RG_ARDLL_RESETB_B0, 15)
-
-/* DDRPHY_REG_B1_DQ8 */
-DEFINE_BIT(B1_DQ8_RG_RX_ARDQS_SER_RST_MODE_B1, 13)
-DEFINE_BIT(B1_DQ8_RG_ARDLL_RESETB_B1, 15)
-
-/* DDRPHY_REG_CA_CMD11 */
-DEFINE_BITFIELD(CA_CMD11_RG_RRESETB_DRVP, 4, 0)
-DEFINE_BITFIELD(CA_CMD11_RG_RRESETB_DRVN, 12, 8)
-DEFINE_BIT(CA_CMD11_RG_TX_RRESETB_DDR3_SEL, 19)
-DEFINE_BIT(CA_CMD11_RG_TX_RRESETB_PULL_DN, 20)
-
-/* DDRPHY_REG_MISC_CTRL1 */
-DEFINE_BIT(MISC_CTRL1_R_RK_PINMUXSWAP_EN, 0)
-DEFINE_BIT(MISC_CTRL1_R_DMPHYRST, 1)
-DEFINE_BIT(MISC_CTRL1_R_DM_TX_ARCLK_OE, 2)
-DEFINE_BIT(MISC_CTRL1_R_DM_TX_ARCMD_OE, 3)
-DEFINE_BIT(MISC_CTRL1_R_DMARPIDQ_SW, 7)
-DEFINE_BITFIELD(MISC_CTRL1_R_DMPINMUX, 9, 8)
-DEFINE_BIT(MISC_CTRL1_R_DMRRESETB_I_OPT, 12)
-DEFINE_BIT(MISC_CTRL1_R_DMDA_RRESETB_I, 13)
-DEFINE_BIT(MISC_CTRL1_R_DMDQSIENCG_EN, 24)
-DEFINE_BIT(MISC_CTRL1_R_DMSTBENCMP_RK_OPT, 25)
-DEFINE_BIT(MISC_CTRL1_R_DMDA_RRESETB_E, 31)
-
-/* DDRPHY_REG_B0_LP_CTRL0 */
-DEFINE_BIT(B0_LP_CTRL0_RG_ARDMSUS_10_B0, 0)
-DEFINE_BIT(B0_LP_CTRL0_RG_ARDMSUS_10_B0_LP_SEL, 4)
-DEFINE_BIT(B0_LP_CTRL0_RG_ARDQ_RESETB_B0_LP_SEL, 8)
-DEFINE_BIT(B0_LP_CTRL0_RG_ARPI_RESETB_B0_LP_SEL, 9)
-DEFINE_BIT(B0_LP_CTRL0_RG_B0_MS_SLV_LP_SEL, 12)
-DEFINE_BIT(B0_LP_CTRL0_RG_ARDLL_PHDET_EN_B0_LP_SEL, 13)
-DEFINE_BIT(B0_LP_CTRL0_RG_RX_ARDQ_BIAS_EN_B0_LP_SEL, 16)
-DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_MCK_B0_LP_SEL, 17)
-DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_B0_LP_SEL, 18)
-DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_MCTL_B0_LP_SEL, 19)
-DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_FB_B0_LP_SEL, 20)
-DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_DQ_B0_LP_SEL, 21)
-DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_DQM_B0_LP_SEL, 22)
-DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_DQS_B0_LP_SEL, 23)
-DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_DQSIEN_B0_LP_SEL, 24)
-DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_MPDIV_CG_B0_LP_SEL, 25)
-DEFINE_BIT(B0_LP_CTRL0_RG_RX_ARDQ_VREF_EN_B0_LP_SEL, 26)
-DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_MIDPI_EN_B0_LP_SEL, 27)
-DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_B0_LP_SEL, 28)
-
-/* DDRPHY_REG_B1_LP_CTRL0 */
-DEFINE_BIT(B1_LP_CTRL0_RG_ARDMSUS_10_B1, 0)
-DEFINE_BIT(B1_LP_CTRL0_RG_ARDMSUS_10_B1_LP_SEL, 4)
-DEFINE_BIT(B1_LP_CTRL0_RG_ARDQ_RESETB_B1_LP_SEL, 8)
-DEFINE_BIT(B1_LP_CTRL0_RG_ARPI_RESETB_B1_LP_SEL, 9)
-DEFINE_BIT(B1_LP_CTRL0_RG_B1_MS_SLV_LP_SEL, 12)
-DEFINE_BIT(B1_LP_CTRL0_RG_ARDLL_PHDET_EN_B1_LP_SEL, 13)
-DEFINE_BIT(B1_LP_CTRL0_RG_RX_ARDQ_BIAS_EN_B1_LP_SEL, 16)
-DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_MCK_B1_LP_SEL, 17)
-DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_B1_LP_SEL, 18)
-DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_MCTL_B1_LP_SEL, 19)
-DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_FB_B1_LP_SEL, 20)
-DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_DQ_B1_LP_SEL, 21)
-DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_DQM_B1_LP_SEL, 22)
-DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_DQS_B1_LP_SEL, 23)
-DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_DQSIEN_B1_LP_SEL, 24)
-DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_MPDIV_CG_B1_LP_SEL, 25)
-DEFINE_BIT(B1_LP_CTRL0_RG_RX_ARDQ_VREF_EN_B1_LP_SEL, 26)
-DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_MIDPI_EN_B1_LP_SEL, 27)
-DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_B1_LP_SEL, 28)
-
-/* DDRPHY_REG_CA_LP_CTRL0 */
-DEFINE_BIT(CA_LP_CTRL0_RG_ARDMSUS_10_CA, 0)
-DEFINE_BIT(CA_LP_CTRL0_RG_TX_ARCA_PULL_DN_LP_SEL, 1)
-DEFINE_BIT(CA_LP_CTRL0_RG_TX_ARCA_PULL_UP_LP_SEL, 2)
-DEFINE_BIT(CA_LP_CTRL0_RG_TX_ARCS_PULL_DN_LP_SEL, 3)
-DEFINE_BIT(CA_LP_CTRL0_RG_ARDMSUS_10_CA_LP_SEL, 4)
-DEFINE_BIT(CA_LP_CTRL0_RG_ARCMD_RESETB_LP_SEL, 8)
-DEFINE_BIT(CA_LP_CTRL0_RG_ARPI_RESETB_CA_LP_SEL, 9)
-DEFINE_BIT(CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL, 12)
-DEFINE_BIT(CA_LP_CTRL0_RG_ARDLL_PHDET_EN_CA_LP_SEL, 13)
-DEFINE_BIT(CA_LP_CTRL0_RG_TX_ARCS_PULL_UP_LP_SEL, 15)
-DEFINE_BIT(CA_LP_CTRL0_RG_RX_ARCMD_BIAS_EN_LP_SEL, 16)
-DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_MCK_CA_LP_SEL, 17)
-DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_CA_LP_SEL, 18)
-DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_MCTL_CA_LP_SEL, 19)
-DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_FB_CA_LP_SEL, 20)
-DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_CS_LP_SEL, 21)
-DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_CLK_LP_SEL, 22)
-DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_CMD_LP_SEL, 23)
-DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_CLKIEN_LP_SEL, 24)
-DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_MPDIV_CG_CA_LP_SEL, 25)
-DEFINE_BIT(CA_LP_CTRL0_RG_RX_ARCMD_VREF_EN_LP_SEL, 26)
-DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_MIDPI_EN_CA_LP_SEL, 27)
-DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_CA_LP_SEL, 28)
-
-/* DDRPHY_REG_MISC_LP_CTRL */
-DEFINE_BIT(MISC_LP_CTRL_RG_ARDMSUS_10, 0)
-DEFINE_BIT(MISC_LP_CTRL_RG_ARDMSUS_10_LP_SEL, 1)
-DEFINE_BIT(MISC_LP_CTRL_RG_RIMP_DMSUS_10, 2)
-DEFINE_BIT(MISC_LP_CTRL_RG_RIMP_DMSUS_10_LP_SEL, 3)
-DEFINE_BIT(MISC_LP_CTRL_RG_RRESETB_LP_SEL, 4)
-DEFINE_BIT(MISC_LP_CTRL_RG_RPHYPLL_RESETB_LP_SEL, 5)
-DEFINE_BIT(MISC_LP_CTRL_RG_RPHYPLL_EN_LP_SEL, 6)
-DEFINE_BIT(MISC_LP_CTRL_RG_RCLRPLL_EN_LP_SEL, 7)
-DEFINE_BIT(MISC_LP_CTRL_RG_RPHYPLL_ADA_MCK8X_EN_LP_SEL, 8)
-DEFINE_BIT(MISC_LP_CTRL_RG_RPHYPLL_AD_MCK8X_EN_LP_SEL, 9)
-DEFINE_BIT(MISC_LP_CTRL_RG_RPHYPLL_TOP_REV_0_LP_SEL, 10)
-DEFINE_BIT(MISC_LP_CTRL_RG_SC_ARPI_RESETB_8X_SEQ_LP_SEL, 11)
-DEFINE_BIT(MISC_LP_CTRL_RG_ADA_MCK8X_8X_SEQ_LP_SEL, 12)
-DEFINE_BIT(MISC_LP_CTRL_RG_AD_MCK8X_8X_SEQ_LP_SEL, 13)
-DEFINE_BIT(MISC_LP_CTRL_RG_MIDPI_EN_8X_SEQ_LP_SEL, 17)
-DEFINE_BIT(MISC_LP_CTRL_RG_MIDPI_CKDIV4_EN_8X_SEQ_LP_SEL, 18)
-DEFINE_BIT(MISC_LP_CTRL_RG_MCK8X_CG_SRC_LP_SEL, 19)
-DEFINE_BIT(MISC_LP_CTRL_RG_MCK8X_CG_SRC_AND_LP_SEL, 20)
-
-/* DDRPHY_REG_MISC_CG_CTRL9 */
-DEFINE_BIT(MISC_CG_CTRL9_RG_M_CK_OPENLOOP_MODE_EN, 4)
-DEFINE_BIT(MISC_CG_CTRL9_RG_MCK4X_I_OPENLOOP_MODE_EN, 8)
-DEFINE_BIT(MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_I_OFF, 9)
-DEFINE_BIT(MISC_CG_CTRL9_RG_DDR400_MCK4X_I_FORCE_ON, 10)
-DEFINE_BIT(MISC_CG_CTRL9_RG_MCK4X_I_FB_CK_CG_OFF, 11)
-DEFINE_BIT(MISC_CG_CTRL9_RG_MCK4X_Q_OPENLOOP_MODE_EN, 12)
-DEFINE_BIT(MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_Q_OFF, 13)
-DEFINE_BIT(MISC_CG_CTRL9_RG_DDR400_MCK4X_Q_FORCE_ON, 14)
-DEFINE_BIT(MISC_CG_CTRL9_RG_MCK4X_Q_FB_CK_CG_OFF, 15)
-DEFINE_BIT(MISC_CG_CTRL9_RG_MCK4X_O_OPENLOOP_MODE_EN, 16)
-DEFINE_BIT(MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_O_OFF, 17)
-DEFINE_BIT(MISC_CG_CTRL9_RG_MCK4X_O_FB_CK_CG_OFF, 19)
-
-/* DDRPHY_REG_MISC_SHU_RX_CG_CTRL */
-DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_DCM_OPT, 0)
-DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT, 1)
-DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_RODT_DCM_OPT, 2)
-DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_DQSIEN_STBCAL_CG_EN, 4)
-DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_DQSIEN_AUTOK_CG_EN, 5)
-DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN, 8)
-DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_DQSIEN_RETRY_CG_EN, 9)
-DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN, 10)
-DEFINE_BITFIELD(MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY, 19, 16)
-DEFINE_BITFIELD(MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY, 23, 20)
-
-/* DDRPHY_REG_MISC_SHU_CG_CTRL0 */
-DEFINE_BITFIELD(MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL, 31, 0)
-
-/* DDRPHY_REG_MISC_IMP_CTRL1 */
-DEFINE_BIT(MISC_IMP_CTRL1_RG_IMP_EN, 1)
-DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_DDR4_SEL, 2)
-DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_DDR3_SEL, 3)
-DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_BIAS_EN, 4)
-DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_ODT_EN, 5)
-DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_PRE_EN, 6)
-DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_VREF_EN, 7)
-DEFINE_BIT(MISC_IMP_CTRL1_IMP_ABN_LAT_CLR, 14)
-DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_SUS_ECO_OPT, 31)
-
-/* DDRPHY_REG_MISC_CG_CTRL0 */
-DEFINE_BIT(MISC_CG_CTRL0_W_CHG_MEM, 0)
-DEFINE_BITFIELD(MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1, 3, 1)
-DEFINE_BITFIELD(MISC_CG_CTRL0_CLK_MEM_SEL, 5, 4)
-DEFINE_BIT(MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT7, 7)
-DEFINE_BIT(MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE, 8)
-DEFINE_BIT(MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE, 9)
-DEFINE_BIT(MISC_CG_CTRL0_RG_CG_PHY_OFF_DISABLE, 10)
-DEFINE_BIT(MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE, 11)
-DEFINE_BIT(MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE, 12)
-DEFINE_BIT(MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE, 13)
-DEFINE_BIT(MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE, 14)
-DEFINE_BIT(MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE, 15)
-DEFINE_BIT(MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE, 16)
-DEFINE_BIT(MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE, 17)
-DEFINE_BIT(MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN, 18)
-DEFINE_BIT(MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE, 19)
-DEFINE_BIT(MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF, 20)
-DEFINE_BIT(MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF, 22)
-DEFINE_BIT(MISC_CG_CTRL0_RG_FREERUN_MCK_CG, 29)
-
-/* DDRPHY_REG_MISC_CKMUX_SEL */
-DEFINE_BIT(MISC_CKMUX_SEL_R_PHYCTRLMUX, 0)
-DEFINE_BIT(MISC_CKMUX_SEL_R_PHYCTRLDCM, 1)
-DEFINE_BIT(MISC_CKMUX_SEL_RG_52M_104M_SEL, 12)
-DEFINE_BITFIELD(MISC_CKMUX_SEL_FMEM_CK_MUX, 19, 18)
-
-/* DDRPHY_REG_PHYPLL2 */
-DEFINE_BIT(PHYPLL2_RG_RPHYPLL_RESETB, 16)
-DEFINE_BIT(PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN, 21)
-DEFINE_BIT(PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN, 22)
-
-/* DDRPHY_REG_PHYPLL0 */
-DEFINE_BIT(PHYPLL0_RG_RPHYPLL_EN, 31)
-
-/* DDRPHY_REG_SHU_B0_DLL_ARPI2 */
-DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0, 10)
-DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0, 11)
-DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0, 13)
-DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0, 14)
-DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0, 15)
-DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0, 17)
-DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0, 19)
-DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0, 27)
-DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0, 31)
-
-/* DDRPHY_REG_SHU_B1_DLL_ARPI2 */
-DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1, 10)
-DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1, 11)
-DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1, 13)
-DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1, 14)
-DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1, 15)
-DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1, 17)
-DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1, 19)
-DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1, 27)
-DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1, 31)
-
-/* DDRPHY_REG_SHU_PLL2 */
-DEFINE_BIT(SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU, 0)
-
-/* DDRPHY_REG_B0_SHU_MIDPI_CTRL */
-DEFINE_BIT(B0_SHU_MIDPI_CTRL_MIDPI_ENABLE_B0, 0)
-DEFINE_BIT(B0_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B0, 1)
-
-/* DDRPHY_REG_B1_SHU_MIDPI_CTRL */
-DEFINE_BIT(B1_SHU_MIDPI_CTRL_MIDPI_ENABLE_B1, 0)
-DEFINE_BIT(B1_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B1, 1)
-
-/* DDRPHY_REG_CA_SHU_MIDPI_CTRL */
-DEFINE_BIT(CA_SHU_MIDPI_CTRL_MIDPI_ENABLE_CA, 0)
-DEFINE_BIT(CA_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_CA, 1)
-
-/* DDRPHY_REG_CA_DLL_ARPI0 */
-DEFINE_BIT(CA_DLL_ARPI0_RG_ARPI_RESETB_CA, 3)
-
-/* DDRPHY_REG_B0_DLL_ARPI0 */
-DEFINE_BIT(B0_DLL_ARPI0_RG_ARPI_RESETB_B0, 3)
-
-/* DDRPHY_REG_B1_DLL_ARPI0 */
-DEFINE_BIT(B1_DLL_ARPI0_RG_ARPI_RESETB_B1, 3)
-
-/* DDRPHY_REG_MISC_CG_CTRL2 */
-DEFINE_BIT(MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 0)
-DEFINE_BITFIELD(MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL, 5, 1)
-DEFINE_BIT(MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON, 6)
-DEFINE_BIT(MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN, 7)
-DEFINE_BIT(MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN, 8)
-DEFINE_BITFIELD(MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT, 15, 9)
-DEFINE_BITFIELD(MISC_CG_CTRL2_RG_MEM_DCM_FSEL, 20, 16)
-DEFINE_BITFIELD(MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL, 25, 21)
-DEFINE_BIT(MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF, 26)
-DEFINE_BIT(MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27, 27)
-DEFINE_BIT(MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE, 28)
-DEFINE_BIT(MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE, 29)
-DEFINE_BIT(MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30, 30)
-DEFINE_BIT(MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE, 31)
-
-/* DDRPHY_REG_MISC_CTRL0 */
-DEFINE_BIT(MISC_CTRL0_R_DMDQSIEN_FIFO_EN, 0)
-DEFINE_BIT(MISC_CTRL0_R_DMSTBEN_SYNCOPT, 2)
-DEFINE_BIT(MISC_CTRL0_R_DMVALID_DLY_OPT, 4)
-DEFINE_BIT(MISC_CTRL0_R_DMVALID_NARROW_IG, 5)
-DEFINE_BITFIELD(MISC_CTRL0_R_DMVALID_DLY, 10, 8)
-DEFINE_BIT(MISC_CTRL0_IMPCAL_CHAB_EN, 12)
-DEFINE_BIT(MISC_CTRL0_IMPCAL_TRACK_DISABLE, 13)
-DEFINE_BIT(MISC_CTRL0_IMPCAL_LP_ECO_OPT, 18)
-DEFINE_BIT(MISC_CTRL0_IMPCAL_CDC_ECO_OPT, 19)
-DEFINE_BIT(MISC_CTRL0_IDLE_DCM_CHB_CDC_ECO_OPT, 20)
-DEFINE_BIT(MISC_CTRL0_R_DMSHU_PHYDCM_FORCEOFF, 27)
-DEFINE_BIT(MISC_CTRL0_R_DQS0IEN_DIV4_CK_CG_CTRL, 28)
-DEFINE_BIT(MISC_CTRL0_R_DQS1IEN_DIV4_CK_CG_CTRL, 29)
-DEFINE_BIT(MISC_CTRL0_R_CLKIEN_DIV4_CK_CG_CTRL, 30)
-DEFINE_BIT(MISC_CTRL0_R_STBENCMP_DIV4CK_EN, 31)
-
-/* DDRPHY_REG_MISC_RXDVS2 */
-DEFINE_BIT(MISC_RXDVS2_R_DMRXDVS_DEPTH_HALF, 0)
-DEFINE_BIT(MISC_RXDVS2_R_DMRXDVS_SHUFFLE_CTRL_CG_IG, 8)
-DEFINE_BIT(MISC_RXDVS2_R_DMRXDVS_DBG_MON_EN, 16)
-DEFINE_BIT(MISC_RXDVS2_R_DMRXDVS_DBG_MON_CLR, 17)
-DEFINE_BIT(MISC_RXDVS2_R_DMRXDVS_DBG_PAUSE_EN, 18)
-
-/* DDRPHY_REG_MISC_DVFS_EMI_CLK */
-DEFINE_BIT(MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY, 24)
-
-/* DDRPHY_REG_B0_DQ10 */
-DEFINE_BIT(B0_DQ10_ARPI_CG_RK1_SRC_SEL_B0, 0)
-
-/* DDRPHY_REG_B1_DQ10 */
-DEFINE_BIT(B1_DQ10_ARPI_CG_RK1_SRC_SEL_B1, 0)
-
-/* DDRPHY_REG_MISC_DVFSCTL */
-DEFINE_BITFIELD(MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW, 3, 0)
-DEFINE_BITFIELD(MISC_DVFSCTL_R_DVFS_PICG_MARGIN2_NEW, 7, 4)
-DEFINE_BITFIELD(MISC_DVFSCTL_R_DVFS_PICG_MARGIN3_NEW, 11, 8)
-DEFINE_BITFIELD(MISC_DVFSCTL_R_DVFS_PICG_MARGIN4_NEW, 15, 12)
-DEFINE_BIT(MISC_DVFSCTL_R_DMSHUFFLE_CHANGE_FREQ_OPT, 18)
-DEFINE_BIT(MISC_DVFSCTL_R_SHUFFLE_PI_RESET_ENABLE, 26)
-DEFINE_BIT(MISC_DVFSCTL_R_DVFS_PICG_POSTPONE, 27)
-DEFINE_BITFIELD(MISC_DVFSCTL_R_DVFS_MCK8X_MARGIN, 31, 28)
-
-/* DDRPHY_REG_MISC_STBCAL1 */
-DEFINE_BIT(MISC_STBCAL1_STBCNT_SHU_RST_EN, 0)
-DEFINE_BIT(MISC_STBCAL1_DIS_PI_TRACK_AS_NOT_RD, 2)
-DEFINE_BIT(MISC_STBCAL1_STBCNT_MODESEL, 4)
-DEFINE_BIT(MISC_STBCAL1_DQSIEN_7UI_EN, 5)
-DEFINE_BIT(MISC_STBCAL1_STB_SHIFT_DTCOUT_IG, 6)
-DEFINE_BIT(MISC_STBCAL1_STB_FLAGCLR_OPT, 8)
-DEFINE_BIT(MISC_STBCAL1_STBCNT_SW_RST, 15)
-DEFINE_BITFIELD(MISC_STBCAL1_STBCAL_FILTER, 31, 16)
-
-/* DDRPHY_REG_MISC_STBCAL2 */
-DEFINE_BIT(MISC_STBCAL2_STB_PIDLYCG_IG, 0)
-DEFINE_BIT(MISC_STBCAL2_STB_UIDLYCG_IG, 1)
-DEFINE_BITFIELD(MISC_STBCAL2_STB_DBG_EN, 7, 4)
-DEFINE_BIT(MISC_STBCAL2_STB_DBG_CG_AO, 8)
-DEFINE_BIT(MISC_STBCAL2_STB_DBG_UIPI_UPD_OPT, 9)
-DEFINE_BIT(MISC_STBCAL2_DQSGCNT_BYP_REF, 10)
-DEFINE_BIT(MISC_STBCAL2_STB_PICG_EARLY_1T_EN, 16)
-DEFINE_BIT(MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN, 17)
-DEFINE_BIT(MISC_STBCAL2_STB_IG_XRANK_CG_RST, 18)
-DEFINE_BIT(MISC_STBCAL2_STB_RST_BY_RANK, 19)
-DEFINE_BIT(MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN, 20)
-DEFINE_BIT(MISC_STBCAL2_STB_GERRSTOP, 28)
-DEFINE_BIT(MISC_STBCAL2_STB_GERR_RST, 29)
-DEFINE_BIT(MISC_STBCAL2_STB_GERR_B01, 30)
-DEFINE_BIT(MISC_STBCAL2_STB_GERR_B23, 31)
-
-/* DDRPHY_REG_MISC_SHU_STBCAL */
-DEFINE_BITFIELD(MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE, 13, 12)
-DEFINE_BIT(MISC_SHU_STBCAL_DQSIEN_BURST_MODE, 14)
-DEFINE_BIT(MISC_SHU_STBCAL_STBCALEN, 16)
-DEFINE_BIT(MISC_SHU_STBCAL_STB_SELPHCALEN, 17)
-
-/* DDRPHY_REG_MISC_STBCAL */
-DEFINE_BIT(MISC_STBCAL_PIMASK_RKCHG_OPT, 0)
-DEFINE_BIT(MISC_STBCAL_STBDLELAST_OPT, 4)
-DEFINE_BITFIELD(MISC_STBCAL_STBDLELAST_PULSE, 11, 8)
-DEFINE_BIT(MISC_STBCAL_STBDLELAST_FILTER, 12)
-DEFINE_BIT(MISC_STBCAL_STBSTATE_OPT, 15)
-DEFINE_BIT(MISC_STBCAL_PHYVALID_IG, 16)
-DEFINE_BIT(MISC_STBCAL_SREF_DQSGUPD, 17)
-DEFINE_BIT(MISC_STBCAL_RKCHGMASKDIS, 19)
-DEFINE_BIT(MISC_STBCAL_PICGEN, 20)
-DEFINE_BIT(MISC_STBCAL_REFUICHG, 21)
-DEFINE_BIT(MISC_STBCAL_STBCAL2R, 23)
-DEFINE_BIT(MISC_STBCAL_PICHGBLOCK_NORD, 26)
-DEFINE_BIT(MISC_STBCAL_STB_DQIEN_IG, 27)
-DEFINE_BIT(MISC_STBCAL_DQSIENCG_CHG_EN, 28)
-DEFINE_BIT(MISC_STBCAL_DQSIENCG_NORMAL_EN, 29)
-DEFINE_BIT(MISC_STBCAL_DQSIENMODE, 31)
-
-/* DDRPHY_REG_B0_PHY2 */
-DEFINE_BITFIELD(B0_PHY2_RG_RX_ARDQS_JM_SEL_B0, 7, 4)
-DEFINE_BIT(B0_PHY2_RG_RX_ARDQS_JM_EN_B0, 8)
-DEFINE_BITFIELD(B0_PHY2_RG_RX_ARDQS_JM_DLY_B0, 24, 16)
-DEFINE_BIT(B0_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B0, 28)
-
-/* DDRPHY_REG_B1_PHY2 */
-DEFINE_BITFIELD(B1_PHY2_RG_RX_ARDQS_JM_SEL_B1, 7, 4)
-DEFINE_BIT(B1_PHY2_RG_RX_ARDQS_JM_EN_B1, 8)
-DEFINE_BITFIELD(B1_PHY2_RG_RX_ARDQS_JM_DLY_B1, 24, 16)
-DEFINE_BIT(B1_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B1, 28)
-
-/* DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL */
-DEFINE_BIT(MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT, 0)
-DEFINE_BIT(MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_4BYTE_EN, 1)
-DEFINE_BITFIELD(MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN, 11, 8)
-DEFINE_BITFIELD(MISC_RX_IN_GATE_EN_CTRL_DIS_IN_GATE_EN, 15, 12)
-
-/* DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL */
-DEFINE_BIT(MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT, 0)
-DEFINE_BIT(MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_4BYTE_EN, 1)
-DEFINE_BITFIELD(MISC_RX_IN_BUFF_EN_CTRL_FIX_IN_BUFF_EN, 11, 8)
-DEFINE_BITFIELD(MISC_RX_IN_BUFF_EN_CTRL_DIS_IN_BUFF_EN, 15, 12)
-
-/* DDRPHY_REG_B0_RXDVS0 */
-DEFINE_BIT(B0_RXDVS0_R_RX_RANKINSEL_B0, 0)
-DEFINE_BITFIELD(B0_RXDVS0_R_RX_RANKINCTL_B0, 7, 4)
-DEFINE_BIT(B0_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B0, 9)
-DEFINE_BIT(B0_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B0, 19)
-DEFINE_BIT(B0_RXDVS0_R_HWRESTORE_ENA_B0, 22)
-DEFINE_BIT(B0_RXDVS0_R_HWSAVE_MODE_ENA_B0, 24)
-DEFINE_BIT(B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0, 28)
-DEFINE_BIT(B0_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B0, 29)
-DEFINE_BIT(B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0, 31)
-
-/* DDRPHY_REG_B1_RXDVS0 */
-DEFINE_BIT(B1_RXDVS0_R_RX_RANKINSEL_B1, 0)
-DEFINE_BITFIELD(B1_RXDVS0_R_RX_RANKINCTL_B1, 7, 4)
-DEFINE_BIT(B1_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B1, 9)
-DEFINE_BIT(B1_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B1, 19)
-DEFINE_BIT(B1_RXDVS0_R_HWRESTORE_ENA_B1, 22)
-DEFINE_BIT(B1_RXDVS0_R_HWSAVE_MODE_ENA_B1, 24)
-DEFINE_BIT(B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1, 28)
-DEFINE_BIT(B1_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B1, 29)
-DEFINE_BIT(B1_RXDVS0_R_RX_DLY_TRACK_ENA_B1, 31)
-
-/* DDRPHY_REG_RK_B0_RXDVS3 */
-DEFINE_BITFIELD(RK_B0_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B0, 7, 0)
-DEFINE_BITFIELD(RK_B0_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B0, 15, 8)
-
-/* DDRPHY_REG_RK_B0_RXDVS4 */
-DEFINE_BITFIELD(RK_B0_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B0, 8, 0)
-DEFINE_BITFIELD(RK_B0_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B0, 24, 16)
-
-/* DDRPHY_REG_RK_B0_RXDVS2 */
-DEFINE_BITFIELD(RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B0, 17, 16)
-DEFINE_BITFIELD(RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B0, 19, 18)
-DEFINE_BIT(RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0, 23)
-DEFINE_BITFIELD(RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B0, 25, 24)
-DEFINE_BITFIELD(RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B0, 27, 26)
-DEFINE_BIT(RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0, 28)
-DEFINE_BIT(RK_B0_RXDVS2_R_RK0_DVS_FDLY_MODE_B0, 29)
-DEFINE_BITFIELD(RK_B0_RXDVS2_R_RK0_DVS_MODE_B0, 31, 30)
-
-/* DDRPHY_REG_RK_B0_RXDVS1 */
-DEFINE_BITFIELD(RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LAG, 15, 0)
-DEFINE_BITFIELD(RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LEAD, 31, 16)
-
-/* DDRPHY_REG_RK_B1_RXDVS3 */
-DEFINE_BITFIELD(RK_B1_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B1, 7, 0)
-DEFINE_BITFIELD(RK_B1_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B1, 15, 8)
-
-/* DDRPHY_REG_RK_B1_RXDVS4 */
-DEFINE_BITFIELD(RK_B1_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B1, 8, 0)
-DEFINE_BITFIELD(RK_B1_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B1, 24, 16)
-
-/* DDRPHY_REG_RK_B1_RXDVS2 */
-DEFINE_BITFIELD(RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B1, 17, 16)
-DEFINE_BITFIELD(RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B1, 19, 18)
-DEFINE_BIT(RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1, 23)
-DEFINE_BITFIELD(RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B1, 25, 24)
-DEFINE_BITFIELD(RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B1, 27, 26)
-DEFINE_BIT(RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1, 28)
-DEFINE_BIT(RK_B1_RXDVS2_R_RK0_DVS_FDLY_MODE_B1, 29)
-DEFINE_BITFIELD(RK_B1_RXDVS2_R_RK0_DVS_MODE_B1, 31, 30)
-
-/* DDRPHY_REG_RK_B1_RXDVS1 */
-DEFINE_BITFIELD(RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LAG, 15, 0)
-DEFINE_BITFIELD(RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LEAD, 31, 16)
-
-/* DDRPHY_REG_MISC_CG_CTRL1 */
-DEFINE_BITFIELD(MISC_CG_CTRL1_R_DVS_DIV4_CG_CTRL, 31, 0)
-
-/* DDRPHY_REG_B0_RXDVS1 */
-DEFINE_BIT(B0_RXDVS1_F_LEADLAG_TRACK_B0, 15)
-DEFINE_BIT(B0_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B0, 17)
-
-/* DDRPHY_REG_B1_RXDVS1 */
-DEFINE_BIT(B1_RXDVS1_F_LEADLAG_TRACK_B1, 15)
-DEFINE_BIT(B1_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B1, 17)
-
-/* DRAMC_REG_DLLFRZ_CTRL */
-DEFINE_BIT(DLLFRZ_CTRL_INPUTRXTRACK_BLOCK, 0)
-DEFINE_BIT(DLLFRZ_CTRL_DLLFRZ_MON_PBREF_OPT, 1)
-DEFINE_BIT(DLLFRZ_CTRL_DLLFRZ_BLOCKLONG, 2)
-DEFINE_BIT(DLLFRZ_CTRL_DLLFRZ, 7)
-DEFINE_BIT(DLLFRZ_CTRL_UPDBYWR, 8)
-
-/* DDRPHY_REG_MISC_RG_DFS_CTRL */
-DEFINE_BIT(MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL, 0)
-DEFINE_BIT(MISC_RG_DFS_CTRL_RG_DPY_RXDLY_TRACK_EN, 2)
-DEFINE_BITFIELD(MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM, 7, 4)
-DEFINE_BIT(MISC_RG_DFS_CTRL_RG_DR_SRAM_RESTORE, 8)
-DEFINE_BIT(MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM_LATCH, 9)
-DEFINE_BIT(MISC_RG_DFS_CTRL_RG_DR_SRAM_LOAD, 10)
-DEFINE_BITFIELD(MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL, 17, 16)
-DEFINE_BIT(MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN, 18)
-DEFINE_BIT(MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN, 19)
-DEFINE_BIT(MISC_RG_DFS_CTRL_RG_DR_SHU_EN, 23)
-DEFINE_BIT(MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN, 24)
-
-/* DDRPHY_REG_MISC_CTRL4 */
-DEFINE_BIT(MISC_CTRL4_R_OPT2_MPDIV_CG, 0)
-DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_MCK, 1)
-DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_DQM, 2)
-DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_DQS, 3)
-DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_DQ, 4)
-DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_DQSIEN, 5)
-DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_CMD, 6)
-DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_CLK, 7)
-DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_CS, 8)
-
-/* DDRPHY_REG_MISC_CTRL3 */
-DEFINE_BITFIELD(MISC_CTRL3_ARPI_CG_CMD_OPT, 1, 0)
-DEFINE_BITFIELD(MISC_CTRL3_ARPI_CG_CLK_OPT, 3, 2)
-DEFINE_BIT(MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT, 4)
-DEFINE_BIT(MISC_CTRL3_ARPI_CG_MCK_CA_OPT, 5)
-DEFINE_BIT(MISC_CTRL3_ARPI_CG_MCTL_CA_OPT, 6)
-DEFINE_BITFIELD(MISC_CTRL3_ARPI_CG_DQ_OPT, 17, 16)
-DEFINE_BITFIELD(MISC_CTRL3_ARPI_CG_DQS_OPT, 19, 18)
-DEFINE_BIT(MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT, 20)
-DEFINE_BIT(MISC_CTRL3_ARPI_CG_MCK_DQ_OPT, 21)
-DEFINE_BIT(MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT, 22)
-DEFINE_BIT(MISC_CTRL3_R_DDRPHY_COMB_CG_IG, 26)
-DEFINE_BIT(MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG, 27)
-
-/* DDRPHY_REG_MISC_CG_CTRL5 */
-DEFINE_BIT(MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN, 16)
-DEFINE_BIT(MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN, 17)
-DEFINE_BIT(MISC_CG_CTRL5_R_CA_DLY_DCM_EN, 18)
-DEFINE_BIT(MISC_CG_CTRL5_R_DQ1_PI_DCM_EN, 20)
-DEFINE_BIT(MISC_CG_CTRL5_R_DQ0_PI_DCM_EN, 21)
-DEFINE_BIT(MISC_CG_CTRL5_R_CA_PI_DCM_EN, 22)
-
-/* DRAMC_REG_RX_CG_SET0 */
-DEFINE_BIT(RX_CG_SET0_RDATCKAR, 30)
-DEFINE_BIT(RX_CG_SET0_RDYCKAR, 31)
-
-/* DRAMC_REG_SREF_DPD_CTRL */
-DEFINE_BIT(SREF_DPD_CTRL_LPSM_BYPASS_B, 7)
-DEFINE_BIT(SREF_DPD_CTRL_CLR_EN, 9)
-DEFINE_BIT(SREF_DPD_CTRL_SELFREF_AUTOSAVE_EN, 10)
-DEFINE_BIT(SREF_DPD_CTRL_SREF_PRD_OPT, 11)
-DEFINE_BIT(SREF_DPD_CTRL_SREF_CG_OPT, 12)
-DEFINE_BIT(SREF_DPD_CTRL_SRFPD_DIS, 13)
-DEFINE_BITFIELD(SREF_DPD_CTRL_SREFDLY, 19, 16)
-DEFINE_BIT(SREF_DPD_CTRL_SREF_HW_EN, 22)
-DEFINE_BIT(SREF_DPD_CTRL_CMDCKAR, 26)
-DEFINE_BIT(SREF_DPD_CTRL_GT_SYNC_MASK, 29)
-DEFINE_BIT(SREF_DPD_CTRL_DAT_SYNC_MASK, 30)
-DEFINE_BIT(SREF_DPD_CTRL_PHY_SYNC_MASK, 31)
-
-/* DRAMC_REG_DCM_CTRL0 */
-DEFINE_BIT(DCM_CTRL0_BCLKAR, 2)
-
-/* DRAMC_REG_TX_CG_SET0 */
-DEFINE_BIT(TX_CG_SET0_SELPH_4LCG_DIS, 0)
-DEFINE_BIT(TX_CG_SET0_SELPH_CG_DIS, 1)
-DEFINE_BIT(TX_CG_SET0_DWCLKRUN, 2)
-DEFINE_BIT(TX_CG_SET0_WDATA_CG_DIS, 3)
-DEFINE_BIT(TX_CG_SET0_TX_ATK_CLKRUN, 4)
-DEFINE_BIT(TX_CG_SET0_PSELAR, 31)
-
-/* DRAMC_REG_SCSMCTRL_CG */
-DEFINE_BIT(SCSMCTRL_CG_SCARB_SM_CGAR, 30)
-DEFINE_BIT(SCSMCTRL_CG_SCSM_CGAR, 31)
-
-/* DRAMC_REG_TX_TRACKING_SET0 */
-DEFINE_BIT(TX_TRACKING_SET0_TX_TRACKING_OPT, 15)
-DEFINE_BIT(TX_TRACKING_SET0_SW_UP_TX_NOW_CASE, 16)
-DEFINE_BIT(TX_TRACKING_SET0_TXUIPI_CAL_CGAR, 17)
-DEFINE_BIT(TX_TRACKING_SET0_SHU_PRELOAD_TX_START, 18)
-DEFINE_BIT(TX_TRACKING_SET0_SHU_PRELOAD_TX_HW, 19)
-DEFINE_BIT(TX_TRACKING_SET0_HMRRSEL_CGAR, 21)
-DEFINE_BIT(TX_TRACKING_SET0_RDDQSOSC_CGAR, 22)
-
-/* DRAMC_REG_ZQ_SET0 */
-DEFINE_BITFIELD(ZQ_SET0_ZQCSOP, 7, 0)
-DEFINE_BITFIELD(ZQ_SET0_ZQCSAD, 15, 8)
-DEFINE_BITFIELD(ZQ_SET0_ZQCS_MASK_SEL, 18, 16)
-DEFINE_BIT(ZQ_SET0_ZQCS_MASK_SEL_CGAR, 19)
-DEFINE_BIT(ZQ_SET0_ZQMASK_CGAR, 20)
-DEFINE_BIT(ZQ_SET0_ZQCSMASK_OPT, 21)
-DEFINE_BIT(ZQ_SET0_ZQCSMASK, 29)
-DEFINE_BIT(ZQ_SET0_ZQCSDUAL, 30)
-
-/* DRAMC_REG_ACTIMING_CTRL */
-DEFINE_BIT(ACTIMING_CTRL_SEQCLKRUN3, 0)
-DEFINE_BIT(ACTIMING_CTRL_SEQCLKRUN2, 1)
-DEFINE_BIT(ACTIMING_CTRL_SEQCLKRUN, 2)
-DEFINE_BIT(ACTIMING_CTRL_REFNA_OPT, 6)
-DEFINE_BIT(ACTIMING_CTRL_REFBW_FREN, 8)
-DEFINE_BIT(ACTIMING_CTRL_CLKWITRFC, 9)
-DEFINE_BIT(ACTIMING_CTRL_TMRRICHKDIS, 21)
-DEFINE_BIT(ACTIMING_CTRL_TMRRIBYRK_DIS, 22)
-DEFINE_BIT(ACTIMING_CTRL_MRRIOPT, 23)
-DEFINE_BIT(ACTIMING_CTRL_FASTW2R, 24)
-
-/* DRAMC_REG_CLKAR */
-DEFINE_BITFIELD(CLKAR_REQQUE_PACG_DIS, 14, 0)
-DEFINE_BIT(CLKAR_DCMREF_OPT, 24)
-DEFINE_BIT(CLKAR_REQQUECLKRUN, 27)
-
-/* DRAMC_REG_DRAMC_PD_CTRL */
-DEFINE_BIT(DRAMC_PD_CTRL_DCMEN, 0)
-DEFINE_BIT(DRAMC_PD_CTRL_DCMEN2, 1)
-DEFINE_BIT(DRAMC_PD_CTRL_DCMENNOTRFC, 2)
-DEFINE_BIT(DRAMC_PD_CTRL_PHYGLUECLKRUN, 3)
-DEFINE_BIT(DRAMC_PD_CTRL_COMBPHY_CLKENSAME, 5)
-DEFINE_BIT(DRAMC_PD_CTRL_MIOCKCTRLOFF, 6)
-DEFINE_BIT(DRAMC_PD_CTRL_PG_DCM_OPT, 9)
-DEFINE_BIT(DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 12)
-DEFINE_BIT(DRAMC_PD_CTRL_TCKFIXON, 13)
-DEFINE_BIT(DRAMC_PD_CTRL_PHYCLKDYNGEN, 30)
-DEFINE_BIT(DRAMC_PD_CTRL_COMBCLKCTRL, 31)
-
-/* DRAMC_REG_TEST2_A3 */
-DEFINE_BIT(TEST2_A3_ADRDECEN_TARKMODE, 5)
-DEFINE_BIT(TEST2_A3_TESTAUDPAT, 7)
-DEFINE_BIT(TEST2_A3_TESTCLKRUN, 8)
-DEFINE_BIT(TEST2_A3_PAT_SHIFT_SW_EN, 11)
-DEFINE_BIT(TEST2_A3_TEST2_PAT_SHIFT, 15)
-DEFINE_BIT(TEST2_A3_TEST_AID_EN, 16)
-DEFINE_BIT(TEST2_A3_HFIDPAT, 17)
-DEFINE_BIT(TEST2_A3_AUTO_GEN_PAT, 18)
-DEFINE_BIT(TEST2_A3_TEST2WREN2_HW_EN, 28)
-DEFINE_BIT(TEST2_A3_TEST1, 29)
-DEFINE_BIT(TEST2_A3_TEST2R, 30)
-DEFINE_BIT(TEST2_A3_TEST2W, 31)
-
-/* DRAMC_REG_DVFS_CTRL0 */
-DEFINE_BIT(DVFS_CTRL0_R_DRAMC_CHA, 0)
-DEFINE_BIT(DVFS_CTRL0_SHU_PHYRST_SEL, 1)
-DEFINE_BIT(DVFS_CTRL0_R_DVFS_SREF_OPT, 5)
-DEFINE_BIT(DVFS_CTRL0_HWSET_WLRL, 8)
-DEFINE_BIT(DVFS_CTRL0_MR13_SHU_EN, 9)
-DEFINE_BIT(DVFS_CTRL0_VRCG_EN, 10)
-DEFINE_BIT(DVFS_CTRL0_DVFS_RXFIFOST_SKIP, 13)
-DEFINE_BIT(DVFS_CTRL0_DVFS_NOQUEFLUSH_EN, 15)
-DEFINE_BIT(DVFS_CTRL0_DVFS_CKE_OPT, 16)
-DEFINE_BIT(DVFS_CTRL0_DVFS_CG_OPT, 19)
-DEFINE_BIT(DVFS_CTRL0_SCARB_PRI_OPT, 20)
-DEFINE_BIT(DVFS_CTRL0_R_DMDVFSMRW_EN, 21)
-DEFINE_BIT(DVFS_CTRL0_MRWWOPRA, 22)
-DEFINE_BIT(DVFS_CTRL0_DVFS_SYNC_MASK, 27)
-
-/* DDRPHY_REG_MISC_DUTYSCAN1 */
-DEFINE_BIT(MISC_DUTYSCAN1_REG_SW_RST, 0)
-DEFINE_BIT(MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 1)
-DEFINE_BIT(MISC_DUTYSCAN1_RX_MIOCK_JIT_EN, 2)
-DEFINE_BIT(MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN, 3)
-DEFINE_BIT(MISC_DUTYSCAN1_EYESCAN_DQ_SYNC_EN, 8)
-DEFINE_BIT(MISC_DUTYSCAN1_EYESCAN_NEW_DQ_SYNC_EN, 9)
-DEFINE_BIT(MISC_DUTYSCAN1_EYESCAN_DQS_SYNC_EN, 10)
-DEFINE_BIT(MISC_DUTYSCAN1_EYESCAN_DQS_OPT, 11)
-DEFINE_BIT(MISC_DUTYSCAN1_DQSERRCNT_DIS, 14)
-
-/* DDRPHY_REG_SHU_B0_DQ8 */
-DEFINE_BITFIELD(SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0, 14, 0)
-DEFINE_BIT(SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0, 15)
-DEFINE_BIT(SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 19)
-DEFINE_BIT(SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 20)
-DEFINE_BIT(SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 21)
-DEFINE_BIT(SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 22)
-DEFINE_BIT(SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 23)
-DEFINE_BIT(SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 24)
-DEFINE_BIT(SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 26)
-DEFINE_BIT(SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 27)
-DEFINE_BIT(SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 28)
-DEFINE_BIT(SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 29)
-DEFINE_BIT(SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 30)
-DEFINE_BIT(SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 31)
-
-/* DDRPHY_REG_SHU_B1_DQ8 */
-DEFINE_BITFIELD(SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1, 14, 0)
-DEFINE_BIT(SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1, 15)
-DEFINE_BIT(SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 19)
-DEFINE_BIT(SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 20)
-DEFINE_BIT(SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 21)
-DEFINE_BIT(SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 22)
-DEFINE_BIT(SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 23)
-DEFINE_BIT(SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 24)
-DEFINE_BIT(SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 26)
-DEFINE_BIT(SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 27)
-DEFINE_BIT(SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 28)
-DEFINE_BIT(SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 29)
-DEFINE_BIT(SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 30)
-DEFINE_BIT(SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 31)
-
-/* DRAMC_REG_DDRCOMMON0 */
-DEFINE_BIT(DDRCOMMON0_DISSTOP26M, 0)
-DEFINE_BIT(DDRCOMMON0_TRCDEARLY, 3)
-DEFINE_BIT(DDRCOMMON0_BK8EN, 8)
-DEFINE_BIT(DDRCOMMON0_LPDDR4EN, 19)
-DEFINE_BIT(DDRCOMMON0_LPDDR5EN, 20)
-
-/* DRAMC_REG_RX_SET0 */
-DEFINE_BIT(RX_SET0_RDATRST, 0)
-DEFINE_BIT(RX_SET0_PRE_DLE_VLD_OPT, 1)
-DEFINE_BITFIELD(RX_SET0_DATLAT_PDLE_TH, 4, 2)
-DEFINE_BIT(RX_SET0_SMRR_UPD_OLD, 6)
-DEFINE_BIT(RX_SET0_DM4TO1MODE, 31)
-
-/* DRAMC_REG_REFCTRL0 */
-DEFINE_BITFIELD(REFCTRL0_PBREF_BK_REFA_NUM, 2, 0)
-DEFINE_BIT(REFCTRL0_PBREF_BK_REFA_ENA, 3)
-DEFINE_BIT(REFCTRL0_DMPGVLD_IG, 8)
-DEFINE_BIT(REFCTRL0_KEEP_PBREF_OPT, 9)
-DEFINE_BIT(REFCTRL0_KEEP_PBREF, 10)
-DEFINE_BITFIELD(REFCTRL0_DISBYREFNUM, 14, 12)
-DEFINE_BIT(REFCTRL0_PBREF_DISBYREFNUM, 16)
-DEFINE_BIT(REFCTRL0_PBREF_DISBYRATE, 17)
-DEFINE_BITFIELD(REFCTRL0_REF_PREGATE_CNT, 27, 24)
-DEFINE_BIT(REFCTRL0_REFDIS, 29)
-
-/* DRAMC_REG_REFCTRL1 */
-DEFINE_BIT(REFCTRL1_PB2AB_OPT, 0)
-DEFINE_BIT(REFCTRL1_REFPENDINGINT_OPT1, 3)
-DEFINE_BIT(REFCTRL1_REF_QUE_AUTOSAVE_EN, 5)
-DEFINE_BIT(REFCTRL1_REFPEND_OPT1, 6)
-DEFINE_BIT(REFCTRL1_REFPEND_OPT2, 7)
-DEFINE_BIT(REFCTRL1_REFPB2AB_IGZQCS, 8)
-DEFINE_BIT(REFCTRL1_REFRATE_MON_CLR, 11)
-DEFINE_BIT(REFCTRL1_REF_OVERHEAD_PBR2PB_ENA, 13)
-DEFINE_BIT(REFCTRL1_REF_OVERHEAD_RATE_REFAL_ENA, 14)
-DEFINE_BIT(REFCTRL1_REF_OVERHEAD_RATE_REFPB_ENA, 15)
-DEFINE_BIT(REFCTRL1_REF_OVERHEAD_SLOW_REFAL_ENA, 24)
-DEFINE_BIT(REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA, 25)
-DEFINE_BIT(REFCTRL1_REF_OVERHEAD_ALL_REFAL_ENA, 26)
-DEFINE_BIT(REFCTRL1_REF_OVERHEAD_ALL_REFPB_ENA, 27)
-
-/* DRAMC_REG_REFCTRL2 */
-DEFINE_BITFIELD(REFCTRL2_MR4INT_TH, 4, 0)
-DEFINE_BITFIELD(REFCTRL2_REF_OVERHEAD_RATE, 31, 16)
-
-/* DRAMC_REG_DRAMCTRL */
-DEFINE_BIT(DRAMCTRL_CTOREQ_HPRI_OPT, 0)
-DEFINE_BIT(DRAMCTRL_ADRDECEN, 2)
-DEFINE_BIT(DRAMCTRL_ADRBIT3DEC, 3)
-DEFINE_BIT(DRAMCTRL_ALL_BLOCK_CTO_ALE_DBG_EN, 8)
-DEFINE_BIT(DRAMCTRL_SELFREF_BLOCK_CTO_ALE_DBG_EN, 9)
-DEFINE_BIT(DRAMCTRL_DVFS_BLOCK_CTO_ALE_DBG_EN, 10)
-DEFINE_BIT(DRAMCTRL_AG0MWR, 12)
-DEFINE_BIT(DRAMCTRL_DYNMWREN, 13)
-DEFINE_BIT(DRAMCTRL_PREALL_OPTION, 19)
-DEFINE_BIT(DRAMCTRL_REQQUE_THD_EN, 26)
-DEFINE_BIT(DRAMCTRL_SHORTQ_OPT, 31)
-
-/* DRAMC_REG_ARBCTL */
-DEFINE_BITFIELD(ARBCTL_MAXPENDCNT, 7, 0)
-DEFINE_BIT(ARBCTL_WDATACNTDIS, 9)
-
-/* DRAMC_REG_DRAM_CLK_CTRL */
-DEFINE_BIT(DRAM_CLK_CTRL_CLK_EN, 0)
-
-/* DRAMC_REG_RKCFG */
-DEFINE_BIT(RKCFG_MRS2RK, 10)
-DEFINE_BIT(RKCFG_CKE2RANK, 12)
-
-/* DRAMC_REG_CKECTRL */
-DEFINE_BIT(CKECTRL_CKE2RANK_OPT3, 1)
-DEFINE_BIT(CKECTRL_CKE1FIXON, 4)
-DEFINE_BIT(CKECTRL_CKE1FIXOFF, 5)
-DEFINE_BIT(CKECTRL_CKEFIXON, 6)
-DEFINE_BIT(CKECTRL_CKEFIXOFF, 7)
-DEFINE_BIT(CKECTRL_CKE2RANK_OPT5, 8)
-DEFINE_BIT(CKECTRL_CKE2RANK_OPT6, 9)
-DEFINE_BIT(CKECTRL_CKE2RANK_OPT7, 10)
-DEFINE_BIT(CKECTRL_CKE2RANK_OPT8, 11)
-DEFINE_BIT(CKECTRL_CKETIMER_SEL, 13)
-DEFINE_BIT(CKECTRL_FASTWAKE_SEL, 14)
-DEFINE_BIT(CKECTRL_CKEWAKE_SEL, 15)
-DEFINE_BIT(CKECTRL_CKEPBDIS, 22)
-DEFINE_BIT(CKECTRL_CKELCKFIX, 23)
-DEFINE_BIT(CKECTRL_CKE2RANK_OPT2, 24)
-DEFINE_BIT(CKECTRL_CKE2RANK_OPT, 25)
-DEFINE_BIT(CKECTRL_RUNTIMEMRRCKEFIX, 27)
-DEFINE_BIT(CKECTRL_RUNTIMEMRRMIODIS, 28)
-DEFINE_BIT(CKECTRL_CKEON, 31)
-
-/* DRAMC_REG_SCHEDULER_COM */
-DEFINE_BIT(SCHEDULER_COM_RWOFOEN, 0)
-DEFINE_BIT(SCHEDULER_COM_RWHPRICTL, 4)
-DEFINE_BIT(SCHEDULER_COM_RWSPLIT, 5)
-DEFINE_BIT(SCHEDULER_COM_MWHPRIEN, 6)
-DEFINE_BIT(SCHEDULER_COM_DISRDPHASE1, 8)
-DEFINE_BIT(SCHEDULER_COM_PBR2PBR_OPT, 9)
-
-/* DRAMC_REG_PERFCTL0 */
-DEFINE_BIT(PERFCTL0_EBG_EN, 0)
-DEFINE_BIT(PERFCTL0_RWHPRIEN, 8)
-DEFINE_BIT(PERFCTL0_RWLLATEN, 9)
-DEFINE_BIT(PERFCTL0_RWAGEEN, 10)
-DEFINE_BIT(PERFCTL0_EMILLATEN, 11)
-DEFINE_BIT(PERFCTL0_WFLUSHEN, 14)
-DEFINE_BIT(PERFCTL0_REORDER_MODE, 18)
-DEFINE_BIT(PERFCTL0_REORDEREN, 19)
-
-/* DRAMC_REG_HW_MRR_FUN */
-DEFINE_BIT(HW_MRR_FUN_TMRR_ENA, 0)
-DEFINE_BIT(HW_MRR_FUN_TRCDMRR_EN, 1)
-DEFINE_BIT(HW_MRR_FUN_TRPMRR_EN, 2)
-DEFINE_BIT(HW_MRR_FUN_MANTMRR_EN, 3)
-DEFINE_BIT(HW_MRR_FUN_TR2MRR_ENA, 4)
-DEFINE_BIT(HW_MRR_FUN_R2MRRHPRICTL, 5)
-DEFINE_BIT(HW_MRR_FUN_MRR_HW_HIPRI, 11)
-
-/* DRAMC_REG_MPC_OPTION */
-DEFINE_BIT(MPC_OPTION_MPCRKEN, 17)
-
-/* DRAMC_REG_MPC_CTRL */
-DEFINE_BIT(MPC_CTRL_MPC_BLOCKALE_OPT, 0)
-DEFINE_BIT(MPC_CTRL_MPC_BLOCKALE_OPT1, 1)
-DEFINE_BIT(MPC_CTRL_MPC_BLOCKALE_OPT2, 2)
-DEFINE_BIT(MPC_CTRL_ZQ_BLOCKALE_OPT, 3)
-DEFINE_BIT(MPC_CTRL_REFR_BLOCKEN, 5)
-DEFINE_BIT(MPC_CTRL_RTMRW_HPRI_EN, 6)
-DEFINE_BIT(MPC_CTRL_RTSWCMD_HPRI_EN, 7)
-
-/* DRAMC_REG_HMR4 */
-DEFINE_BIT(HMR4_HMR4_TOG_OPT, 1)
-DEFINE_BIT(HMR4_SPDR_MR4_OPT, 2)
-DEFINE_BIT(HMR4_HMR4_BYTEMODE_EN, 5)
-DEFINE_BIT(HMR4_MR4INT_LIMITEN, 6)
-DEFINE_BIT(HMR4_REFR_PERIOD_OPT, 7)
-DEFINE_BIT(HMR4_REFRDIS, 8)
-DEFINE_BIT(HMR4_REFRCNT_OPT, 9)
-
-/* DRAMC_REG_RK_TEST2_A1 */
-DEFINE_BITFIELD(RK_TEST2_A1_TEST2_BASE, 31, 3)
-
-/* DRAMC_REG_TEST2_A2 */
-DEFINE_BITFIELD(TEST2_A2_TEST2_OFF, 31, 4)
-
-/* DRAMC_REG_TEST2_A4 */
-DEFINE_BITFIELD(TEST2_A4_TESTAUDINC, 4, 0)
-DEFINE_BIT(TEST2_A4_TESTSSOPAT, 6)
-DEFINE_BIT(TEST2_A4_TESTSSOXTALKPAT, 7)
-DEFINE_BITFIELD(TEST2_A4_TESTAUDINIT, 12, 8)
-DEFINE_BIT(TEST2_A4_TESTAUDBITINV, 14)
-DEFINE_BIT(TEST2_A4_TESTAUDMODE, 15)
-DEFINE_BIT(TEST2_A4_TESTXTALKPAT, 16)
-DEFINE_BIT(TEST2_A4_TEST_REQ_LEN1, 17)
-DEFINE_BITFIELD(TEST2_A4_TESTAGENTRK, 25, 24)
-DEFINE_BITFIELD(TEST2_A4_TESTAGENTRKSEL, 30, 28)
-
-/* DRAMC_REG_CMD_DEC_CTRL0 */
-DEFINE_BIT(CMD_DEC_CTRL0_SELPH_CMD_CG_DIS, 4)
-DEFINE_BITFIELD(CMD_DEC_CTRL0_RKMODE, 10, 8)
-
-/* DRAMC_REG_MISCTL0 */
-DEFINE_BIT(MISCTL0_REFP_ARBMASK_PBR2PBR_ENA, 0)
-DEFINE_BIT(MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS, 1)
-DEFINE_BITFIELD(MISCTL0_PG_WAKEUP_OPT, 15, 14)
-DEFINE_BIT(MISCTL0_PAGDIS, 17)
-DEFINE_BIT(MISCTL0_REFA_ARB_EN2, 19)
-DEFINE_BIT(MISCTL0_PBC_ARB_E1T, 23)
-DEFINE_BIT(MISCTL0_PBC_ARB_EN, 24)
-DEFINE_BIT(MISCTL0_EMIPREEN, 27)
-DEFINE_BIT(MISCTL0_REFP_ARB_EN2, 31)
-
-/* DRAMC_REG_SCSMCTRL */
-DEFINE_BIT(SCSMCTRL_SC_PG_UPD_OPT, 0)
-DEFINE_BIT(SCSMCTRL_SC_PG_MAN_DIS, 1)
-
-/* DRAMC_REG_SHUCTRL1 */
-DEFINE_BITFIELD(SHUCTRL1_FC_PRDCNT, 7, 0)
-DEFINE_BITFIELD(SHUCTRL1_CKFSPE_PRDCNT, 15, 8)
-DEFINE_BITFIELD(SHUCTRL1_CKFSPX_PRDCNT, 23, 16)
-DEFINE_BITFIELD(SHUCTRL1_VRCGEN_PRDCNT, 31, 24)
-
-/* DRAMC_REG_DVFS_TIMING_CTRL1 */
-DEFINE_BITFIELD(DVFS_TIMING_CTRL1_SHU_PERIOD_GO_ZERO_CNT, 7, 0)
-DEFINE_BITFIELD(DVFS_TIMING_CTRL1_DMSHU_CNT, 21, 16)
-
-/* DRAMC_REG_REFPEND1 */
-DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH0, 3, 0)
-DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH1, 7, 4)
-DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH2, 11, 8)
-DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH3, 15, 12)
-DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH4, 19, 16)
-DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH5, 23, 20)
-DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH6, 27, 24)
-DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH7, 31, 28)
-
-/* DRAMC_REG_CBT_WLEV_CTRL1 */
-DEFINE_BITFIELD(CBT_WLEV_CTRL1_CATRAINLAT, 14, 11)
-DEFINE_BITFIELD(CBT_WLEV_CTRL1_CATRAIN_INTV, 22, 15)
-DEFINE_BITFIELD(CBT_WLEV_CTRL1_TCMDO1LAT, 30, 23)
-
-/* DRAMC_REG_TX_SET0 */
-DEFINE_BITFIELD(TX_SET0_TXRANK, 1, 0)
-DEFINE_BIT(TX_SET0_TXRANKFIX, 2)
-DEFINE_BIT(TX_SET0_OE_DOWNGRADE, 6)
-DEFINE_BIT(TX_SET0_WPRE2T, 22)
-DEFINE_BIT(TX_SET0_DRSCLR_EN, 24)
-DEFINE_BIT(TX_SET0_DRSCLR_RK0_EN, 25)
-DEFINE_BIT(TX_SET0_RK_SCINPUT_OPT, 30)
-
-/* DRAMC_REG_DQSOSCR */
-DEFINE_BIT(DQSOSCR_ARUIDQ_SW, 7)
-DEFINE_BIT(DQSOSCR_SREF_TXUI_RELOAD_OPT, 23)
-DEFINE_BIT(DQSOSCR_DQSOSCRDIS, 24)
-DEFINE_BIT(DQSOSCR_R_DMDQS2DQ_FILT_OPT, 26)
-DEFINE_BIT(DQSOSCR_SREF_TXPI_RELOAD_OPT, 27)
-DEFINE_BIT(DQSOSCR_DQSOSC_CALEN, 31)
-
-/* DRAMC_REG_DUMMY_RD */
-DEFINE_BIT(DUMMY_RD_DUMMY_RD_SW, 4)
-DEFINE_BIT(DUMMY_RD_DMY_WR_DBG, 6)
-DEFINE_BIT(DUMMY_RD_DMY_RD_DBG, 7)
-DEFINE_BIT(DUMMY_RD_DRS_SELFWAKE_DMYRD_DIS, 15)
-DEFINE_BITFIELD(DUMMY_RD_RANK_NUM, 17, 16)
-DEFINE_BIT(DUMMY_RD_DUMMY_RD_EN, 20)
-DEFINE_BIT(DUMMY_RD_SREF_DMYRD_EN, 21)
-DEFINE_BIT(DUMMY_RD_DQSG_DMYRD_EN, 22)
-DEFINE_BIT(DUMMY_RD_DQSG_DMYWR_EN, 23)
-DEFINE_BIT(DUMMY_RD_DUMMY_RD_PA_OPT, 24)
-DEFINE_BIT(DUMMY_RD_DMYRD_REORDER_DIS, 27)
-
-/* DRAMC_REG_DUMMY_RD_INTV */
-DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT0, 0)
-DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT1, 1)
-DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT2, 2)
-DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT3, 3)
-DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT4, 4)
-DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT5, 5)
-DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT6, 6)
-DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT7, 7)
-
-/* DRAMC_REG_RK_DQSOSC */
-DEFINE_BIT(RK_DQSOSC_RK0_BYTE_MODE, 29)
-DEFINE_BIT(RK_DQSOSC_DQSOSCR_RK0EN, 30)
-
-/* DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0 */
-DEFINE_BIT(TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT, 31)
-
-/* DRAMC_REG_SWCMD_CTRL1 */
-DEFINE_BIT(SWCMD_CTRL1_RDDQC_LP_ENB, 2)
-DEFINE_BIT(SWCMD_CTRL1_WRFIFO_MODE2, 31)
-
-/* DRAMC_REG_DBG_CMDDEC_CMDSEL0 */
-DEFINE_BIT(DBG_CMDDEC_CMDSEL0_RANK0_10GBEN, 0)
-DEFINE_BIT(DBG_CMDDEC_CMDSEL0_RANK1_10GBEN, 1)
-
-/* DRAMC_REG_DBIWR_PROTECT */
-DEFINE_BIT(DBIWR_PROTECT_DBIWR_IMP_EN, 0)
-DEFINE_BIT(DBIWR_PROTECT_DBIWR_PINMUX_EN, 1)
-DEFINE_BITFIELD(DBIWR_PROTECT_DBIWR_OPT_B0, 23, 16)
-DEFINE_BITFIELD(DBIWR_PROTECT_DBIWR_OPT_B1, 31, 24)
-
-/* DDRPHY_REG_MISC_SRAM_DMA0 */
-DEFINE_BIT(MISC_SRAM_DMA0_SW_DMA_FIRE, 0)
-DEFINE_BIT(MISC_SRAM_DMA0_SW_MODE, 1)
-DEFINE_BIT(MISC_SRAM_DMA0_APB_WR_MODE, 2)
-DEFINE_BIT(MISC_SRAM_DMA0_SRAM_WR_MODE, 3)
-DEFINE_BITFIELD(MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM, 7, 4)
-DEFINE_BITFIELD(MISC_SRAM_DMA0_SW_SHU_LEVEL_APB, 11, 8)
-DEFINE_BITFIELD(MISC_SRAM_DMA0_PENABLE_LAT_WR, 15, 14)
-DEFINE_BIT(MISC_SRAM_DMA0_KEEP_SRAM_ARB_ENA, 16)
-DEFINE_BIT(MISC_SRAM_DMA0_KEEP_APB_ARB_ENA, 17)
-DEFINE_BIT(MISC_SRAM_DMA0_DMA_TIMER_EN, 18)
-DEFINE_BIT(MISC_SRAM_DMA0_SW_STEP_EN_MODE, 23)
-DEFINE_BITFIELD(MISC_SRAM_DMA0_APB_SLV_SEL, 29, 28)
-
-/* DDRPHY_MD32_REG_SSPM_MCLK_DIV */
-DEFINE_BIT(SSPM_MCLK_DIV_MCLK_DCM_EN, 8)
-
-/* DDRPHY_REG_CA_CMD7 */
-DEFINE_BIT(CA_CMD7_RG_TX_ARCLKB_PULL_DN, 0)
-DEFINE_BIT(CA_CMD7_RG_TX_ARCLKB_PULL_UP, 1)
-DEFINE_BIT(CA_CMD7_RG_TX_ARCLK_PULL_DN, 2)
-DEFINE_BIT(CA_CMD7_RG_TX_ARCLK_PULL_UP, 3)
-DEFINE_BIT(CA_CMD7_RG_TX_ARCS0_PULL_DN, 4)
-DEFINE_BIT(CA_CMD7_RG_TX_ARCS0_PULL_UP, 5)
-DEFINE_BIT(CA_CMD7_RG_TX_ARCMD_PULL_DN, 6)
-DEFINE_BIT(CA_CMD7_RG_TX_ARCMD_PULL_UP, 7)
-DEFINE_BIT(CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y, 16)
-
-/* DDRPHY_REG_B0_DQ7 */
-DEFINE_BIT(B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0, 0)
-DEFINE_BIT(B0_DQ7_RG_TX_ARDQS0B_PULL_UP_B0, 1)
-DEFINE_BIT(B0_DQ7_RG_TX_ARDQS0_PULL_DN_B0, 2)
-DEFINE_BIT(B0_DQ7_RG_TX_ARDQS0_PULL_UP_B0, 3)
-DEFINE_BIT(B0_DQ7_RG_TX_ARDQM0_PULL_DN_B0, 4)
-DEFINE_BIT(B0_DQ7_RG_TX_ARDQM0_PULL_UP_B0, 5)
-DEFINE_BIT(B0_DQ7_RG_TX_ARDQ_PULL_DN_B0, 6)
-DEFINE_BIT(B0_DQ7_RG_TX_ARDQ_PULL_UP_B0, 7)
-DEFINE_BIT(B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y, 16)
-
-/* DDRPHY_REG_B1_DQ7 */
-DEFINE_BIT(B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1, 0)
-DEFINE_BIT(B1_DQ7_RG_TX_ARDQS0B_PULL_UP_B1, 1)
-DEFINE_BIT(B1_DQ7_RG_TX_ARDQS0_PULL_DN_B1, 2)
-DEFINE_BIT(B1_DQ7_RG_TX_ARDQS0_PULL_UP_B1, 3)
-DEFINE_BIT(B1_DQ7_RG_TX_ARDQM0_PULL_DN_B1, 4)
-DEFINE_BIT(B1_DQ7_RG_TX_ARDQM0_PULL_UP_B1, 5)
-DEFINE_BIT(B1_DQ7_RG_TX_ARDQ_PULL_DN_B1, 6)
-DEFINE_BIT(B1_DQ7_RG_TX_ARDQ_PULL_UP_B1, 7)
-DEFINE_BIT(B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y, 16)
-
-/* DDRPHY_REG_B0_DQ11 */
-DEFINE_BIT(B0_DQ11_DMY_DQ11_B0, 0)
-
-/* DDRPHY_REG_B1_DQ11 */
-DEFINE_BIT(B1_DQ11_DMY_DQ11_B1, 0)
-
-/* DDRPHY_REG_MISC_SRAM_DMA1 */
-DEFINE_BITFIELD(MISC_SRAM_DMA1_SPM_RESTORE_STEP_EN, 16, 0)
-DEFINE_BIT(MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS, 19)
-DEFINE_BITFIELD(MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL, 23, 20)
-
-/* DDRPHY_REG_MISC_CG_CTRL7 */
-DEFINE_BIT(MISC_CG_CTRL7_CK_BFE_DCM_EN, 11)
-DEFINE_BIT(MISC_CG_CTRL7_ARMCTL_CK_OUT_CG_SEL, 16)
-
-/* DDRPHY_REG_MISC_DVFSCTL2 */
-DEFINE_BIT(MISC_DVFSCTL2_RG_TOPCK_FMEM_CK_BLOCK_DURING_DFS, 3)
-DEFINE_BIT(MISC_DVFSCTL2_RG_DLL_SHUFFLE, 4)
-DEFINE_BIT(MISC_DVFSCTL2_RG_ADA_MCK8X_EN_SHUFFLE, 5)
-DEFINE_BIT(MISC_DVFSCTL2_RG_MRW_AFTER_DFS, 8)
-DEFINE_BIT(MISC_DVFSCTL2_R_DVFS_CDC_OPTION, 9)
-DEFINE_BIT(MISC_DVFSCTL2_R_DVFS_DLL_CHA, 12)
-DEFINE_BIT(MISC_DVFSCTL2_R_CDC_MUX_SEL_OPTION, 13)
-DEFINE_BIT(MISC_DVFSCTL2_R_DVFS_PARK_N, 14)
-DEFINE_BIT(MISC_DVFSCTL2_R_DVFS_OPTION, 15)
-DEFINE_BIT(MISC_DVFSCTL2_R_DVFS_CLK_CHG_OK_SEL, 29)
-DEFINE_BIT(MISC_DVFSCTL2_R_DVFS_SYNC_MODULE_RST_SEL, 31)
-
-/* DDRPHY_REG_MISC_DVFSCTL3 */
-DEFINE_BIT(MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_MCLK, 4)
-DEFINE_BIT(MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_MCLK, 5)
-DEFINE_BIT(MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_BCLK, 6)
-DEFINE_BIT(MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_BCLK, 7)
-DEFINE_BITFIELD(MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI, 9, 8)
-DEFINE_BITFIELD(MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE, 11, 10)
-DEFINE_BITFIELD(MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_MCLK, 17, 12)
-DEFINE_BITFIELD(MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_BCLK, 27, 22)
-DEFINE_BITFIELD(MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_BCLK, 31, 28)
-
-/* DDRPHY_REG_MISC_CLK_CTRL */
-DEFINE_BIT(MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN, 0)
-DEFINE_BIT(MISC_CLK_CTRL_DVFS_CLK_MEM_SEL, 1)
-DEFINE_BITFIELD(MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL, 10, 9)
-DEFINE_BITFIELD(MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE, 13, 12)
-
-/* DDRPHY_REG_MISC_SHU_OPT */
-DEFINE_BIT(MISC_SHU_OPT_R_DQB0_SHU_PHY_GATING_RESETB_SPM_EN, 0)
-DEFINE_BITFIELD(MISC_SHU_OPT_R_DQB0_SHU_PHDET_SPM_EN, 3, 2)
-DEFINE_BIT(MISC_SHU_OPT_R_DQB1_SHU_PHY_GATING_RESETB_SPM_EN, 8)
-DEFINE_BITFIELD(MISC_SHU_OPT_R_DQB1_SHU_PHDET_SPM_EN, 11, 10)
-DEFINE_BIT(MISC_SHU_OPT_R_CA_SHU_PHY_GATING_RESETB_SPM_EN, 16)
-DEFINE_BITFIELD(MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN, 19, 18)
-
-/* DRAMC_REG_SHU_SELPH_CA1 */
-DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_CS, 2, 0)
-DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_CKE, 6, 4)
-DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_ODT, 10, 8)
-DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_RESET, 14, 12)
-DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_WE, 18, 16)
-DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_CAS, 22, 20)
-DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_RAS, 26, 24)
-DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_CS1, 30, 28)
-
-/* DRAMC_REG_SHU_SELPH_CA2 */
-DEFINE_BITFIELD(SHU_SELPH_CA2_TXDLY_BA0, 2, 0)
-DEFINE_BITFIELD(SHU_SELPH_CA2_TXDLY_BA1, 6, 4)
-DEFINE_BITFIELD(SHU_SELPH_CA2_TXDLY_BA2, 10, 8)
-DEFINE_BITFIELD(SHU_SELPH_CA2_TXDLY_CKE1, 26, 24)
-
-/* DRAMC_REG_SHU_SELPH_CA3 */
-DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA0, 2, 0)
-DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA1, 6, 4)
-DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA2, 10, 8)
-DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA3, 14, 12)
-DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA4, 18, 16)
-DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA5, 22, 20)
-DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA6, 26, 24)
-DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA7, 30, 28)
-
-/* DRAMC_REG_SHU_SELPH_CA4 */
-DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA8, 2, 0)
-DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA9, 6, 4)
-DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA10, 10, 8)
-DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA11, 14, 12)
-DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA12, 18, 16)
-DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA13, 22, 20)
-DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA14, 26, 24)
-DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA15, 30, 28)
-
-/* DRAMC_REG_SHU_SELPH_CA5 */
-DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_CS, 2, 0)
-DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_CKE, 6, 4)
-DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_ODT, 10, 8)
-DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_RESET, 14, 12)
-DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_WE, 18, 16)
-DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_CAS, 22, 20)
-DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_RAS, 26, 24)
-DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_CS1, 30, 28)
-
-/* DRAMC_REG_SHU_SELPH_CA6 */
-DEFINE_BITFIELD(SHU_SELPH_CA6_DLY_BA0, 2, 0)
-DEFINE_BITFIELD(SHU_SELPH_CA6_DLY_BA1, 6, 4)
-DEFINE_BITFIELD(SHU_SELPH_CA6_DLY_BA2, 10, 8)
-DEFINE_BITFIELD(SHU_SELPH_CA6_DLY_CKE1, 26, 24)
-
-/* DRAMC_REG_SHU_SELPH_CA7 */
-DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA0, 2, 0)
-DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA1, 6, 4)
-DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA2, 10, 8)
-DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA3, 14, 12)
-DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA4, 18, 16)
-DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA5, 22, 20)
-DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA6, 26, 24)
-DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA7, 30, 28)
-
-/* DRAMC_REG_SHU_SELPH_CA8 */
-DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA8, 2, 0)
-DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA9, 6, 4)
-DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA10, 10, 8)
-DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA11, 14, 12)
-DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA12, 18, 16)
-DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA13, 22, 20)
-DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA14, 26, 24)
-DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA15, 30, 28)
-
-/* DDRPHY_REG_SHU_MISC_DRVING2 */
-DEFINE_BITFIELD(SHU_MISC_DRVING2_CMDDRVN1, 4, 0)
-DEFINE_BITFIELD(SHU_MISC_DRVING2_CMDDRVP1, 9, 5)
-DEFINE_BITFIELD(SHU_MISC_DRVING2_CMDDRVN2, 14, 10)
-DEFINE_BITFIELD(SHU_MISC_DRVING2_CMDDRVP2, 19, 15)
-DEFINE_BITFIELD(SHU_MISC_DRVING2_DQDRVN1, 24, 20)
-DEFINE_BITFIELD(SHU_MISC_DRVING2_DQDRVP1, 29, 25)
-DEFINE_BIT(SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN, 31)
-
-/* DDRPHY_REG_SHU_MISC_IMPCAL1 */
-DEFINE_BITFIELD(SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE, 2, 0)
-DEFINE_BITFIELD(SHU_MISC_IMPCAL1_IMPDRVP, 8, 4)
-DEFINE_BITFIELD(SHU_MISC_IMPCAL1_IMPDRVN, 16, 12)
-DEFINE_BITFIELD(SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE, 19, 17)
-DEFINE_BITFIELD(SHU_MISC_IMPCAL1_IMPCALCNT, 27, 20)
-DEFINE_BITFIELD(SHU_MISC_IMPCAL1_IMPCAL_CALICNT, 31, 28)
-
-/* DDRPHY_REG_SHU_CA_CMD12 */
-DEFINE_BITFIELD(SHU_CA_CMD12_RG_RIMP_REV, 7, 0)
-DEFINE_BITFIELD(SHU_CA_CMD12_RG_RIMP_VREF_SEL_ODTN, 14, 8)
-DEFINE_BITFIELD(SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVN, 22, 16)
-DEFINE_BIT(SHU_CA_CMD12_RG_RIMP_DRV05, 23)
-DEFINE_BITFIELD(SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVP, 30, 24)
-DEFINE_BIT(SHU_CA_CMD12_RG_RIMP_UNTERM_EN, 31)
-
-/* DDRPHY_REG_MISC_SHU_IMPEDAMCE_UPD_DIS1 */
-DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVP_UPD_DIS, 0)
-DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVN_UPD_DIS, 1)
-DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_ODTN_UPD_DIS, 2)
-DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVP_UPD_DIS, 4)
-DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVN_UPD_DIS, 5)
-DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_ODTN_UPD_DIS, 6)
-DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVP_UPD_DIS, 8)
-DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVN_UPD_DIS, 9)
-DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS, 10)
-DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVP_UPD_DIS, 12)
-DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVN_UPD_DIS, 13)
-DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_ODTN_UPD_DIS, 14)
-DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVP_UPD_DIS, 16)
-DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVN_UPD_DIS, 17)
-DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_ODTN_UPD_DIS, 18)
-DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_DRVP_UPD_DIS, 20)
-DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_DRVN_UPD_DIS, 21)
-DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_ODTN_UPD_DIS, 22)
-DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVP_UPD_DIS, 28)
-DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVN_UPD_DIS, 29)
-DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_ODTN_UPD_DIS, 30)
-
-/* DDRPHY_REG_SHU_MISC_DRVING6 */
-DEFINE_BITFIELD(SHU_MISC_DRVING6_IMP_TXDLY_CMD, 5, 0)
-
-/* DRAMC_REG_SHU_COMMON0 */
-DEFINE_BIT(SHU_COMMON0_FREQDIV4, 0)
-DEFINE_BIT(SHU_COMMON0_FDIV2, 1)
-DEFINE_BIT(SHU_COMMON0_DM64BITEN, 4)
-DEFINE_BIT(SHU_COMMON0_BL4, 10)
-DEFINE_BIT(SHU_COMMON0_BC4OTF, 12)
-
-/* DRAMC_REG_SHU_ACTIMING_CONF */
-DEFINE_BITFIELD(SHU_ACTIMING_CONF_SCINTV, 5, 0)
-DEFINE_BITFIELD(SHU_ACTIMING_CONF_REFBW_FR, 25, 16)
-DEFINE_BIT(SHU_ACTIMING_CONF_TREFBWIG, 31)
-
-/* DRAMC_REG_SHU_DCM_CTRL0 */
-DEFINE_BIT(SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT, 7)
-DEFINE_BITFIELD(SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT, 10, 8)
-DEFINE_BITFIELD(SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL, 15, 12)
-DEFINE_BITFIELD(SHU_DCM_CTRL0_APHYPI_CKCGL_CNT, 19, 16)
-DEFINE_BITFIELD(SHU_DCM_CTRL0_APHYPI_CKCGH_CNT, 23, 20)
-DEFINE_BIT(SHU_DCM_CTRL0_FASTWAKE2, 29)
-DEFINE_BIT(SHU_DCM_CTRL0_FASTWAKE, 31)
-
-/* DRAMC_REG_SHU_CONF0 */
-DEFINE_BITFIELD(SHU_CONF0_DMPGTIM, 6, 0)
-DEFINE_BIT(SHU_CONF0_ADVPREEN, 7)
-DEFINE_BIT(SHU_CONF0_PBREFEN, 8)
-DEFINE_BITFIELD(SHU_CONF0_REFTHD, 15, 12)
-
-/* DRAMC_REG_SHU_MATYPE */
-DEFINE_BITFIELD(SHU_MATYPE_MATYPE, 1, 0)
-
-/* DRAMC_REG_SHU_SCHEDULER */
-DEFINE_BIT(SHU_SCHEDULER_DUALSCHEN, 2)
-
-/* DRAMC_REG_SHU_TX_SET0 */
-DEFINE_BITFIELD(SHU_TX_SET0_DQOE_CNT, 3, 0)
-DEFINE_BIT(SHU_TX_SET0_DQOE_OPT, 4)
-DEFINE_BITFIELD(SHU_TX_SET0_TXUPD_SEL, 7, 6)
-DEFINE_BITFIELD(SHU_TX_SET0_TXUPD_W2R_SEL, 10, 8)
-DEFINE_BIT(SHU_TX_SET0_DBIWR, 12)
-DEFINE_BIT(SHU_TX_SET0_WDATRGO, 13)
-DEFINE_BIT(SHU_TX_SET0_WPST1P5T, 15)
-DEFINE_BITFIELD(SHU_TX_SET0_OE_EXT2UI, 24, 22)
-DEFINE_BITFIELD(SHU_TX_SET0_DQS2DQ_FILT_PITHRD, 30, 25)
-
-/* DDRPHY_REG_MISC_SHU_STBCAL1 */
-DEFINE_BIT(MISC_SHU_STBCAL1_STB_UPDMASK_EN, 11)
-DEFINE_BITFIELD(MISC_SHU_STBCAL1_STB_UPDMASKCYC, 15, 12)
-DEFINE_BIT(MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL, 16)
-DEFINE_BITFIELD(MISC_SHU_STBCAL1_STB_PI_TRACKING_RATIO, 25, 20)
-
-/* DDRPHY_REG_MISC_SHU_STBCAL */
-DEFINE_BITFIELD(MISC_SHU_STBCAL_DMSTBLAT, 3, 0)
-DEFINE_BITFIELD(MISC_SHU_STBCAL_PICGLAT, 6, 4)
-DEFINE_BIT(MISC_SHU_STBCAL_DQSG_MODE, 8)
-DEFINE_BIT(MISC_SHU_STBCAL_DQSIEN_PICG_MODE, 9)
-
-/* DDRPHY_REG_MISC_SHU_RANKCTL */
-DEFINE_BITFIELD(MISC_SHU_RANKCTL_RANKINCTL_RXDLY, 3, 0)
-DEFINE_BIT(MISC_SHU_RANKCTL_RANK_RXDLY_OPT, 4)
-DEFINE_BIT(MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN, 15)
-DEFINE_BITFIELD(MISC_SHU_RANKCTL_RANKINCTL_STB, 19, 16)
-DEFINE_BITFIELD(MISC_SHU_RANKCTL_RANKINCTL, 23, 20)
-DEFINE_BITFIELD(MISC_SHU_RANKCTL_RANKINCTL_ROOT1, 27, 24)
-DEFINE_BITFIELD(MISC_SHU_RANKCTL_RANKINCTL_PHY, 31, 28)
-
-/* DRAMC_REG_SHU_MISC */
-DEFINE_BITFIELD(SHU_MISC_REQQUE_MAXCNT, 3, 0)
-DEFINE_BITFIELD(SHU_MISC_DCMDLYREF, 18, 16)
-DEFINE_BIT(SHU_MISC_DAREFEN, 30)
-
-/* DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL */
-DEFINE_BITFIELD(MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT, 2, 0)
-DEFINE_BITFIELD(MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT, 6, 4)
-
-/* DDRPHY_REG_MISC_SHU_RODTENSTB */
-DEFINE_BIT(MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN, 0)
-DEFINE_BIT(MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE, 1)
-DEFINE_BIT(MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL, 3)
-DEFINE_BIT(MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE, 4)
-DEFINE_BIT(MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME, 5)
-DEFINE_BITFIELD(MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET, 11, 8)
-DEFINE_BITFIELD(MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET, 15, 12)
-DEFINE_BITFIELD(MISC_SHU_RODTENSTB_RODTENSTB_EXT, 31, 16)
-
-/* DDRPHY_REG_MISC_SHU_RODTENSTB1 */
-DEFINE_BITFIELD(MISC_SHU_RODTENSTB1_RODTENCGEN_HEAD, 5, 4)
-DEFINE_BITFIELD(MISC_SHU_RODTENSTB1_RODTENCGEN_TAIL, 7, 6)
-
-/* DDRPHY_REG_MISC_SHU_RX_SELPH_MODE */
-DEFINE_BITFIELD(MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE, 1, 0)
-DEFINE_BITFIELD(MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE, 5, 4)
-DEFINE_BITFIELD(MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE, 7, 6)
-
-/* DDRPHY_REG_MISC_SHU_RDAT1 */
-DEFINE_BIT(MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT, 0)
-DEFINE_BIT(MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT, 1)
-DEFINE_BIT(MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT, 2)
-
-/* DRAMC_REG_SHURK_CKE_CTRL */
-DEFINE_BITFIELD(SHURK_CKE_CTRL_CKE_DBE_CNT, 3, 0)
-
-/* DDRPHY_REG_MISC_SHU_DQSG_RETRY1 */
-DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_SW_RESET, 0)
-DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_SW_EN, 1)
-DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_DDR1866_PLUS, 2)
-DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_ONCE, 3)
-DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_3TIMES, 4)
-DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_1RANK, 5)
-DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_BY_RANK, 6)
-DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_DM4BYTE, 7)
-DEFINE_BITFIELD(MISC_SHU_DQSG_RETRY1_RETRY_DQSIENLAT, 11, 8)
-DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_STBENCMP_ALLBYTE, 12)
-DEFINE_BIT(MISC_SHU_DQSG_RETRY1_XSR_DQSG_RETRY_EN, 13)
-DEFINE_BIT(MISC_SHU_DQSG_RETRY1_XSR_RETRY_SPM_MODE, 14)
-DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_CMP_DATA, 15)
-DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_ALE_BLOCK_MASK, 20)
-DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_RDY_SEL_DLE, 21)
-DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_USE_NON_EXTEND, 22)
-DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_USE_CG_GATING, 23)
-DEFINE_BITFIELD(MISC_SHU_DQSG_RETRY1_RETRY_ROUND_NUM, 25, 24)
-DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_RANKSEL_FROM_PHY, 28)
-DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_PA_DISABLE, 29)
-DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_STBEN_RESET_MSK, 30)
-DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_USE_BURST_MODE, 31)
-
-/* DRAMC_REG_SHU_HWSET_MR13 */
-DEFINE_BITFIELD(SHU_HWSET_MR13_HWSET_MR13_MRSMA, 12, 0)
-DEFINE_BITFIELD(SHU_HWSET_MR13_HWSET_MR13_OP, 23, 16)
-
-/* DRAMC_REG_SHU_HWSET_VRCG */
-DEFINE_BITFIELD(SHU_HWSET_VRCG_HWSET_VRCG_MRSMA, 12, 0)
-DEFINE_BITFIELD(SHU_HWSET_VRCG_HWSET_VRCG_OP, 23, 16)
-DEFINE_BITFIELD(SHU_HWSET_VRCG_VRCGDIS_PRDCNT, 31, 24)
-
-/* DRAMC_REG_SHU_HWSET_MR2 */
-DEFINE_BITFIELD(SHU_HWSET_MR2_HWSET_MR2_MRSMA, 12, 0)
-DEFINE_BITFIELD(SHU_HWSET_MR2_HWSET_MR2_OP, 23, 16)
-
-/* DDRPHY_REG_MISC_SHU_DVFSDLL */
-DEFINE_BIT(MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL, 0)
-DEFINE_BIT(MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL, 1)
-DEFINE_BITFIELD(MISC_SHU_DVFSDLL_R_DLL_IDLE, 10, 4)
-DEFINE_BITFIELD(MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE, 22, 16)
-
-/* DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL */
-DEFINE_BIT(SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN, 0)
-
-/* DRAMC_REG_SHU_ACTIM1 */
-DEFINE_BITFIELD(SHU_ACTIM1_TRPAB, 3, 0)
-DEFINE_BITFIELD(SHU_ACTIM1_TMRWCKEL, 7, 4)
-DEFINE_BITFIELD(SHU_ACTIM1_TRP, 11, 8)
-DEFINE_BITFIELD(SHU_ACTIM1_TRAS, 21, 16)
-DEFINE_BITFIELD(SHU_ACTIM1_TRC, 28, 24)
-
-/* DRAMC_REG_SHU_ACTIM3 */
-DEFINE_BITFIELD(SHU_ACTIM3_TRFCPB, 7, 0)
-DEFINE_BITFIELD(SHU_ACTIM3_MANTMRR, 11, 8)
-DEFINE_BITFIELD(SHU_ACTIM3_TR2MRR, 15, 12)
-DEFINE_BITFIELD(SHU_ACTIM3_TRFC, 23, 16)
-DEFINE_BITFIELD(SHU_ACTIM3_TWTR_L, 29, 24)
-
-/* DRAMC_REG_SHU_ACTIM2 */
-DEFINE_BITFIELD(SHU_ACTIM2_TXP, 3, 0)
-DEFINE_BITFIELD(SHU_ACTIM2_TMRRI, 8, 4)
-DEFINE_BITFIELD(SHU_ACTIM2_TRTP, 14, 12)
-DEFINE_BITFIELD(SHU_ACTIM2_TR2W, 21, 16)
-DEFINE_BITFIELD(SHU_ACTIM2_TFAW, 28, 24)
-
-/* DRAMC_REG_SHU_ACTIM0 */
-DEFINE_BITFIELD(SHU_ACTIM0_TWTR, 5, 0)
-DEFINE_BITFIELD(SHU_ACTIM0_TWR, 15, 8)
-DEFINE_BITFIELD(SHU_ACTIM0_TRRD, 18, 16)
-DEFINE_BITFIELD(SHU_ACTIM0_TRCD, 27, 24)
-DEFINE_BITFIELD(SHU_ACTIM0_CKELCKCNT, 31, 28)
-
-/* DRAMC_REG_SHU_ACTIM5 */
-DEFINE_BITFIELD(SHU_ACTIM5_TR2PD, 6, 0)
-DEFINE_BITFIELD(SHU_ACTIM5_TWTPD, 14, 8)
-DEFINE_BITFIELD(SHU_ACTIM5_TPBR2PBR, 23, 16)
-DEFINE_BITFIELD(SHU_ACTIM5_TPBR2ACT, 29, 28)
-
-/* DRAMC_REG_SHU_ACTIM6 */
-DEFINE_BITFIELD(SHU_ACTIM6_TZQLAT2, 4, 0)
-DEFINE_BITFIELD(SHU_ACTIM6_TMRD, 11, 8)
-DEFINE_BITFIELD(SHU_ACTIM6_TMRW, 15, 12)
-DEFINE_BITFIELD(SHU_ACTIM6_TW2MRW, 25, 20)
-DEFINE_BITFIELD(SHU_ACTIM6_TR2MRW, 31, 26)
-
-/* DRAMC_REG_SHU_ACTIM4 */
-DEFINE_BITFIELD(SHU_ACTIM4_TXREFCNT, 9, 0)
-DEFINE_BITFIELD(SHU_ACTIM4_TMRR2MRW, 15, 10)
-DEFINE_BITFIELD(SHU_ACTIM4_TMRR2W, 21, 16)
-DEFINE_BITFIELD(SHU_ACTIM4_TZQCS, 31, 24)
-
-/* DRAMC_REG_SHU_CKECTRL */
-DEFINE_BIT(SHU_CKECTRL_TPDE_05T, 0)
-DEFINE_BIT(SHU_CKECTRL_TPDX_05T, 1)
-DEFINE_BITFIELD(SHU_CKECTRL_TPDE, 14, 12)
-DEFINE_BITFIELD(SHU_CKECTRL_TPDX, 18, 16)
-DEFINE_BITFIELD(SHU_CKECTRL_TCKEPRD, 22, 20)
-DEFINE_BITFIELD(SHU_CKECTRL_TCKESRX, 25, 24)
-
-/* DRAMC_REG_SHU_ACTIM_XRT */
-DEFINE_BITFIELD(SHU_ACTIM_XRT_XRTR2R, 4, 0)
-DEFINE_BITFIELD(SHU_ACTIM_XRT_XRTR2W, 13, 8)
-DEFINE_BITFIELD(SHU_ACTIM_XRT_XRTW2R, 19, 16)
-DEFINE_BITFIELD(SHU_ACTIM_XRT_XRTW2W, 28, 24)
-
-/* DRAMC_REG_SHU_AC_TIME_05T */
-DEFINE_BIT(SHU_AC_TIME_05T_TRC_05T, 0)
-DEFINE_BIT(SHU_AC_TIME_05T_TRFCPB_05T, 1)
-DEFINE_BIT(SHU_AC_TIME_05T_TRFC_05T, 2)
-DEFINE_BIT(SHU_AC_TIME_05T_TPBR2PBR_05T, 3)
-DEFINE_BIT(SHU_AC_TIME_05T_TXP_05T, 4)
-DEFINE_BIT(SHU_AC_TIME_05T_TRTP_05T, 5)
-DEFINE_BIT(SHU_AC_TIME_05T_TRCD_05T, 6)
-DEFINE_BIT(SHU_AC_TIME_05T_TRP_05T, 7)
-DEFINE_BIT(SHU_AC_TIME_05T_TRPAB_05T, 8)
-DEFINE_BIT(SHU_AC_TIME_05T_TRAS_05T, 9)
-DEFINE_BIT(SHU_AC_TIME_05T_TWR_M05T, 10)
-DEFINE_BIT(SHU_AC_TIME_05T_TRRD_05T, 12)
-DEFINE_BIT(SHU_AC_TIME_05T_TFAW_05T, 13)
-DEFINE_BIT(SHU_AC_TIME_05T_TCKEPRD_05T, 14)
-DEFINE_BIT(SHU_AC_TIME_05T_TR2PD_05T, 15)
-DEFINE_BIT(SHU_AC_TIME_05T_TWTPD_M05T, 16)
-DEFINE_BIT(SHU_AC_TIME_05T_TMRRI_05T, 17)
-DEFINE_BIT(SHU_AC_TIME_05T_TMRWCKEL_05T, 18)
-DEFINE_BIT(SHU_AC_TIME_05T_BGTRRD_05T, 19)
-DEFINE_BIT(SHU_AC_TIME_05T_BGTCCD_05T, 20)
-DEFINE_BIT(SHU_AC_TIME_05T_BGTWTR_M05T, 21)
-DEFINE_BIT(SHU_AC_TIME_05T_TR2W_05T, 22)
-DEFINE_BIT(SHU_AC_TIME_05T_TWTR_M05T, 23)
-DEFINE_BIT(SHU_AC_TIME_05T_XRTR2W_05T, 24)
-DEFINE_BIT(SHU_AC_TIME_05T_TMRD_05T, 25)
-DEFINE_BIT(SHU_AC_TIME_05T_TMRW_05T, 26)
-DEFINE_BIT(SHU_AC_TIME_05T_TMRR2MRW_05T, 27)
-DEFINE_BIT(SHU_AC_TIME_05T_TW2MRW_05T, 28)
-DEFINE_BIT(SHU_AC_TIME_05T_TR2MRW_05T, 29)
-DEFINE_BIT(SHU_AC_TIME_05T_TPBR2ACT_05T, 30)
-DEFINE_BIT(SHU_AC_TIME_05T_XRTW2R_M05T, 31)
-
-/* DRAMC_REG_SHU_AC_DERATING0 */
-DEFINE_BIT(SHU_AC_DERATING0_ACDERATEEN, 0)
-DEFINE_BITFIELD(SHU_AC_DERATING0_TRRD_DERATE, 18, 16)
-DEFINE_BITFIELD(SHU_AC_DERATING0_TRCD_DERATE, 27, 24)
-
-/* DRAMC_REG_SHU_AC_DERATING1 */
-DEFINE_BITFIELD(SHU_AC_DERATING1_TRPAB_DERATE, 3, 0)
-DEFINE_BITFIELD(SHU_AC_DERATING1_TRP_DERATE, 11, 8)
-DEFINE_BITFIELD(SHU_AC_DERATING1_TRAS_DERATE, 21, 16)
-DEFINE_BITFIELD(SHU_AC_DERATING1_TRC_DERATE, 28, 24)
-
-/* DRAMC_REG_SHU_AC_DERATING_05T */
-DEFINE_BIT(SHU_AC_DERATING_05T_TRC_05T_DERATE, 0)
-DEFINE_BIT(SHU_AC_DERATING_05T_TRCD_05T_DERATE, 6)
-DEFINE_BIT(SHU_AC_DERATING_05T_TRP_05T_DERATE, 7)
-DEFINE_BIT(SHU_AC_DERATING_05T_TRPAB_05T_DERATE, 8)
-DEFINE_BIT(SHU_AC_DERATING_05T_TRAS_05T_DERATE, 9)
-DEFINE_BIT(SHU_AC_DERATING_05T_TRRD_05T_DERATE, 12)
-
-/* DRAMC_REG_REFCTRL3 */
-DEFINE_BITFIELD(REFCTRL3_REF_DERATING_EN, 15, 0)
-
-/* DDRPHY_REG_MISC_SHU_RK_DQSCTL */
-DEFINE_BITFIELD(MISC_SHU_RK_DQSCTL_DQSINCTL, 3, 0)
-
-/* DDRPHY_REG_MISC_SHU_ODTCTRL */
-DEFINE_BIT(MISC_SHU_ODTCTRL_RODTEN, 0)
-DEFINE_BIT(MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG, 1)
-DEFINE_BITFIELD(MISC_SHU_ODTCTRL_RODT_LAT, 7, 4)
-DEFINE_BIT(MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN, 15)
-DEFINE_BITFIELD(MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT, 25, 24)
-DEFINE_BIT(MISC_SHU_ODTCTRL_FIXRODT, 27)
-DEFINE_BIT(MISC_SHU_ODTCTRL_RODTEN_OPT, 29)
-DEFINE_BIT(MISC_SHU_ODTCTRL_RODTE2, 30)
-DEFINE_BIT(MISC_SHU_ODTCTRL_RODTE, 31)
-
-/* DDRPHY_REG_SHU_MISC_RANK_SEL_STB */
-DEFINE_BIT(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN, 0)
-DEFINE_BIT(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23, 1)
-DEFINE_BITFIELD(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE, 3, 2)
-DEFINE_BIT(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK, 4)
-DEFINE_BIT(SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK, 5)
-DEFINE_BIT(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN, 7)
-DEFINE_BITFIELD(SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, 11, 8)
-DEFINE_BITFIELD(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS, 19, 16)
-DEFINE_BITFIELD(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS, 23, 20)
-DEFINE_BITFIELD(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS, 27, 24)
-DEFINE_BITFIELD(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS, 31, 28)
-
-/* DDRPHY_REG_MISC_SHU_RDAT */
-DEFINE_BITFIELD(MISC_SHU_RDAT_DATLAT, 4, 0)
-DEFINE_BITFIELD(MISC_SHU_RDAT_DATLAT_DSEL, 12, 8)
-DEFINE_BITFIELD(MISC_SHU_RDAT_DATLAT_DSEL_PHY, 20, 16)
-
-/* DRAMC_REG_SHU_TX_RANKCTL */
-DEFINE_BITFIELD(SHU_TX_RANKCTL_TXRANKINCTL_TXDLY, 3, 0)
-DEFINE_BITFIELD(SHU_TX_RANKCTL_TXRANKINCTL, 7, 4)
-DEFINE_BITFIELD(SHU_TX_RANKCTL_TXRANKINCTL_ROOT, 11, 8)
-
-/* DRAMC_REG_BYPASS_FSPOP */
-DEFINE_BIT(BYPASS_FSPOP_BPFSP_OPT, 16)
-
-/* DDRPHY_MD32_REG_LPIF_FSM_CFG_1 */
-DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL, 0)
-DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND, 1)
-DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR, 2)
-DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND, 3)
-DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW, 4)
-DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW_2ND, 5)
-DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL, 6)
-DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL_2ND, 7)
-
-/* DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0 */
-DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_PHYPLL_EN, 3, 2)
-DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_DPY_DLL_EN, 5, 4)
-DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_DPY_2ND_DLL_EN, 7, 6)
-DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_DPY_DLL_CK_EN, 9, 8)
-DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_DPY_VREF_EN, 11, 10)
-DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN, 17, 16)
-DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN, 21, 20)
-DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW, 23, 22)
-DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN, 25, 24)
-DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW, 27, 26)
-
-/* DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1 */
-DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_1_DMY_EN_MOD_SEL, 13, 12)
-DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_1_DMYRD_INTV_SEL, 15, 14)
-DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_1_DMYRD_EN, 17, 16)
-DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_1_TX_TRACKING_RETRY_EN, 21, 20)
-DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_1_DR_SHU_SRAM_LEVEL, 29, 22)
-
-/* DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3 */
-DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_3_DPY_MCK8X_EN, 1, 0)
-DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_3_DPY_MIDPI_EN, 3, 2)
-DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_3_DPY_PI_RESETB_EN, 5, 4)
-
-/* DDRPHY_MD32_REG_LPIF_FSM_OUT_CTRL_0 */
-DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_EN, 1)
-DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_EN, 2)
-DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_2ND_DLL_EN, 3)
-DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_CK_EN, 4)
-DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_VREF_EN, 5)
-DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_SHU_EN, 10)
-DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_MODE_SW, 11)
-
-/* DDRPHY_REG_CLRPLL0 */
-DEFINE_BIT(CLRPLL0_RG_RCLRPLL_EN, 31)
-
-/* DDRPHY_MD32_REG_LPIF_DFD_DBUG_0 */
-DEFINE_BIT(LPIF_DFD_DBUG_0_LPIF_DFD_DEBUG_ISO_EN, 0)
-
-/* DDRPHY_REG_MISC_DMA_DEBUG0 */
-DEFINE_BIT(MISC_DMA_DEBUG0_SRAM_DONE, 16)
-DEFINE_BIT(MISC_DMA_DEBUG0_APB_DONE, 17)
-DEFINE_BIT(MISC_DMA_DEBUG0_SC_DR_SRAM_LOAD_ACK, 29)
-DEFINE_BIT(MISC_DMA_DEBUG0_SC_DR_SRAM_RESTORE_ACK, 30)
-
-/* DDRPHY_MD32_REG_LPIF_STATUS_4 */
-DEFINE_BITFIELD(LPIF_STATUS_4_SHU_EN_ACK, 15, 14)
-
-/* DRAMC_REG_MRR_STATUS2 */
-DEFINE_BITFIELD(MRR_STATUS2_DVFS_STATE, 31, 24)
-
-/* DDRPHY_REG_SHU_MISC_RDSEL_TRACK */
-DEFINE_BITFIELD(SHU_MISC_RDSEL_TRACK_DMDATLAT_I, 4, 0)
-DEFINE_BIT(SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK, 6)
-DEFINE_BIT(SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN, 7)
-DEFINE_BITFIELD(SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG, 19, 8)
-DEFINE_BITFIELD(SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS, 31, 20)
-
-/* DDRPHY_REG_MISC_SHU_PHY_RX_CTRL */
-DEFINE_BIT(MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN, 8)
-DEFINE_BITFIELD(MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET, 11, 9)
-DEFINE_BITFIELD(MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET, 15, 14)
-DEFINE_BITFIELD(MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD, 18, 16)
-DEFINE_BITFIELD(MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL, 22, 20)
-DEFINE_BITFIELD(MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD, 26, 24)
-DEFINE_BITFIELD(MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL, 30, 28)
-
-/* DDRPHY_REG_MISC_SHU_RANK_SEL_LAT */
-DEFINE_BITFIELD(MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0, 3, 0)
-DEFINE_BITFIELD(MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1, 7, 4)
-DEFINE_BITFIELD(MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA, 11, 8)
-
-/* DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY */
-DEFINE_BITFIELD(SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 3, 0)
-DEFINE_BITFIELD(SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 7, 4)
-DEFINE_BITFIELD(SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 19, 16)
-DEFINE_BITFIELD(SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 23, 20)
-
-/* DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY */
-DEFINE_BITFIELD(SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 6, 0)
-
-/* DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY */
-DEFINE_BITFIELD(SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 3, 0)
-DEFINE_BITFIELD(SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 7, 4)
-DEFINE_BITFIELD(SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 19, 16)
-DEFINE_BITFIELD(SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 23, 20)
-
-/* DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY */
-DEFINE_BITFIELD(SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 6, 0)
-
-/* DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY */
-DEFINE_BITFIELD(SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 2, 0)
-DEFINE_BITFIELD(SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 6, 4)
-DEFINE_BITFIELD(SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 18, 16)
-DEFINE_BITFIELD(SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 22, 20)
-
-/* DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY */
-DEFINE_BITFIELD(SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 2, 0)
-DEFINE_BITFIELD(SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 6, 4)
-DEFINE_BITFIELD(SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 18, 16)
-DEFINE_BITFIELD(SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 22, 20)
-
-/* DRAMC_REG_SHU_RX_CG_SET0 */
-DEFINE_BIT(SHU_RX_CG_SET0_DLE_LAST_EXTEND3, 0)
-DEFINE_BIT(SHU_RX_CG_SET0_READ_START_EXTEND3, 1)
-DEFINE_BIT(SHU_RX_CG_SET0_DLE_LAST_EXTEND2, 2)
-DEFINE_BIT(SHU_RX_CG_SET0_READ_START_EXTEND2, 3)
-DEFINE_BIT(SHU_RX_CG_SET0_DLE_LAST_EXTEND1, 4)
-DEFINE_BIT(SHU_RX_CG_SET0_READ_START_EXTEND1, 5)
-
-/* DDRPHY_REG_MISC_SHU_RK_DQSCAL */
-DEFINE_BITFIELD(MISC_SHU_RK_DQSCAL_DQSIENLLMT, 6, 0)
-DEFINE_BIT(MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 7)
-DEFINE_BITFIELD(MISC_SHU_RK_DQSCAL_DQSIENHLMT, 14, 8)
-DEFINE_BIT(MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 15)
-
-/* DDRPHY_REG_SHU_R0_B0_INI_UIPI */
-DEFINE_BITFIELD(SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 6, 0)
-DEFINE_BITFIELD(SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 15, 8)
-
-/* DDRPHY_REG_SHU_R0_B1_INI_UIPI */
-DEFINE_BITFIELD(SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 6, 0)
-DEFINE_BITFIELD(SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 15, 8)
-
-/* DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI */
-DEFINE_BITFIELD(SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 6, 0)
-DEFINE_BITFIELD(SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 15, 8)
-DEFINE_BITFIELD(SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 31, 24)
-
-/* DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI */
-DEFINE_BITFIELD(SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 6, 0)
-DEFINE_BITFIELD(SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 15, 8)
-DEFINE_BITFIELD(SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 31, 24)
-
-/* DDRPHY_REG_SHU_R0_B0_DQ0 */
-DEFINE_BITFIELD(SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 2, 0)
-DEFINE_BITFIELD(SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 6, 4)
-DEFINE_BITFIELD(SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 13, 8)
-DEFINE_BITFIELD(SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 21, 16)
-DEFINE_BITFIELD(SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 29, 24)
-DEFINE_BIT(SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 30)
-DEFINE_BIT(SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 31)
-
-/* DDRPHY_REG_SHU_R0_B1_DQ0 */
-DEFINE_BITFIELD(SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 2, 0)
-DEFINE_BITFIELD(SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 6, 4)
-DEFINE_BITFIELD(SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 13, 8)
-DEFINE_BITFIELD(SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 21, 16)
-DEFINE_BITFIELD(SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 29, 24)
-DEFINE_BIT(SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 30)
-DEFINE_BIT(SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 31)
-
-/* DRAMC_REG_SHU_APHY_TX_PICG_CTRL */
-DEFINE_BITFIELD(SHU_APHY_TX_PICG_CTRL_TX_PICG_CNT, 3, 0)
-DEFINE_BITFIELD(SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P1, 6, 4)
-DEFINE_BITFIELD(SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P0, 10, 8)
-DEFINE_BITFIELD(SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT, 15, 12)
-DEFINE_BIT(SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 31)
-
-/* DRAMC_REG_SHURK_APHY_TX_PICG_CTRL */
-DEFINE_BITFIELD(SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 2, 0)
-DEFINE_BITFIELD(SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 6, 4)
-
-/* DRAMC_REG_SHU_NEW_XRW2W_CTRL */
-DEFINE_BITFIELD(SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0, 18, 16)
-DEFINE_BITFIELD(SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1, 26, 24)
-DEFINE_BIT(SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE, 31)
-
-/* DRAMC_REG_SHU_SELPH_DQS0 */
-DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_DQS0, 2, 0)
-DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_DQS1, 6, 4)
-DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_DQS2, 10, 8)
-DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_DQS3, 14, 12)
-DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_OEN_DQS0, 18, 16)
-DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_OEN_DQS1, 22, 20)
-DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_OEN_DQS2, 26, 24)
-DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_OEN_DQS3, 30, 28)
-
-/* DRAMC_REG_SHURK_SELPH_DQ0 */
-DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_DQ0, 2, 0)
-DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_DQ1, 6, 4)
-DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_DQ2, 10, 8)
-DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_DQ3, 14, 12)
-DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 18, 16)
-DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 22, 20)
-DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 26, 24)
-DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 30, 28)
-
-/* DRAMC_REG_SHURK_SELPH_DQ1 */
-DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_DQM0, 2, 0)
-DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_DQM1, 6, 4)
-DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_DQM2, 10, 8)
-DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_DQM3, 14, 12)
-DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 18, 16)
-DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 22, 20)
-DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 26, 24)
-DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 30, 28)
-
-/* DRAMC_REG_SHURK_SELPH_DQ2 */
-DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_DQ0, 3, 0)
-DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_DQ1, 7, 4)
-DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_DQ2, 11, 8)
-DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_DQ3, 15, 12)
-DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_OEN_DQ0, 19, 16)
-DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_OEN_DQ1, 23, 20)
-DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_OEN_DQ2, 27, 24)
-DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_OEN_DQ3, 31, 28)
-
-/* DRAMC_REG_SHURK_SELPH_DQ3 */
-DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_DQM0, 3, 0)
-DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_DQM1, 7, 4)
-DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_DQM2, 11, 8)
-DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_DQM3, 15, 12)
-DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_OEN_DQM0, 19, 16)
-DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_OEN_DQM1, 23, 20)
-DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_OEN_DQM2, 27, 24)
-DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_OEN_DQM3, 31, 28)
-
-/* DRAMC_REG_SHURK_DQS2DQ_CAL1 */
-DEFINE_BITFIELD(SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 10, 0)
-DEFINE_BITFIELD(SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 26, 16)
-
-/* DRAMC_REG_SHURK_DQS2DQ_CAL2 */
-DEFINE_BITFIELD(SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 10, 0)
-DEFINE_BITFIELD(SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 26, 16)
-
-/* DRAMC_REG_SHURK_DQS2DQ_CAL5 */
-DEFINE_BITFIELD(SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 10, 0)
-DEFINE_BITFIELD(SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 26, 16)
-
-/* DRAMC_REG_SHURK_PI */
-DEFINE_BITFIELD(SHURK_PI_RK0_ARPI_DQ_B1, 5, 0)
-DEFINE_BITFIELD(SHURK_PI_RK0_ARPI_DQ_B0, 13, 8)
-DEFINE_BITFIELD(SHURK_PI_RK0_ARPI_DQM_B1, 21, 16)
-DEFINE_BITFIELD(SHURK_PI_RK0_ARPI_DQM_B0, 29, 24)
-
-/* DDRPHY_REG_SHU_R0_B0_TXDLY0 */
-DEFINE_BITFIELD(SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 7, 0)
-DEFINE_BITFIELD(SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 15, 8)
-DEFINE_BITFIELD(SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 23, 16)
-DEFINE_BITFIELD(SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 31, 24)
-
-/* DDRPHY_REG_SHU_R0_B0_TXDLY1 */
-DEFINE_BITFIELD(SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 7, 0)
-DEFINE_BITFIELD(SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 15, 8)
-DEFINE_BITFIELD(SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 23, 16)
-DEFINE_BITFIELD(SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 31, 24)
-
-/* DDRPHY_REG_SHU_R0_B0_TXDLY3 */
-DEFINE_BITFIELD(SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 7, 0)
-DEFINE_BITFIELD(SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 23, 16)
-DEFINE_BITFIELD(SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 31, 24)
-
-/* DDRPHY_REG_SHU_R0_B1_TXDLY0 */
-DEFINE_BITFIELD(SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 7, 0)
-DEFINE_BITFIELD(SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 15, 8)
-DEFINE_BITFIELD(SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 23, 16)
-DEFINE_BITFIELD(SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 31, 24)
-
-/* DDRPHY_REG_SHU_R0_B1_TXDLY1 */
-DEFINE_BITFIELD(SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 7, 0)
-DEFINE_BITFIELD(SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 15, 8)
-DEFINE_BITFIELD(SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 23, 16)
-DEFINE_BITFIELD(SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 31, 24)
-
-/* DDRPHY_REG_SHU_R0_B1_TXDLY3 */
-DEFINE_BITFIELD(SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 7, 0)
-DEFINE_BITFIELD(SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 23, 16)
-DEFINE_BITFIELD(SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 31, 24)
-
-/* DRAMC_REG_SHU_SREF_CTRL */
-DEFINE_BITFIELD(SHU_SREF_CTRL_CKEHCMD, 5, 4)
-DEFINE_BITFIELD(SHU_SREF_CTRL_SREF_CK_DLY, 29, 28)
-
-/* DRAMC_REG_SHU_HMR4_DVFS_CTRL0 */
-DEFINE_BITFIELD(SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT, 15, 8)
-DEFINE_BITFIELD(SHU_HMR4_DVFS_CTRL0_REFRCNT, 27, 16)
-
-/* DDRPHY_REG_SHU_B0_DQ5 */
-DEFINE_BITFIELD(SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0, 5, 0)
-DEFINE_BIT(SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0, 6)
-DEFINE_BITFIELD(SHU_B0_DQ5_RG_ARPI_FB_B0, 13, 8)
-DEFINE_BITFIELD(SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0, 18, 16)
-DEFINE_BIT(SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0, 19)
-DEFINE_BITFIELD(SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0, 23, 20)
-DEFINE_BITFIELD(SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0, 31, 29)
-
-/* DDRPHY_REG_SHU_B1_DQ5 */
-DEFINE_BITFIELD(SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1, 5, 0)
-DEFINE_BIT(SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1, 6)
-DEFINE_BITFIELD(SHU_B1_DQ5_RG_ARPI_FB_B1, 13, 8)
-DEFINE_BITFIELD(SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1, 18, 16)
-DEFINE_BIT(SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1, 19)
-DEFINE_BITFIELD(SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1, 23, 20)
-DEFINE_BITFIELD(SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1, 31, 29)
-
-/* DDRPHY_REG_SHU_R0_B0_RXDLY0 */
-DEFINE_BITFIELD(SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 7, 0)
-DEFINE_BITFIELD(SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 15, 8)
-DEFINE_BITFIELD(SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 23, 16)
-DEFINE_BITFIELD(SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 31, 24)
-
-/* DDRPHY_REG_SHU_R0_B0_RXDLY1 */
-DEFINE_BITFIELD(SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 7, 0)
-DEFINE_BITFIELD(SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 15, 8)
-DEFINE_BITFIELD(SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 23, 16)
-DEFINE_BITFIELD(SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 31, 24)
-
-/* DDRPHY_REG_SHU_R0_B0_RXDLY2 */
-DEFINE_BITFIELD(SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 7, 0)
-DEFINE_BITFIELD(SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 15, 8)
-DEFINE_BITFIELD(SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 23, 16)
-DEFINE_BITFIELD(SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 31, 24)
-
-/* DDRPHY_REG_SHU_R0_B0_RXDLY3 */
-DEFINE_BITFIELD(SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 7, 0)
-DEFINE_BITFIELD(SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 15, 8)
-DEFINE_BITFIELD(SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 23, 16)
-DEFINE_BITFIELD(SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 31, 24)
-
-/* DDRPHY_REG_SHU_R0_B0_RXDLY4 */
-DEFINE_BITFIELD(SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 7, 0)
-DEFINE_BITFIELD(SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 15, 8)
-
-/* DDRPHY_REG_SHU_R0_B0_RXDLY5 */
-DEFINE_BITFIELD(SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 8, 0)
-DEFINE_BITFIELD(SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 24, 16)
-
-/* DDRPHY_REG_SHU_R0_B1_RXDLY0 */
-DEFINE_BITFIELD(SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 7, 0)
-DEFINE_BITFIELD(SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 15, 8)
-DEFINE_BITFIELD(SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 23, 16)
-DEFINE_BITFIELD(SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 31, 24)
-
-/* DDRPHY_REG_SHU_R0_B1_RXDLY1 */
-DEFINE_BITFIELD(SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 7, 0)
-DEFINE_BITFIELD(SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 15, 8)
-DEFINE_BITFIELD(SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 23, 16)
-DEFINE_BITFIELD(SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 31, 24)
-
-/* DDRPHY_REG_SHU_R0_B1_RXDLY2 */
-DEFINE_BITFIELD(SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 7, 0)
-DEFINE_BITFIELD(SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 15, 8)
-DEFINE_BITFIELD(SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 23, 16)
-DEFINE_BITFIELD(SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 31, 24)
-
-/* DDRPHY_REG_SHU_R0_B1_RXDLY3 */
-DEFINE_BITFIELD(SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 7, 0)
-DEFINE_BITFIELD(SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 15, 8)
-DEFINE_BITFIELD(SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 23, 16)
-DEFINE_BITFIELD(SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 31, 24)
-
-/* DDRPHY_REG_SHU_R0_B1_RXDLY4 */
-DEFINE_BITFIELD(SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 7, 0)
-DEFINE_BITFIELD(SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 15, 8)
-
-/* DDRPHY_REG_SHU_R0_B1_RXDLY5 */
-DEFINE_BITFIELD(SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 8, 0)
-DEFINE_BITFIELD(SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 24, 16)
-
-/* DDRPHY_REG_B0_DQ4 */
-DEFINE_BITFIELD(B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0, 6, 0)
-DEFINE_BITFIELD(B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0, 14, 8)
-DEFINE_BITFIELD(B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0, 21, 16)
-DEFINE_BITFIELD(B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0, 29, 24)
-
-/* DDRPHY_REG_B1_DQ4 */
-DEFINE_BITFIELD(B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1, 6, 0)
-DEFINE_BITFIELD(B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1, 14, 8)
-DEFINE_BITFIELD(B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1, 21, 16)
-DEFINE_BITFIELD(B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1, 29, 24)
-
-/* DDRPHY_REG_SHU_R0_CA_CMD0 */
-DEFINE_BITFIELD(SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY, 2, 0)
-DEFINE_BITFIELD(SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY, 6, 4)
-DEFINE_BITFIELD(SHU_R0_CA_CMD0_RG_ARPI_CS, 13, 8)
-DEFINE_BITFIELD(SHU_R0_CA_CMD0_RG_ARPI_CMD, 21, 16)
-DEFINE_BITFIELD(SHU_R0_CA_CMD0_RG_ARPI_CLK, 29, 24)
-DEFINE_BIT(SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA, 30)
-DEFINE_BIT(SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA, 31)
-
-/* DRAMC_REG_SHU_SELPH_DQS1 */
-DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_DQS0, 3, 0)
-DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_DQS1, 7, 4)
-DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_DQS2, 11, 8)
-DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_DQS3, 15, 12)
-DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_OEN_DQS0, 19, 16)
-DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_OEN_DQS1, 23, 20)
-DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_OEN_DQS2, 27, 24)
-DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_OEN_DQS3, 31, 28)
-
-/* DDRPHY_REG_MISC_RX_AUTOK_CFG0 */
-DEFINE_BIT(MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN, 3)
-
-/* DDRPHY_REG_SHU_CA_CMD8 */
-DEFINE_BIT(SHU_CA_CMD8_R_RMRODTEN_CG_IG_CA, 20)
-DEFINE_BIT(SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA, 21)
-DEFINE_BIT(SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA, 26)
-DEFINE_BIT(SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA, 27)
-DEFINE_BIT(SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA, 28)
-DEFINE_BIT(SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA, 29)
-DEFINE_BIT(SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA, 30)
-DEFINE_BIT(SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA, 31)
-
-/* DRAMC_REG_MRR_BIT_MUX1 */
-DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT0_SEL, 4, 0)
-DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT1_SEL, 12, 8)
-DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT2_SEL, 20, 16)
-DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT3_SEL, 28, 24)
-
-/* DRAMC_REG_MRR_BIT_MUX2 */
-DEFINE_BITFIELD(MRR_BIT_MUX2_MRR_BIT4_SEL, 4, 0)
-DEFINE_BITFIELD(MRR_BIT_MUX2_MRR_BIT5_SEL, 12, 8)
-DEFINE_BITFIELD(MRR_BIT_MUX2_MRR_BIT6_SEL, 20, 16)
-DEFINE_BITFIELD(MRR_BIT_MUX2_MRR_BIT7_SEL, 28, 24)
-
-/* DRAMC_REG_MRR_BIT_MUX3 */
-DEFINE_BITFIELD(MRR_BIT_MUX3_MRR_BIT8_SEL, 4, 0)
-DEFINE_BITFIELD(MRR_BIT_MUX3_MRR_BIT9_SEL, 12, 8)
-DEFINE_BITFIELD(MRR_BIT_MUX3_MRR_BIT10_SEL, 20, 16)
-DEFINE_BITFIELD(MRR_BIT_MUX3_MRR_BIT11_SEL, 28, 24)
-
-/* DRAMC_REG_MRR_BIT_MUX4 */
-DEFINE_BITFIELD(MRR_BIT_MUX4_MRR_BIT12_SEL, 4, 0)
-DEFINE_BITFIELD(MRR_BIT_MUX4_MRR_BIT13_SEL, 12, 8)
-DEFINE_BITFIELD(MRR_BIT_MUX4_MRR_BIT14_SEL, 20, 16)
-DEFINE_BITFIELD(MRR_BIT_MUX4_MRR_BIT15_SEL, 28, 24)
-
-/* DDRPHY_REG_MISC_DQ_SE_PINMUX_CTRL0 */
-DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ0, 3, 0)
-DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ1, 7, 4)
-DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ2, 11, 8)
-DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ3, 15, 12)
-DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ4, 19, 16)
-DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ5, 23, 20)
-DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ6, 27, 24)
-DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ7, 31, 28)
-
-/* DDRPHY_REG_MISC_DQ_SE_PINMUX_CTRL1 */
-DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ8, 3, 0)
-DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ9, 7, 4)
-DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ10, 11, 8)
-DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ11, 15, 12)
-DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ12, 19, 16)
-DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ13, 23, 20)
-DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ14, 27, 24)
-DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ15, 31, 28)
-
-/* DRAMC_REG_SA_RESERVE */
-DEFINE_BIT(SA_RESERVE_SINGLE_RANK, 0)
-DEFINE_BITFIELD(SA_RESERVE_MODE_RK1, 27, 24)
-DEFINE_BITFIELD(SA_RESERVE_MODE_RK0, 31, 28)
-
-/* DRAMC_REG_SWCMD_CTRL0 */
-DEFINE_BITFIELD(SWCMD_CTRL0_MRSOP, 7, 0)
-DEFINE_BITFIELD(SWCMD_CTRL0_MRSMA, 20, 8)
-DEFINE_BITFIELD(SWCMD_CTRL0_MRSRK, 25, 24)
-DEFINE_BIT(SWCMD_CTRL0_SWTRIG_ZQ_RK, 30)
-
-/* DRAMC_REG_DRAMC_IRQ_EN */
-DEFINE_BIT(DRAMC_IRQ_EN_MR4INT_EN, 0)
-DEFINE_BITFIELD(DRAMC_IRQ_EN_DRAMC_IRQ_EN_RSV, 31, 18)
-
-/* DDRPHY_REG_CA_TX_MCK */
-DEFINE_BITFIELD(CA_TX_MCK_R_DMRESETB_DRVP_FRPHY, 25, 21)
-DEFINE_BITFIELD(CA_TX_MCK_R_DMRESETB_DRVN_FRPHY, 30, 26)
-DEFINE_BIT(CA_TX_MCK_R_DMRESET_FRPHY_OPT, 31)
-
-/* DDRPHY_REG_MISC_IMPCAL */
-DEFINE_BIT(MISC_IMPCAL_DRVCGWREF, 2)
-DEFINE_BIT(MISC_IMPCAL_DQDRVSWUPD, 3)
-DEFINE_BIT(MISC_IMPCAL_IMPSRCEXT, 4)
-DEFINE_BIT(MISC_IMPCAL_IMPBINARY, 5)
-DEFINE_BIT(MISC_IMPCAL_DRV_ECO_OPT, 10)
-DEFINE_BIT(MISC_IMPCAL_IMPCAL_CHGDRV_ECO_OPT, 11)
-DEFINE_BIT(MISC_IMPCAL_IMPCAL_SM_ECO_OPT, 12)
-DEFINE_BIT(MISC_IMPCAL_IMPCAL_ECO_OPT, 13)
-DEFINE_BIT(MISC_IMPCAL_DIS_SUS_CH1_DRV, 14)
-DEFINE_BIT(MISC_IMPCAL_DIS_SUS_CH0_DRV, 15)
-DEFINE_BIT(MISC_IMPCAL_IMPCAL_DRVUPDOPT, 17)
-DEFINE_BIT(MISC_IMPCAL_IMPCAL_BYPASS_UP_CA_DRV, 19)
-DEFINE_BIT(MISC_IMPCAL_IMPCAL_HWSAVE_EN, 20)
-DEFINE_BIT(MISC_IMPCAL_IMPCAL_CALI_ENN, 21)
-DEFINE_BIT(MISC_IMPCAL_IMPCAL_CALI_ENP, 22)
-DEFINE_BIT(MISC_IMPCAL_IMPCAL_CALI_EN, 23)
-DEFINE_BIT(MISC_IMPCAL_IMPCAL_IMPPDN, 24)
-DEFINE_BIT(MISC_IMPCAL_IMPCAL_IMPPDP, 25)
-DEFINE_BIT(MISC_IMPCAL_IMPCAL_NEW_OLD_SL, 26)
-DEFINE_BIT(MISC_IMPCAL_IMPCAL_SWVALUE_EN, 29)
-DEFINE_BIT(MISC_IMPCAL_IMPCAL_EN, 30)
-DEFINE_BIT(MISC_IMPCAL_IMPCAL_HW, 31)
-
-/* DDRPHY_REG_SHU_B0_DLL2 */
-DEFINE_BITFIELD(SHU_B0_DLL2_RG_ARDQ_REV_B0, 31, 0)
-
-/* DDRPHY_REG_SHU_B1_DLL2 */
-DEFINE_BITFIELD(SHU_B1_DLL2_RG_ARDQ_REV_B1, 31, 0)
-
-/* DDRPHY_REG_SHU_CA_DLL2 */
-DEFINE_BITFIELD(SHU_CA_DLL2_RG_ARCMD_REV, 31, 0)
-
-/* DRAMC_REG_DRAMC_DBG_SEL1 */
-DEFINE_BITFIELD(DRAMC_DBG_SEL1_DEBUG_SEL_0, 15, 0)
-
-/* DRAMC_REG_SWCMD_CTRL2 */
-DEFINE_BITFIELD(SWCMD_CTRL2_RTSWCMD_AGE, 9, 0)
-
-/* DRAMC_REG_RTMRW_CTRL0 */
-DEFINE_BITFIELD(RTMRW_CTRL0_RTMRW_AGE, 24, 15)
-
-/* DRAMC_REG_REF_BOUNCE1 */
-DEFINE_BITFIELD(REF_BOUNCE1_REFRATE_DEBOUNCE_COUNT, 7, 0)
-DEFINE_BITFIELD(REF_BOUNCE1_REFRATE_DEBOUNCE_TH, 12, 8)
-DEFINE_BIT(REF_BOUNCE1_REFRATE_DEBOUNCE_OPT, 13)
-DEFINE_BITFIELD(REF_BOUNCE1_REFRATE_DEBOUNCE_DIS, 31, 16)
-
-/* DRAMC_REG_REFPEND2 */
-DEFINE_BITFIELD(REFPEND2_MPENDREFCNT_TH8, 3, 0)
-
-/* DRAMC_REG_RTSWCMD_CNT */
-DEFINE_BITFIELD(RTSWCMD_CNT_RTSWCMD_CNT, 31, 0)
-
-/* DDRPHY_REG_B0_DLL_ARPI4 */
-DEFINE_BIT(B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B0, 8)
-DEFINE_BIT(B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B0, 9)
-
-/* DDRPHY_REG_B1_DLL_ARPI4 */
-DEFINE_BIT(B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B1, 8)
-DEFINE_BIT(B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B1, 9)
-
-/* DDRPHY_REG_CA_DLL_ARPI4 */
-DEFINE_BIT(CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CA_CA, 8)
-DEFINE_BIT(CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CLK_CA, 9)
-
-/* DDRPHY_REG_MISC_DDR_RESERVE */
-DEFINE_BITFIELD(MISC_DDR_RESERVE_WDT_CONF_ISO_CNT, 7, 0)
-DEFINE_BIT(MISC_DDR_RESERVE_WDT_SM_CLR, 24)
-DEFINE_BIT(MISC_DDR_RESERVE_WDT_LITE_EN, 25)
-
-/* DDRPHY_REG_MISC_CTRL6 */
-DEFINE_BIT(MISC_CTRL6_RG_PHDET_EN_SHU_OPT, 0)
-DEFINE_BIT(MISC_CTRL6_RG_ADA_MCK8X_EN_SHU_OPT, 1)
-
-/* DRAMC_REG_REF_BOUNCE2 */
-DEFINE_BITFIELD(REF_BOUNCE2_PRE_MR4INT_TH, 4, 0)
-
-/* DRAMC_REG_SHU_REF0 */
-DEFINE_BITFIELD(SHU_REF0_MPENDREF_CNT, 2, 0)
-
-/* DRAMC_REG_ZQ_SET1 */
-DEFINE_BIT(ZQ_SET1_ZQCALDISB, 30)
-
-/* DRAMC_REG_TX_RETRY_SET0 */
-DEFINE_BIT(TX_RETRY_SET0_XSR_TX_RETRY_BLOCK_ALE_MASK, 0)
-DEFINE_BIT(TX_RETRY_SET0_XSR_TX_RETRY_EN, 2)
-DEFINE_BIT(TX_RETRY_SET0_XSR_TX_RETRY_SW_EN, 4)
-
-/* DRAMC_REG_SPCMDRESP */
-DEFINE_BIT(SPCMDRESP_MRR_RESPONSE, 1)
-DEFINE_BIT(SPCMDRESP_RDDQC_RESPONSE, 7)
-DEFINE_BIT(SPCMDRESP_TX_RETRY_DONE_RESPONSE, 15)
-
-/* DDRPHY_REG_SHU_B0_VREF */
-DEFINE_BIT(SHU_B0_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B0, 16)
-DEFINE_BIT(SHU_B0_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B0, 22)
-
-/* DDRPHY_REG_SHU_B1_VREF */
-DEFINE_BIT(SHU_B1_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B1, 16)
-DEFINE_BIT(SHU_B1_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B1, 22)
-
-/* DDRPHY_REG_SHU_B0_PHY_VREF_SEL */
-DEFINE_BITFIELD(RG_RX_ARDQ_VREF_SEL_LB_B0, 6, 0)
-DEFINE_BITFIELD(RG_RX_ARDQ_VREF_SEL_UB_B0, 14, 8)
-
-/* DDRPHY_REG_SHU_B1_PHY_VREF_SEL */
-DEFINE_BITFIELD(RG_RX_ARDQ_VREF_SEL_LB_B1, 6, 0)
-DEFINE_BITFIELD(RG_RX_ARDQ_VREF_SEL_UB_B1, 14, 8)
-
-/* DDRPHY_REG_SHU_MISC_DRVING1 */
-DEFINE_BITFIELD(SHU_MISC_DRVING1_DQDRVN2, 4, 0)
-DEFINE_BITFIELD(SHU_MISC_DRVING1_DQDRVP2, 9, 5)
-DEFINE_BITFIELD(SHU_MISC_DRVING1_DQSDRVN1, 14, 10)
-DEFINE_BITFIELD(SHU_MISC_DRVING1_DQSDRVP1, 19, 15)
-DEFINE_BITFIELD(SHU_MISC_DRVING1_DQSDRVN2, 24, 20)
-DEFINE_BITFIELD(SHU_MISC_DRVING1_DQSDRVP2, 29, 25)
-DEFINE_BIT(SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK, 30)
-DEFINE_BIT(SHU_MISC_DRVING1_DIS_IMPCAL_HW, 31)
-
-/* DRAMC_REG_SHU_ZQ_SET0 */
-DEFINE_BITFIELD(SHU_ZQ_SET0_ZQCSCNT, 15, 0)
-DEFINE_BITFIELD(SHU_ZQ_SET0_TZQLAT, 31, 27)
-
-/* DRAMC_REG_DCM_SUB_CTRL */
-DEFINE_BIT(DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING, 1)
-DEFINE_BIT(DCM_SUB_CTRL_SUBCLK_CTRL_TX_AUTOK, 12)
-
-/* DDRPHY_REG_B0_PHY3 */
-DEFINE_BIT(B0_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B0, 28)
-
-/* DDRPHY_REG_B1_PHY3 */
-DEFINE_BIT(B1_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B1, 28)
-
-/* DRAMC_REG_CBT_WLEV_CTRL5 */
-DEFINE_BITFIELD(CBT_WLEV_CTRL5_NEW_CBT_PAT_INTV, 11, 4)
-
-/* DRAMC_REG_CBT_WLEV_CTRL0 */
-DEFINE_BIT(CBT_WLEV_CTRL0_BYTEMODECBTEN, 2)
-DEFINE_BIT(CBT_WLEV_CTRL0_WRITE_LEVEL_EN, 3)
-DEFINE_BIT(CBT_WLEV_CTRL0_DQSOEAOEN, 4)
-DEFINE_BIT(CBT_WLEV_CTRL0_CBT_WLEV_DQS_TRIG, 7)
-DEFINE_BITFIELD(CBT_WLEV_CTRL0_CBT_WLEV_DQS_SEL, 11, 8)
-DEFINE_BITFIELD(CBT_WLEV_CTRL0_WLEV_DQSPAT_LAT, 19, 12)
-DEFINE_BITFIELD(CBT_WLEV_CTRL0_CBT_DQBYTE_OEAO_EN, 29, 26)
-DEFINE_BIT(CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE, 30)
-
-/* DRAMC_REG_SHU_LP5_CMD */
-DEFINE_BIT(SHU_LP5_CMD_LP5_CMD1TO2EN, 0)
-
-/* DDRPHY_REG_SHU_R0_CA_TXDLY0 */
-DEFINE_BITFIELD(SHU_R0_CA_TXDLY0_TX_ARCA0_DLY, 7, 0)
-DEFINE_BITFIELD(SHU_R0_CA_TXDLY0_TX_ARCA1_DLY, 15, 8)
-DEFINE_BITFIELD(SHU_R0_CA_TXDLY0_TX_ARCA2_DLY, 23, 16)
-DEFINE_BITFIELD(SHU_R0_CA_TXDLY0_TX_ARCA3_DLY, 31, 24)
-
-/* DDRPHY_REG_SHU_R0_CA_TXDLY1 */
-DEFINE_BITFIELD(SHU_R0_CA_TXDLY1_TX_ARCA4_DLY, 7, 0)
-DEFINE_BITFIELD(SHU_R0_CA_TXDLY1_TX_ARCA5_DLY, 15, 8)
-DEFINE_BITFIELD(SHU_R0_CA_TXDLY1_TX_ARCA6_DLY, 23, 16)
-DEFINE_BITFIELD(SHU_R0_CA_TXDLY1_TX_ARCA7_DLY, 31, 24)
-
-/* DRAMC_REG_CBT_WLEV_CTRL4 */
-DEFINE_BITFIELD(CBT_WLEV_CTRL4_CBT_TXDQ_B0, 7, 0)
-DEFINE_BITFIELD(CBT_WLEV_CTRL4_CBT_TXDQ_B1, 15, 8)
-
-/* DRAMC_REG_CBT_WLEV_CTRL3 */
-DEFINE_BITFIELD(CBT_WLEV_CTRL3_DQSBX_G, 17, 14)
-
-/* DRAMC_REG_SWCMD_EN */
-DEFINE_BIT(SWCMD_EN_RDDQCEN, 5)
-DEFINE_BIT(SWCMD_EN_MRWEN, 11)
-DEFINE_BIT(SWCMD_EN_MRREN, 12)
-DEFINE_BIT(SWCMD_EN_ZQCEN_SWTRIG, 16)
-DEFINE_BIT(SWCMD_EN_ZQLATEN_SWTRIG, 17)
-DEFINE_BIT(SWCMD_EN_WCK2DQI_START_SWTRIG, 18)
-
-/* DRAMC_REG_SPCMDRESP3 */
-DEFINE_BIT(SPCMDRESP3_ZQC_SWTRIG_RESPONSE, 1)
-DEFINE_BIT(SPCMDRESP3_ZQLAT_SWTRIG_RESPONSE, 2)
-DEFINE_BIT(SPCMDRESP3_WCK2DQI_START_SWTRIG_RESPONSE, 3)
-
-/* DDRPHY_REG_SHU_B0_RANK_SELPH_UI_DLY */
-DEFINE_BITFIELD(SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B0, 18, 16)
-DEFINE_BITFIELD(SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B0, 22, 20)
-
-/* DDRPHY_REG_SHU_B1_RANK_SELPH_UI_DLY */
-DEFINE_BITFIELD(SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B1, 18, 16)
-DEFINE_BITFIELD(SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B1, 22, 20)
-
-/* DRAMC_REG_RDDQCGOLDEN */
-DEFINE_BITFIELD(RDDQCGOLDEN_MR20_GOLDEN, 7, 0)
-DEFINE_BITFIELD(RDDQCGOLDEN_MR15_GOLDEN, 15, 8)
-DEFINE_BITFIELD(RDDQCGOLDEN_MR40_GOLDEN, 23, 16)
-DEFINE_BITFIELD(RDDQCGOLDEN_MR32_GOLDEN, 31, 24)
-
-/* DDRPHY_REG_MISC_JMETER */
-DEFINE_BIT(MISC_JMETER_JMTR_EN, 0)
-
-/* DDRPHY_REG_MISC_DUTY_TOGGLE_CNT */
-DEFINE_BITFIELD(MISC_DUTY_TOGGLE_CNT_TOGGLE_CNT, 31, 0)
-
-/* DDRPHY_REG_MISC_DUTY_DQS0_ERR_CNT */
-DEFINE_BITFIELD(MISC_DUTY_DQS0_ERR_CNT_DQS0_ERR_CNT, 31, 0)
-
-/* DDRPHY_REG_DVFS_STATUS */
-DEFINE_BITFIELD(DVFS_STATUS_OTHER_SHU_GP, 17, 16)
-
-/* DDRPHY_REG_SHU_MISC_DRVING3 */
-DEFINE_BITFIELD(SHU_MISC_DRVING3_DQODTN2, 4, 0)
-DEFINE_BITFIELD(SHU_MISC_DRVING3_DQODTP2, 9, 5)
-DEFINE_BITFIELD(SHU_MISC_DRVING3_DQSODTN, 14, 10)
-DEFINE_BITFIELD(SHU_MISC_DRVING3_DQSODTP, 19, 15)
-DEFINE_BITFIELD(SHU_MISC_DRVING3_DQSODTN2, 24, 20)
-DEFINE_BITFIELD(SHU_MISC_DRVING3_DQSODTP2, 29, 25)
-
-/* DDRPHY_REG_SHU_MISC_DRVING4 */
-DEFINE_BITFIELD(SHU_MISC_DRVING4_CMDODTN1, 4, 0)
-DEFINE_BITFIELD(SHU_MISC_DRVING4_CMDODTP1, 9, 5)
-DEFINE_BITFIELD(SHU_MISC_DRVING4_CMDODTN2, 14, 10)
-DEFINE_BITFIELD(SHU_MISC_DRVING4_CMDODTP2, 19, 15)
-DEFINE_BITFIELD(SHU_MISC_DRVING4_DQODTN1, 24, 20)
-DEFINE_BITFIELD(SHU_MISC_DRVING4_DQODTP1, 29, 25)
-
-/* DDRPHY_REG_MISC_SHU_DRVING8 */
-DEFINE_BITFIELD(MISC_SHU_DRVING8_CS_DRVN, 4, 0)
-DEFINE_BITFIELD(MISC_SHU_DRVING8_CS_DRVP, 12, 8)
-
-/* DDRPHY_REG_MISC_PHY_RGS_CMD */
-DEFINE_BIT(MISC_PHY_RGS_CMD_RGS_RIMPCALOUT, 24)
-
-/* DDRPHY_REG_SHU_CA_TXDUTY */
-DEFINE_BITFIELD(SHU_CA_TXDUTY_DA_TX_ARCLK_DUTY_DLY, 13, 8)
-
-/* DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_TXDUTY */
-DEFINE_BITFIELD(SHU_B0_TXDUTY_DA_TX_ARDQ_DUTY_DLY_B0, 5, 0)
-DEFINE_BITFIELD(SHU_B0_TXDUTY_DA_TX_ARDQS_DUTY_DLY_B0, 13, 8)
-DEFINE_BITFIELD(SHU_B0_TXDUTY_DA_TX_ARDQM_DUTY_DLY_B0, 21, 16)
-DEFINE_BITFIELD(SHU_B0_TXDUTY_DA_TX_ARWCK_DUTY_DLY_B0, 29, 24)
-
-/* DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A3 */
-DEFINE_BITFIELD(TEST2_A3_TESTCNT, 3, 0)
-
-/* DRAMC_REG_SHU_DQSOSC_SET0 */
-DEFINE_BIT(SHU_DQSOSC_SET0_DQSOSCENDIS, 0)
-DEFINE_BITFIELD(SHU_DQSOSC_SET0_DQSOSC_PRDCNT, 13, 4)
-DEFINE_BITFIELD(SHU_DQSOSC_SET0_DQSOSCENCNT, 31, 16)
-
-/* DRAMC_REG_SHURK_DQSOSC */
-DEFINE_BITFIELD(SHURK_DQSOSC_DQSOSC_BASE_RK0, 15, 0)
-DEFINE_BITFIELD(SHURK_DQSOSC_DQSOSC_BASE_RK0_B1, 31, 16)
-
-/* DRAMC_REG_SHU_DQSOSCR */
-DEFINE_BITFIELD(SHU_DQSOSCR_DQSOSCRCNT, 7, 0)
-
-/* DRAMC_REG_SHURK_DQSOSC_THRD */
-DEFINE_BITFIELD(SHURK_DQSOSC_THRD_DQSOSCTHRD_INC, 11, 0)
-DEFINE_BITFIELD(SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC, 27, 16)
-
-/* DRAMC_REG_SHU_FREQ_RATIO_SET0 */
-DEFINE_BITFIELD(SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3, 7, 0)
-DEFINE_BITFIELD(SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2, 15, 8)
-DEFINE_BITFIELD(SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1, 23, 16)
-DEFINE_BITFIELD(SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0, 31, 24)
-
-/* DRAMC_REG_SHU_FREQ_RATIO_SET1 */
-DEFINE_BITFIELD(SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO7, 7, 0)
-DEFINE_BITFIELD(SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO6, 15, 8)
-DEFINE_BITFIELD(SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO5, 23, 16)
-DEFINE_BITFIELD(SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO4, 31, 24)
-
-/* DRAMC_REG_SHU_FREQ_RATIO_SET2 */
-DEFINE_BITFIELD(SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO9, 23, 16)
-DEFINE_BITFIELD(SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO8, 31, 24)
-
-/* DDRPHY_REG_SHU_MISC_PRE_TDQSCK */
-DEFINE_BIT(SHU_MISC_PRE_TDQSCK_PRECAL_DISABLE, 0)
-
-/* DDRPHY_REG_MISC_PRE_TDQSCK1 */
-DEFINE_BIT(MISC_PRE_TDQSCK1_TDQSCK_HW_SW_UP_SEL, 22)
-DEFINE_BIT(MISC_PRE_TDQSCK1_TDQSCK_REG_DVFS, 25)
-DEFINE_BIT(MISC_PRE_TDQSCK1_TDQSCK_PRECAL_HW, 26)
-
-/* DRAMC_REG_MISC_STATUSA */
-DEFINE_BIT(MISC_STATUSA_REQQ_EMPTY, 2)
-DEFINE_BITFIELD(MISC_STATUSA_REFRESH_QUEUE_CNT, 27, 24)
-
-/* DRAMC_REG_TEST2_A0 */
-DEFINE_BITFIELD(TEST2_A0_TEST2_PAT1, 7, 0)
-DEFINE_BITFIELD(TEST2_A0_TEST2_PAT0, 15, 8)
-DEFINE_BIT(TEST2_A0_LOOP_NV_END, 16)
-DEFINE_BIT(TEST2_A0_ERR_BREAK_EN, 17)
-DEFINE_BIT(TEST2_A0_TA2_LOOP_EN, 18)
-DEFINE_BITFIELD(TEST2_A0_LOOP_CNT_INDEX, 23, 20)
-
-/* DRAMC_REG_TESTRPT */
-DEFINE_BITFIELD(TESTRPT_TESTSTAT, 22, 20)
-
-/* DRAMC_REG_MRR_STATUS */
-DEFINE_BITFIELD(MRR_STATUS_MRR_SW_REG, 31, 16)
-
-/* DRAMC_REG_SPCMDRESP */
-DEFINE_BIT(SPCMDRESP_MRW_RESPONSE, 0)
-
-/* DRAMC_REG_MISC_STATUSA */
-DEFINE_BITFIELD(MISC_STATUSA_REFRESH_RATE, 12, 8)
-
-/* DDRPHY_REG_SHU_CA_CMD0 */
-DEFINE_BIT(SHU_CA_CMD0_R_LP4Y_WDN_MODE_CLK, 31)
-
-/* DDRPHY_REG_SHU_B0_DQ0 */
-DEFINE_BIT(SHU_B0_DQ0_R_LP4Y_WDN_MODE_DQS0, 31)
-
-/* DDRPHY_REG_SHU_B1_DQ0 */
-DEFINE_BIT(SHU_B1_DQ0_R_LP4Y_WDN_MODE_DQS1, 31)
-
-#endif /* __SOC_MEDIATEK_MT8192_DRAMC_MACRO_DEF_H__ */