soc/intel/icelake: Rename `pch_init()` function

There's two instances of the same function, one for the bootblock and
another for romstage. Prefix them with the stage they are executed in.

Change-Id: I35e87cd47f3cef8952481d25b54558a546aebb60
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50944
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

6 files changed, 6 insertions, 6 deletions

diff --git a/src/soc/intel/icelake/bootblock/bootblock.c b/src/soc/intel/icelake/bootblock/bootblock.c
index 54ad85a82e..9f360daf00 100644
--- a/src/soc/intel/icelake/bootblock/bootblock.c
+++ b/src/soc/intel/icelake/bootblock/bootblock.c
@@ -24,5 +24,5 @@ void bootblock_soc_early_init(void)
 void bootblock_soc_init(void)
 {
 	report_platform_info();
-	pch_init();
+	bootblock_pch_init();
 }
diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c
index a4166fcf67..7694a104e1 100644
--- a/src/soc/intel/icelake/bootblock/pch.c
+++ b/src/soc/intel/icelake/bootblock/pch.c
@@ -109,7 +109,7 @@ void pch_early_iorange_init(void)
 	pch_enable_lpc();
 }
 
-void pch_init(void)
+void bootblock_pch_init(void)
 {
 	/*
 	 * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
diff --git a/src/soc/intel/icelake/include/soc/bootblock.h b/src/soc/intel/icelake/include/soc/bootblock.h
index 0132cfc07e..f22b2665ec 100644
--- a/src/soc/intel/icelake/include/soc/bootblock.h
+++ b/src/soc/intel/icelake/include/soc/bootblock.h
@@ -8,7 +8,7 @@ void bootblock_cpu_init(void);
 void bootblock_pch_early_init(void);
 
 /* Bootblock post console init programming */
-void pch_init(void);
+void bootblock_pch_init(void);
 void pch_early_iorange_init(void);
 void report_platform_info(void);
 
diff --git a/src/soc/intel/icelake/include/soc/romstage.h b/src/soc/intel/icelake/include/soc/romstage.h
index 90a19f20db..3772db4bc1 100644
--- a/src/soc/intel/icelake/include/soc/romstage.h
+++ b/src/soc/intel/icelake/include/soc/romstage.h
@@ -7,7 +7,7 @@
 
 void mainboard_memory_init_params(FSPM_UPD *mupd);
 void systemagent_early_init(void);
-void pch_init(void);
+void romstage_pch_init(void);
 
 /* Board type */
 enum board_type {
diff --git a/src/soc/intel/icelake/romstage/pch.c b/src/soc/intel/icelake/romstage/pch.c
index e800ce50bd..6b134c0681 100644
--- a/src/soc/intel/icelake/romstage/pch.c
+++ b/src/soc/intel/icelake/romstage/pch.c
@@ -4,7 +4,7 @@
 #include <intelblocks/tco.h>
 #include <soc/romstage.h>
 
-void pch_init(void)
+void romstage_pch_init(void)
 {
 	/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
 	tco_configure();
diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c
index 6af2961dfe..15179745bd 100644
--- a/src/soc/intel/icelake/romstage/romstage.c
+++ b/src/soc/intel/icelake/romstage/romstage.c
@@ -111,7 +111,7 @@ void mainboard_romstage_entry(void)
 	/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
 	systemagent_early_init();
 	/* Program PCH init */
-	pch_init();
+	romstage_pch_init();
 	/* initialize Heci interface */
 	heci_init(HECI1_BASE_ADDRESS);