diff options
| author | Nico Huber <nico.huber@secunet.com> | 2017-05-09 16:14:36 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2017-06-06 17:44:09 +0200 |
| commit | 4a47e4b8eedafa3f2099393de1f00365d1846ee5 (patch) | |
| tree | 01bc7b8c057aeca2fa4cd5615b9d8039c7e0d6fb /src/soc | |
| parent | 503965f93960fffd2a3b8ba00af4edc5fd894295 (diff) | |
soc/intel/skylake/chip.h: Reorder declarations
Place `tdp_pl2_override` above the FSP options as it's not an FSP option.
Change-Id: Idff2b628d19ce1a80294b28c55c05ba4157d07e0
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 88d598f9a8..b4f6545c36 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -94,6 +94,9 @@ struct soc_intel_skylake_config { /* TCC activation offset */ int tcc_offset; + /* PL2 Override value in Watts */ + u32 tdp_pl2_override; + /* * The following fields come from FspUpdVpd.h. * These are configuration values that are passed to FSP during @@ -392,8 +395,6 @@ struct soc_intel_skylake_config { * Setting to 0 (default) disables Heci1 and hides the device from OS */ u8 HeciEnabled; - /* PL2 Override value in Watts */ - u32 tdp_pl2_override; u8 PmTimerDisabled; /* Intel Speed Shift Technology */ u8 speed_shift_enable; |