arch/x86/postcar: Set up postcar MTRR in C code

Setting up postcar MTRRs is done when invd is already called so there
is no reason to do this in assembly anymore.

This also drops the custom code for Quark to set up MTRRs.

TESTED on foxconn/g41m and hermes/prodrive that MTRR are properly set
in postcar & ramstage.

Change-Id: I5ec10e84118197a04de0a5194336ef8bb049bba4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54299
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 18 insertions, 91 deletions

diff --git a/src/soc/amd/common/block/cpu/noncar/early_cache.c b/src/soc/amd/common/block/cpu/noncar/early_cache.c
index b9650a96a7..94c8b10272 100644
--- a/src/soc/amd/common/block/cpu/noncar/early_cache.c
+++ b/src/soc/amd/common/block/cpu/noncar/early_cache.c
@@ -1,11 +1,16 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/cpu.h>
+#include <assert.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <soc/iomap.h>
+#include <stdint.h>
+
+/* Allocate a static amount of stack for the MTRR context. */
+#define MAX_VAR_MTRR_USE 10
 
 /*
  * PSP performs the memory training and setting up DRAM map prior to x86 cores being released.
@@ -19,9 +24,15 @@ void early_cache_setup(void)
 	msr_t mtrr_def_type;
 	msr_t fixed_mtrr_ram;
 	msr_t fixed_mtrr_mmio;
-	struct var_mtrr_context mtrr_ctx;
+	union mtrr_ctx {
+		struct var_mtrr_context ctx;
+		char buffer[sizeof(struct var_mtrr_context)
+			    + 2 * MAX_VAR_MTRR_USE * sizeof(msr_t)];
+
+	} mtrr_ctx;
 
-	var_mtrr_context_init(&mtrr_ctx, NULL);
+	var_mtrr_context_init(&mtrr_ctx.ctx);
+	mtrr_ctx.ctx.max_var_mtrrs = MIN(MAX_VAR_MTRR_USE, mtrr_ctx.ctx.max_var_mtrrs);
 	top_mem = rdmsr(TOP_MEM);
 	/* Enable RdDram and WrDram attributes in fixed MTRRs. */
 	sys_cfg = rdmsr(SYSCFG_MSR);
@@ -49,11 +60,11 @@ void early_cache_setup(void)
 
 	wrmsr(SYSCFG_MSR, sys_cfg);
 
-	clear_all_var_mtrr();
-
-	var_mtrr_set(&mtrr_ctx, 0, ALIGN_DOWN(top_mem.lo, 8*MiB), MTRR_TYPE_WRBACK);
+	var_mtrr_set(&mtrr_ctx.ctx, 0, ALIGN_DOWN(top_mem.lo, 8*MiB), MTRR_TYPE_WRBACK);
 	/* TODO: check if we should always mark 16 MByte below 4 GByte as WRPROT */
-	var_mtrr_set(&mtrr_ctx, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
+	var_mtrr_set(&mtrr_ctx.ctx, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
+
+	commit_mtrr_setup(&mtrr_ctx.ctx);
 
 	/* Set up RAM caching for everything below 1MiB except for 0xa0000-0xc0000 . */
 	wrmsr(MTRR_FIX_64K_00000, fixed_mtrr_ram);
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 8ac2eb5a04..a2037fced6 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -121,7 +121,7 @@ asmlinkage void car_stage_entry(void)
 		smm_list_regions();
 
 	post_code(0x44);
-	if (postcar_frame_init(&pcf, 0))
+	if (postcar_frame_init(&pcf))
 		die("Unable to initialize postcar frame.\n");
 
 	/*
diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc
index 8630acb4dd..ff9b2b6743 100644
--- a/src/soc/intel/quark/romstage/Makefile.inc
+++ b/src/soc/intel/quark/romstage/Makefile.inc
@@ -3,10 +3,7 @@
 romstage-y += car.c
 romstage-$(CONFIG_DISPLAY_UPD_DATA) += debug.c
 romstage-y += fsp_params.c
-romstage-y += mtrr.c
 romstage-y += pcie.c
 romstage-y += report_platform.c
 romstage-y += romstage.c
 romstage-y += ../../../../cpu/intel/car/romstage.c
-
-postcar-y += mtrr.c
diff --git a/src/soc/intel/quark/romstage/mtrr.c b/src/soc/intel/quark/romstage/mtrr.c
deleted file mode 100644
index e72ce335d7..0000000000
--- a/src/soc/intel/quark/romstage/mtrr.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <cpu/x86/msr.h>
-#include <cpu/x86/mtrr.h>
-#include <soc/pci_devs.h>
-#include <soc/reg_access.h>
-
-asmlinkage void *soc_set_mtrrs(void *top_of_stack)
-{
-	union {
-		uint32_t u32[2];
-		uint64_t u64;
-		msr_t msr;
-	} data;
-	uint32_t mtrr_count;
-	uint32_t *mtrr_data;
-	uint32_t mtrr_reg;
-
-	/*
-	 * The stack contents are initialized in src/soc/intel/common/stack.c
-	 * to be the following:
-	 *
-	 *				*
-	 *				*
-	 *				*
-	 *		   +36: MTRR mask 1 63:32
-	 *		   +32: MTRR mask 1 31:0
-	 *		   +28: MTRR base 1 63:32
-	 *		   +24: MTRR base 1 31:0
-	 *		   +20: MTRR mask 0 63:32
-	 *		   +16: MTRR mask 0 31:0
-	 *		   +12: MTRR base 0 63:32
-	 *		    +8: MTRR base 0 31:0
-	 *		    +4: Number of MTRRs to setup (described above)
-	 * top_of_stack --> +0: Number of variable MTRRs to clear
-	 *
-	 * This routine:
-	 *	* Clears all of the variable MTRRs
-	 *	* Initializes the variable MTRRs with the data passed in
-	 *	* Returns the new top of stack after removing all of the
-	 *	  data passed in.
-	 */
-
-	/* Clear all of the variable MTRRs (base and mask). */
-	mtrr_reg = MTRR_PHYS_BASE(0);
-	mtrr_data = top_of_stack;
-	mtrr_count = (*mtrr_data++) * 2;
-	data.u64 = 0;
-	while (mtrr_count-- > 0)
-		soc_msr_write(mtrr_reg++, data.msr);
-
-	/* Setup the specified variable MTRRs */
-	mtrr_reg = MTRR_PHYS_BASE(0);
-	mtrr_count = *mtrr_data++;
-	while (mtrr_count-- > 0) {
-		data.u32[0] = *mtrr_data++;
-		data.u32[1] = *mtrr_data++;
-		soc_msr_write(mtrr_reg++, data.msr); /* Base */
-		data.u32[0] = *mtrr_data++;
-		data.u32[1] = *mtrr_data++;
-		soc_msr_write(mtrr_reg++, data.msr); /* Mask */
-	}
-
-	/* Remove setup_stack_and_mtrrs data and return the new top_of_stack */
-	top_of_stack = mtrr_data;
-	return top_of_stack;
-}
-
-asmlinkage void soc_enable_mtrrs(void)
-{
-	union {
-		uint32_t u32[2];
-		uint64_t u64;
-		msr_t msr;
-	} data;
-
-	/* Enable MTRR. */
-	data.msr = soc_msr_read(MTRR_DEF_TYPE_MSR);
-	data.u32[0] |= MTRR_DEF_TYPE_EN;
-	soc_msr_write(MTRR_DEF_TYPE_MSR, data.msr);
-}