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authorJonathan Zhang <jonzhang@meta.com>2023-01-23 10:55:09 -0800
committerFelix Held <felix-coreboot@felixheld.de>2023-02-17 12:34:27 +0000
commit43277976edaba62f91d16d48f044b443a1e5da7b (patch)
tree13423b3c9d7ae634eac21cfd332eb47a52cce6df /src/soc
parent21fbf84d219244f6806cf6ba5cef59bcba32c37d (diff)
soc/intel/xeon_sp: move PCH specific code into lbg directory
pmc_lock_smi() and pmc_lockdown_config() have PCH specific implementations. Move them from common lockdown.c and pmc.c into lbg/soc_pmutil.c. Move sata_lockdown_config() and spi_lockdown_config() to lbg/lockdown.c. While here, fix some coding style issues. Change-Id: I9b357ce877123530dd5c310a730808b6e651712e Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Reviewed-by: Jian-Ming Wang <jianmingW@supermicro.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/xeon_sp/include/soc/lockdown.h9
-rw-r--r--src/soc/intel/xeon_sp/include/soc/pm.h1
-rw-r--r--src/soc/intel/xeon_sp/lbg/Makefile.inc2
-rw-r--r--src/soc/intel/xeon_sp/lbg/lockdown.c18
-rw-r--r--src/soc/intel/xeon_sp/lbg/soc_pmutil.c27
-rw-r--r--src/soc/intel/xeon_sp/lockdown.c35
-rw-r--r--src/soc/intel/xeon_sp/pmc.c12
7 files changed, 56 insertions, 48 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/lockdown.h b/src/soc/intel/xeon_sp/include/soc/lockdown.h
new file mode 100644
index 0000000000..549a93aa28
--- /dev/null
+++ b/src/soc/intel/xeon_sp/include/soc/lockdown.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _SOC_LOCKDOWN_H_
+#define _SOC_LOCKDOWN_H_
+
+void sata_lockdown_config(int chipset_lockdown);
+
+void spi_lockdown_config(int chipset_lockdown);
+#endif
diff --git a/src/soc/intel/xeon_sp/include/soc/pm.h b/src/soc/intel/xeon_sp/include/soc/pm.h
index b4d6df987e..41160fac5b 100644
--- a/src/soc/intel/xeon_sp/include/soc/pm.h
+++ b/src/soc/intel/xeon_sp/include/soc/pm.h
@@ -121,4 +121,5 @@ uint16_t get_pmbase(void);
void pmc_lock_smi(void);
+void pmc_lockdown_config(void);
#endif
diff --git a/src/soc/intel/xeon_sp/lbg/Makefile.inc b/src/soc/intel/xeon_sp/lbg/Makefile.inc
index d3dd76009b..5dedc8368f 100644
--- a/src/soc/intel/xeon_sp/lbg/Makefile.inc
+++ b/src/soc/intel/xeon_sp/lbg/Makefile.inc
@@ -2,6 +2,6 @@
bootblock-y += soc_pch.c soc_gpio.c
romstage-y += soc_pmutil.c soc_gpio.c
-ramstage-y += soc_pmutil.c soc_pch.c soc_gpio.c
+ramstage-y += soc_pmutil.c soc_pch.c soc_gpio.c lockdown.c
CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/lbg/include
diff --git a/src/soc/intel/xeon_sp/lbg/lockdown.c b/src/soc/intel/xeon_sp/lbg/lockdown.c
new file mode 100644
index 0000000000..29b43781f9
--- /dev/null
+++ b/src/soc/intel/xeon_sp/lbg/lockdown.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/pci.h>
+#include <intelblocks/cfg.h>
+#include <soc/lockdown.h>
+#include <soc/pci_devs.h>
+
+void sata_lockdown_config(int chipset_lockdown)
+{
+ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
+ pci_or_config32(PCH_DEV_SATA, SATAGC, SATAGC_REGLOCK);
+ pci_or_config32(PCH_DEV_SSATA, SATAGC, SATAGC_REGLOCK);
+ }
+}
+
+void spi_lockdown_config(int chipset_lockdown)
+{
+}
diff --git a/src/soc/intel/xeon_sp/lbg/soc_pmutil.c b/src/soc/intel/xeon_sp/lbg/soc_pmutil.c
index 2fbb9ff012..d233b7cdd7 100644
--- a/src/soc/intel/xeon_sp/lbg/soc_pmutil.c
+++ b/src/soc/intel/xeon_sp/lbg/soc_pmutil.c
@@ -17,12 +17,12 @@
uint8_t *pmc_mmio_regs(void)
{
- return (void *)(uintptr_t) pci_read_config32(PCH_DEV_PMC, PWRMBASE);
+ return (void *)(uintptr_t)pci_read_config32(PCH_DEV_PMC, PWRMBASE);
}
uintptr_t soc_read_pmc_base(void)
{
- return (uintptr_t) (pmc_mmio_regs());
+ return (uintptr_t)(pmc_mmio_regs());
}
uint32_t *soc_pmc_etr_addr(void)
@@ -57,11 +57,10 @@ void soc_fill_power_state(struct chipset_power_state *ps)
ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
- printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
- ps->gen_pmcon_a, ps->gen_pmcon_b);
+ printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", ps->gen_pmcon_a, ps->gen_pmcon_b);
printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
- ps->gblrst_cause[0], ps->gblrst_cause[1]);
+ ps->gblrst_cause[0], ps->gblrst_cause[1]);
}
/*
@@ -79,3 +78,21 @@ void pmc_soc_set_afterg3_en(const bool on)
reg8 |= SLEEP_AFTER_POWER_FAIL;
pci_write_config8(PCH_DEV_PMC, GEN_PMCON_B, reg8);
}
+
+void pmc_lock_smi(void)
+{
+ printk(BIOS_DEBUG, "Locking SMM enable.\n");
+ pci_or_config32(PCH_DEV_PMC, GEN_PMCON_A, SMI_LOCK);
+}
+
+void pmc_lockdown_config(void)
+{
+ /* PMSYNC */
+ pmc_or_mmio32(PMSYNC_TPR_CFG, PMSYNC_LOCK);
+
+ /* Make sure payload/OS can't trigger global reset */
+ pmc_global_reset_disable_and_lock();
+
+ /* Lock PMC stretch policy */
+ pci_or_config32(PCH_DEV_PMC, GEN_PMCON_B, SLP_STR_POL_LOCK);
+}
diff --git a/src/soc/intel/xeon_sp/lockdown.c b/src/soc/intel/xeon_sp/lockdown.c
index 7dc1f9834f..9e25920011 100644
--- a/src/soc/intel/xeon_sp/lockdown.c
+++ b/src/soc/intel/xeon_sp/lockdown.c
@@ -1,12 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <device/mmio.h>
-#include <device/pci.h>
-#include <intelblocks/cfg.h>
#include <intelblocks/lpc_lib.h>
-#include <intelblocks/pmclib.h>
#include <intelpch/lockdown.h>
-#include <soc/pci_devs.h>
+#include <soc/lockdown.h>
#include <soc/pm.h>
static void lpc_lockdown_config(void)
@@ -22,35 +18,10 @@ static void lpc_lockdown_config(void)
lpc_set_lock_enable();
}
-static void pmc_lockdown_config(int chipset_lockdown)
-{
- uint8_t *pmcbase;
- u32 pmsyncreg;
-
- /* PMSYNC */
- pmcbase = pmc_mmio_regs();
- pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
- pmsyncreg |= PMSYNC_LOCK;
- write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
-
- /* Make sure payload/OS can't trigger global reset */
- pmc_global_reset_disable_and_lock();
-
- /* Lock PMC stretch policy */
- pci_or_config32(PCH_DEV_PMC, GEN_PMCON_B, SLP_STR_POL_LOCK);
-}
-
-static void sata_lockdown_config(int chipset_lockdown)
-{
- if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
- pci_or_config32(PCH_DEV_SATA, SATAGC, SATAGC_REGLOCK);
- pci_or_config32(PCH_DEV_SSATA, SATAGC, SATAGC_REGLOCK);
- }
-}
-
void soc_lockdown_config(int chipset_lockdown)
{
lpc_lockdown_config();
- pmc_lockdown_config(chipset_lockdown);
+ pmc_lockdown_config();
sata_lockdown_config(chipset_lockdown);
+ spi_lockdown_config(chipset_lockdown);
}
diff --git a/src/soc/intel/xeon_sp/pmc.c b/src/soc/intel/xeon_sp/pmc.c
index b0c067bc69..4321625a16 100644
--- a/src/soc/intel/xeon_sp/pmc.c
+++ b/src/soc/intel/xeon_sp/pmc.c
@@ -28,8 +28,7 @@ int pmc_soc_get_resources(struct pmc_resource_config *cfg)
static const struct reg_script pch_pmc_misc_init_script[] = {
/* Enable SCI and clear SLP requests. */
REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN),
- REG_SCRIPT_END
-};
+ REG_SCRIPT_END};
static const struct reg_script pmc_write1_to_clear_script[] = {
REG_PCI_OR32(GEN_PMCON_A, 0),
@@ -37,8 +36,7 @@ static const struct reg_script pmc_write1_to_clear_script[] = {
REG_PCI_OR32(GEN_PMCON_B, 0),
REG_RES_OR32(PWRMBASE, GBLRST_CAUSE0, 0),
REG_RES_OR32(PWRMBASE, GBLRST_CAUSE1, 0),
- REG_SCRIPT_END
-};
+ REG_SCRIPT_END};
void pmc_soc_init(struct device *dev)
{
@@ -53,9 +51,3 @@ void pmc_soc_init(struct device *dev)
/* Clear registers that contain write-1-to-clear bits. */
reg_script_run_on_dev(dev, pmc_write1_to_clear_script);
}
-
-void pmc_lock_smi(void)
-{
- printk(BIOS_DEBUG, "Locking SMM enable.\n");
- pci_or_config32(PCH_DEV_PMC, GEN_PMCON_A, SMI_LOCK);
-}