diff options
| author | Aseda Aboagye <aaboagye@google.com> | 2021-06-17 12:23:40 -0700 |
|---|---|---|
| committer | Karthik Ramasubramanian <kramasub@google.com> | 2021-06-19 00:04:19 +0000 |
| commit | 4291c82ac0a27a803d3229114c56e5442bd0945c (patch) | |
| tree | 24361356bc03acf468a257b0503e6ad1dc581d25 /src/soc | |
| parent | e58e6f2adfb65fb960cdc41289a5186b4370fd1e (diff) | |
soc/intel/jasperlake: Add offsets for pad locking
This commit simply adds the offset for the PADCFGLOCK register for the
Intel Jasper Lake platform. This enables pads to be locked.
BUG=b:191189275
BRANCH=None
TEST=Enable pad locking on lalala by calling `gpio_lock_pad` and verify
that the pad configuration is locked and cannot be manipulated from the
OS.
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: Iccfe536b4a881f081f22bcc258a375caad3ffcb3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55648
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/jasperlake/gpio.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/jasperlake/include/soc/gpio_defs.h | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/gpio.c b/src/soc/intel/jasperlake/gpio.c index 18405fc01a..391eaae3b5 100644 --- a/src/soc/intel/jasperlake/gpio.c +++ b/src/soc/intel/jasperlake/gpio.c @@ -70,6 +70,7 @@ static const struct pad_community jsl_communities[TOTAL_GPIO_COMM] = { .last_pad = GPIO_COM0_END, .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, + .pad_cfg_lock_offset = PAD_CFG_LOCK, .host_own_reg_0 = HOSTSW_OWN_REG_0, .gpi_int_sts_reg_0 = GPI_INT_STS_0, .gpi_int_en_reg_0 = GPI_INT_EN_0, diff --git a/src/soc/intel/jasperlake/include/soc/gpio_defs.h b/src/soc/intel/jasperlake/include/soc/gpio_defs.h index 5b3cc9d781..77fbf2c45c 100644 --- a/src/soc/intel/jasperlake/include/soc/gpio_defs.h +++ b/src/soc/intel/jasperlake/include/soc/gpio_defs.h @@ -255,5 +255,6 @@ #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1a0 #define PAD_CFG_BASE 0x600 +#define PAD_CFG_LOCK 0x80 #endif |