diff options
| author | MAULIK V VAGHELA <maulik.v.vaghela@intel.com> | 2021-08-02 13:11:46 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-08-09 06:13:07 +0000 |
| commit | 3c0ecd57c174b7391c66d22406effe18ce570cac (patch) | |
| tree | 2f22e85a55e9f7e20d235bb96926515816bf3984 /src/soc | |
| parent | 43a3aa0cf4ef427de6b2e445598c4aa300718bb1 (diff) | |
soc/intel/common/cpu: Handle non-zero BSP APIC ID in init_cpus
coreboot always assumes that BSP APIC ID will always be 0 but as
per Intel 64 and IA-32 Architectures Software Developer’s Manual
Volume 3: 8.4.1 BSP and AP Processors, it says that BSP can
be any processor whose index/APIC ID might not be 0.
To handle this situation, init_cpu call is required to modify to
handle dynamic detection of APIC ID from BSP instead of hardcoding
always through devicetree. Function has been updated to create
a new node with actual BSP APIC ID when devicetree doesn't contain
APIC ID defined. In case APID ID is defined, function will use a
node with the APIC ID defined in devicetree.
Changes also requires to remove "lapic 0" hardcoding from devicetree
to allow code to fill BSP APIC ID dynamically. Otherwise coreboot
will create an extra node for CPU with APIC ID 0 and it'll show as a
extra node in kernel. This will cause kernel to report wrong (extra)
core count information then actually present.
BUG=None
BRANCH=None
TEST=Boot the JSL system and observe there is no functional impacts.
Without this CL kernel core count in `lscpu` = 3
With this CL, kernel core count is corrected to 2.
Change-Id: Ib14a5c31b3afb0d773284c684bd1994a78b94445
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/common/block/cpu/mp_init.c | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index c31a6f70b7..bf47b2e0b2 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -115,14 +115,25 @@ void get_microcode_info(const void **microcode, int *parallel) * this call if user has selected USE_INTEL_FSP_MP_INIT). * 2. coreboot would like to take APs control back after FSP-S has done with MP * initialization based on user select USE_INTEL_FSP_MP_INIT. + * + * This function would use cpu_cluster as a device and APIC device as a linked list to + * the cpu cluster. This function adds a node in case the mainboard doesn't have a lapic id + * hardcoded in devicetree, and then fills with the actual BSP APIC ID. + * This allows coreboot to dynamically detect the LAPIC ID of BSP. + * In case the mainboard has an APIC ID defined in devicetree, a link will be present and + * creation of the new node will be skipped. This node will have the APIC ID defined + * in devicetree. */ void init_cpus(void) { struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); assert(dev != NULL); - if (dev && dev->link_list) - soc_init_cpus(dev->link_list); + /* In case link to APIC device is not found, create the one */ + if (!dev->link_list) + add_more_links(dev, 1); + + soc_init_cpus(dev->link_list); } static void coreboot_init_cpus(void *unused) |