diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-11-08 11:48:40 -0700 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2021-11-12 14:55:45 +0000 |
| commit | 36c5daad33fd6f69b5d3c2fd91a6fa6acd24f658 (patch) | |
| tree | 43e8d693ee21462627c28ad83f70457876fc5c48 /src/soc | |
| parent | c0025c25f3dd4d72f04fa7f5b4c5fbb8459d3be7 (diff) | |
soc/amd/cezanne: Preload FSP-S
FSP-S is normally memmapped and then decompressed. There are about 7 ms
between starting ramstage, and loading FSP-S. By preloading we can
ensure the fsps.bin is already in RAM by the time we need it. This
reduces boot time by about 7 ms.
BUG=b:
TEST=Boot nipperkin and see ~7ms reduction in boot time
| 10 - start of ramstage | 0.044 | 0.044 Δ( 0.00, 0.00%) |
| 30 - device enumeration | 1.899 | 2.073 Δ( 0.17, 0.01%) |
| 971 - loading FSP-S | 6.645 | 6.628 Δ( -0.02, -0.00%) |
| 15 - starting LZMA decompress (ignore for x86) | 0.016 | 0.01 Δ( -0.01, -0.00%) |
| 16 - finished LZMA decompress (ignore for x86) | 15.266 | 8.316 Δ( -6.95, -0.47%) |
| 954 - calling FspSiliconInit | 0.08 | 0.09 Δ( 0.01, 0.00%) |
CBFS DEBUG: _cbfs_alloc(name='fsps.bin', alloc=0xc9761e5c(0xc97a3f0c), force_ro=false, type=-1)
CBFS: Found 'fsps.bin' @0x1a1fc0 size 0x102cd in mcache @0xc97dd208
waiting for thread
took 1 us <-- fsps.bin was preloaded
CBFS DEBUG: get_preload_rdev(name='fsps.bin') preload successful
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5a728047b8ad92d70bba8485017579aa3df48d95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/preload.c | 11 |
2 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 8db0f6cd8d..58df7406ed 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -39,6 +39,7 @@ ramstage-y += gpio.c ramstage-y += graphics.c ramstage-y += i2c.c ramstage-y += mca.c +ramstage-y += preload.c ramstage-y += reset.c ramstage-y += root_complex.c ramstage-y += uart.c diff --git a/src/soc/amd/cezanne/preload.c b/src/soc/amd/cezanne/preload.c new file mode 100644 index 0000000000..d8b08912ad --- /dev/null +++ b/src/soc/amd/cezanne/preload.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootstate.h> +#include <fsp/api.h> + +static void start_fsps_preload(void *unused) +{ + preload_fsps(); +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, start_fsps_preload, NULL); |