soc/amd: rework DRAM and fixed resource reporting

Introduce read_soc_memmap_resources which gets called by
amd_pci_domain_read_resources for the first domain of the SoC to report
the DRAM and PCI config space access resources to the allocator. For
Genoa this allows to use amd_pci_domain_read_resources as read_resources
in the genoa_pci_domain_ops instead of needing to wrap that call to be
able to call add_opensil_memmap for the first domain. For the other
family 17h+ SoCs the moves the reporting of the DRAM resources and the
PCI config space access resources from the northbridge device to the
domain device.

TEST=Resources still get reported on Mandolin, but now under the domain
instead of the northbridge PCI device

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib19fd94e06fa3a1d95ade7fafe22db013045a942
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80268
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

8 files changed, 80 insertions, 90 deletions

diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c
index 20cea054ba..25867408bc 100644
--- a/src/soc/amd/cezanne/root_complex.c
+++ b/src/soc/amd/cezanne/root_complex.c
@@ -101,10 +101,9 @@ struct dptc_input {
  *                     |              DRAM              |
  *                     +--------------------------------+ 0x0
  */
-static void read_resources(struct device *dev)
+void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
 {
 	uint32_t mem_usable = (uintptr_t)cbmem_top();
-	unsigned long idx = 0;
 
 	uintptr_t early_reserved_dram_start, early_reserved_dram_end;
 	const struct memmap_early_dram *e = memmap_get_early_dram_usage();
@@ -112,38 +111,35 @@ static void read_resources(struct device *dev)
 	early_reserved_dram_start = e->base;
 	early_reserved_dram_end = e->base + e->size;
 
-	/* The root complex has no PCI BARs implemented, so there's no need to call
-	   pci_dev_read_resources for it */
-
-	fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT);
+	fixed_io_range_reserved(dev, (*idx)++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT);
 
 	/* 0x0 - 0x9ffff */
-	ram_range(dev, idx++, 0, 0xa0000);
+	ram_range(dev, (*idx)++, 0, 0xa0000);
 
 	/* 0xa0000 - 0xbffff: legacy VGA */
-	mmio_range(dev, idx++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
+	mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
 
 	/* 0xc0000 - 0xfffff: Option ROM */
-	reserved_ram_from_to(dev, idx++, 0xc0000, 1 * MiB);
+	reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB);
 
 	/* 1MiB - bottom of DRAM reserved for early coreboot usage */
-	ram_from_to(dev, idx++, 1 * MiB, early_reserved_dram_start);
+	ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start);
 
 	/* DRAM reserved for early coreboot usage */
-	reserved_ram_from_to(dev, idx++, early_reserved_dram_start, early_reserved_dram_end);
+	reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end);
 
 	/*
 	 * top of DRAM consumed early - low top usable RAM
 	 * cbmem_top() accounts for low UMA and TSEG if they are used.
 	 */
-	ram_from_to(dev, idx++, early_reserved_dram_end, mem_usable);
+	ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable);
 
-	mmconf_resource(dev, idx++);
+	mmconf_resource(dev, (*idx)++);
 
 	/* Reserve fixed IOMMU MMIO region */
-	mmio_range(dev, idx++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
+	mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
 
-	read_fsp_resources(dev, &idx);
+	read_fsp_resources(dev, idx);
 }
 
 static void root_complex_init(struct device *dev)
@@ -175,7 +171,9 @@ static const char *gnb_acpi_name(const struct device *dev)
 }
 
 struct device_operations cezanne_root_complex_operations = {
-	.read_resources		= read_resources,
+	/* The root complex has no PCI BARs implemented, so there's no need to call
+	   pci_dev_read_resources for it */
+	.read_resources		= noop_read_resources,
 	.set_resources		= noop_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= root_complex_init,
diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c
index 8533dffcc4..65735574d1 100644
--- a/src/soc/amd/common/block/data_fabric/domain.c
+++ b/src/soc/amd/common/block/data_fabric/domain.c
@@ -200,6 +200,11 @@ void amd_pci_domain_read_resources(struct device *domain)
 	add_data_fabric_mmio_regions(domain, &idx);
 
 	read_non_pci_resources(domain, &idx);
+
+	/* Only add the SoC's DRAM memory map and fixed resources once */
+	if (domain->path.domain.domain == 0) {
+		read_soc_memmap_resources(domain, &idx);
+	}
 }
 
 static void write_ssdt_domain_io_producer_range_helper(const char *domain_name,
diff --git a/src/soc/amd/common/block/include/amdblocks/root_complex.h b/src/soc/amd/common/block/include/amdblocks/root_complex.h
index 0eef5e8ae5..cac659e756 100644
--- a/src/soc/amd/common/block/include/amdblocks/root_complex.h
+++ b/src/soc/amd/common/block/include/amdblocks/root_complex.h
@@ -22,6 +22,8 @@ struct non_pci_mmio_reg {
 
 void read_non_pci_resources(struct device *domain, unsigned long *idx);
 
+void read_soc_memmap_resources(struct device *domain, unsigned long *idx);
+
 uint32_t get_iohc_misc_smn_base(struct device *domain);
 const struct non_pci_mmio_reg *get_iohc_non_pci_mmio_regs(size_t *count);
 
diff --git a/src/soc/amd/genoa_poc/domain.c b/src/soc/amd/genoa_poc/domain.c
index 653e2d2a8c..b34d2e36bb 100644
--- a/src/soc/amd/genoa_poc/domain.c
+++ b/src/soc/amd/genoa_poc/domain.c
@@ -13,16 +13,9 @@
 
 #define IOHC_IOAPIC_BASE_ADDR_LO 0x2f0
 
-static void genoa_domain_read_resources(struct device *domain)
+void read_soc_memmap_resources(struct device *domain, unsigned long *idx)
 {
-	amd_pci_domain_read_resources(domain);
-
-	// We only want to add the DRAM memory map once
-	if (domain->path.domain.domain == 0) {
-		/* 0x1000 is a large enough first index to be sure to not overlap with the
-		   resources added by amd_pci_domain_read_resources */
-		add_opensil_memmap(domain, 0x1000);
-	}
+	*idx = add_opensil_memmap(domain, *idx);
 }
 
 static void genoa_domain_set_resources(struct device *domain)
@@ -74,7 +67,7 @@ static const char *genoa_domain_acpi_name(const struct device *domain)
 }
 
 struct device_operations genoa_pci_domain_ops = {
-	.read_resources	= genoa_domain_read_resources,
+	.read_resources	= amd_pci_domain_read_resources,
 	.set_resources	= genoa_domain_set_resources,
 	.scan_bus	= amd_pci_domain_scan_bus,
 	.init		= genoa_domain_init,
diff --git a/src/soc/amd/glinda/root_complex.c b/src/soc/amd/glinda/root_complex.c
index 9b53a564c1..37d189e64e 100644
--- a/src/soc/amd/glinda/root_complex.c
+++ b/src/soc/amd/glinda/root_complex.c
@@ -116,10 +116,9 @@ struct dptc_input {
  *                     |              DRAM              |
  *                     +--------------------------------+ 0x0
  */
-static void read_resources(struct device *dev)
+void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
 {
 	uint32_t mem_usable = (uintptr_t)cbmem_top();
-	unsigned long idx = 0;
 
 	uintptr_t early_reserved_dram_start, early_reserved_dram_end;
 	const struct memmap_early_dram *e = memmap_get_early_dram_usage();
@@ -127,38 +126,35 @@ static void read_resources(struct device *dev)
 	early_reserved_dram_start = e->base;
 	early_reserved_dram_end = e->base + e->size;
 
-	/* The root complex has no PCI BARs implemented, so there's no need to call
-	   pci_dev_read_resources for it */
-
-	fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT);
+	fixed_io_range_reserved(dev, (*idx)++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT);
 
 	/* 0x0 - 0x9ffff */
-	ram_range(dev, idx++, 0, 0xa0000);
+	ram_range(dev, (*idx)++, 0, 0xa0000);
 
 	/* 0xa0000 - 0xbffff: legacy VGA */
-	mmio_range(dev, idx++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
+	mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
 
 	/* 0xc0000 - 0xfffff: Option ROM */
-	reserved_ram_from_to(dev, idx++, 0xc0000, 1 * MiB);
+	reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB);
 
 	/* 1MiB - bottom of DRAM reserved for early coreboot usage */
-	ram_from_to(dev, idx++, 1 * MiB, early_reserved_dram_start);
+	ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start);
 
 	/* DRAM reserved for early coreboot usage */
-	reserved_ram_from_to(dev, idx++, early_reserved_dram_start, early_reserved_dram_end);
+	reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end);
 
 	/*
 	 * top of DRAM consumed early - low top usable RAM
 	 * cbmem_top() accounts for low UMA and TSEG if they are used.
 	 */
-	ram_from_to(dev, idx++, early_reserved_dram_end, mem_usable);
+	ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable);
 
-	mmconf_resource(dev, idx++);
+	mmconf_resource(dev, (*idx)++);
 
 	/* Reserve fixed IOMMU MMIO region */
-	mmio_range(dev, idx++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
+	mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
 
-	read_fsp_resources(dev, &idx);
+	read_fsp_resources(dev, idx);
 }
 
 static void root_complex_init(struct device *dev)
@@ -205,7 +201,9 @@ static const char *gnb_acpi_name(const struct device *dev)
 }
 
 struct device_operations glinda_root_complex_operations = {
-	.read_resources		= read_resources,
+	/* The root complex has no PCI BARs implemented, so there's no need to call
+	   pci_dev_read_resources for it */
+	.read_resources		= noop_read_resources,
 	.set_resources		= noop_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= root_complex_init,
diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c
index 886b54e395..7291058e3f 100644
--- a/src/soc/amd/mendocino/root_complex.c
+++ b/src/soc/amd/mendocino/root_complex.c
@@ -144,10 +144,9 @@ struct dptc_input {
  *                     |              DRAM              |
  *                     +--------------------------------+ 0x0
  */
-static void read_resources(struct device *dev)
+void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
 {
 	uint32_t mem_usable = (uintptr_t)cbmem_top();
-	unsigned long idx = 0;
 
 	uintptr_t early_reserved_dram_start, early_reserved_dram_end;
 	const struct memmap_early_dram *e = memmap_get_early_dram_usage();
@@ -155,38 +154,35 @@ static void read_resources(struct device *dev)
 	early_reserved_dram_start = e->base;
 	early_reserved_dram_end = e->base + e->size;
 
-	/* The root complex has no PCI BARs implemented, so there's no need to call
-	   pci_dev_read_resources for it */
-
-	fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT);
+	fixed_io_range_reserved(dev, (*idx)++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT);
 
 	/* 0x0 - 0x9ffff */
-	ram_range(dev, idx++, 0, 0xa0000);
+	ram_range(dev, (*idx)++, 0, 0xa0000);
 
 	/* 0xa0000 - 0xbffff: legacy VGA */
-	mmio_range(dev, idx++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
+	mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
 
 	/* 0xc0000 - 0xfffff: Option ROM */
-	reserved_ram_from_to(dev, idx++, 0xc0000, 1 * MiB);
+	reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB);
 
 	/* 1MiB - bottom of DRAM reserved for early coreboot usage */
-	ram_from_to(dev, idx++, 1 * MiB, early_reserved_dram_start);
+	ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start);
 
 	/* DRAM reserved for early coreboot usage */
-	reserved_ram_from_to(dev, idx++, early_reserved_dram_start, early_reserved_dram_end);
+	reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end);
 
 	/*
 	 * top of DRAM consumed early - low top usable RAM
 	 * cbmem_top() accounts for low UMA and TSEG if they are used.
 	 */
-	ram_from_to(dev, idx++, early_reserved_dram_end, mem_usable);
+	ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable);
 
-	mmconf_resource(dev, idx++);
+	mmconf_resource(dev, (*idx)++);
 
 	/* Reserve fixed IOMMU MMIO region */
-	mmio_range(dev, idx++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
+	mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
 
-	read_fsp_resources(dev, &idx);
+	read_fsp_resources(dev, idx);
 }
 
 static void root_complex_init(struct device *dev)
@@ -366,7 +362,9 @@ static const char *gnb_acpi_name(const struct device *dev)
 }
 
 struct device_operations mendocino_root_complex_operations = {
-	.read_resources		= read_resources,
+	/* The root complex has no PCI BARs implemented, so there's no need to call
+	   pci_dev_read_resources for it */
+	.read_resources		= noop_read_resources,
 	.set_resources		= noop_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= root_complex_init,
diff --git a/src/soc/amd/phoenix/root_complex.c b/src/soc/amd/phoenix/root_complex.c
index 82216aec7e..3e61df1a01 100644
--- a/src/soc/amd/phoenix/root_complex.c
+++ b/src/soc/amd/phoenix/root_complex.c
@@ -116,10 +116,9 @@ struct dptc_input {
  *                     |              DRAM              |
  *                     +--------------------------------+ 0x0
  */
-static void read_resources(struct device *dev)
+void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
 {
 	uint32_t mem_usable = (uintptr_t)cbmem_top();
-	unsigned long idx = 0;
 
 	uintptr_t early_reserved_dram_start, early_reserved_dram_end;
 	const struct memmap_early_dram *e = memmap_get_early_dram_usage();
@@ -127,38 +126,35 @@ static void read_resources(struct device *dev)
 	early_reserved_dram_start = e->base;
 	early_reserved_dram_end = e->base + e->size;
 
-	/* The root complex has no PCI BARs implemented, so there's no need to call
-	   pci_dev_read_resources for it */
-
-	fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT);
+	fixed_io_range_reserved(dev, (*idx)++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT);
 
 	/* 0x0 - 0x9ffff */
-	ram_range(dev, idx++, 0, 0xa0000);
+	ram_range(dev, (*idx)++, 0, 0xa0000);
 
 	/* 0xa0000 - 0xbffff: legacy VGA */
-	mmio_range(dev, idx++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
+	mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
 
 	/* 0xc0000 - 0xfffff: Option ROM */
-	reserved_ram_from_to(dev, idx++, 0xc0000, 1 * MiB);
+	reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB);
 
 	/* 1MiB - bottom of DRAM reserved for early coreboot usage */
-	ram_from_to(dev, idx++, 1 * MiB, early_reserved_dram_start);
+	ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start);
 
 	/* DRAM reserved for early coreboot usage */
-	reserved_ram_from_to(dev, idx++, early_reserved_dram_start, early_reserved_dram_end);
+	reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end);
 
 	/*
 	 * top of DRAM consumed early - low top usable RAM
 	 * cbmem_top() accounts for low UMA and TSEG if they are used.
 	 */
-	ram_from_to(dev, idx++, early_reserved_dram_end, mem_usable);
+	ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable);
 
-	mmconf_resource(dev, idx++);
+	mmconf_resource(dev, (*idx)++);
 
 	/* Reserve fixed IOMMU MMIO region */
-	mmio_range(dev, idx++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
+	mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
 
-	read_fsp_resources(dev, &idx);
+	read_fsp_resources(dev, idx);
 }
 
 static void root_complex_init(struct device *dev)
@@ -205,7 +201,9 @@ static const char *gnb_acpi_name(const struct device *dev)
 }
 
 struct device_operations phoenix_root_complex_operations = {
-	.read_resources		= read_resources,
+	/* The root complex has no PCI BARs implemented, so there's no need to call
+	   pci_dev_read_resources for it */
+	.read_resources		= noop_read_resources,
 	.set_resources		= noop_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= root_complex_init,
diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c
index 0edd245314..ffe4f66f5b 100644
--- a/src/soc/amd/picasso/root_complex.c
+++ b/src/soc/amd/picasso/root_complex.c
@@ -101,10 +101,9 @@ struct dptc_input {
  *                     |              DRAM              |
  *                     +--------------------------------+ 0x0
  */
-static void read_resources(struct device *dev)
+void read_soc_memmap_resources(struct device *dev, unsigned long *idx)
 {
 	uint32_t mem_usable = (uintptr_t)cbmem_top();
-	unsigned long idx = 0;
 
 	uintptr_t early_reserved_dram_start, early_reserved_dram_end;
 	const struct memmap_early_dram *e = memmap_get_early_dram_usage();
@@ -112,36 +111,33 @@ static void read_resources(struct device *dev)
 	early_reserved_dram_start = e->base;
 	early_reserved_dram_end = e->base + e->size;
 
-	/* The root complex has no PCI BARs implemented, so there's no need to call
-	   pci_dev_read_resources for it */
-
-	fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT);
+	fixed_io_range_reserved(dev, (*idx)++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT);
 
 	/* 0x0 - 0x9ffff */
-	ram_range(dev, idx++, 0, 0xa0000);
+	ram_range(dev, (*idx)++, 0, 0xa0000);
 
 	/* 0xa0000 - 0xbffff: legacy VGA */
-	mmio_range(dev, idx++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
+	mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
 
 	/* 0xc0000 - 0xfffff: Option ROM */
-	reserved_ram_from_to(dev, idx++, 0xc0000, 1 * MiB);
+	reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB);
 
 	/* 1MB - bottom of DRAM reserved for early coreboot usage */
-	ram_from_to(dev, idx++, 1 * MiB, early_reserved_dram_start);
+	ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start);
 
 	/* DRAM reserved for early coreboot usage */
-	reserved_ram_from_to(dev, idx++, early_reserved_dram_start, early_reserved_dram_end);
+	reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end);
 
 	/* top of DRAM consumed early - low top usable RAM
 	 * cbmem_top() accounts for low UMA and TSEG if they are used. */
-	ram_from_to(dev, idx++, early_reserved_dram_end, mem_usable);
+	ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable);
 
-	mmconf_resource(dev, idx++);
+	mmconf_resource(dev, (*idx)++);
 
 	/* Reserve fixed IOMMU MMIO region */
-	mmio_range(dev, idx++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
+	mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
 
-	read_fsp_resources(dev, &idx);
+	read_fsp_resources(dev, idx);
 }
 
 static void root_complex_init(struct device *dev)
@@ -182,7 +178,9 @@ static const char *gnb_acpi_name(const struct device *dev)
 }
 
 struct device_operations picasso_root_complex_operations = {
-	.read_resources		= read_resources,
+	/* The root complex has no PCI BARs implemented, so there's no need to call
+	   pci_dev_read_resources for it */
+	.read_resources		= noop_read_resources,
 	.set_resources		= noop_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= root_complex_init,