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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2023-02-12 23:01:20 +0100 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-06-14 21:16:15 +0000 |
| commit | 2fffb5df88faf6da061bd84606db8fad6453ee40 (patch) | |
| tree | 9a43a1d4e13b6f3a6b1a9094ceae3b982c6b8d29 /src/soc | |
| parent | f9ee87ffbf6e7e5d7870bd3617c5a3368ac41c54 (diff) | |
soc/intel/alderlake/vr_config.c: Fix GT domain TDC current
Alder Lake-S 2+0 SKUs and 35W SKUs have 20A GT TDC, all other Alder
Lake-S SKUs have GT TDC of 22A.
Based on the default settings of ADL-S FSP.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie6851d322fc9354d019a76503c3d35b5e6eca48b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/alderlake/vr_config.c | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index 597f8c5d5b..e24d0953ba 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -249,21 +249,21 @@ static const struct vr_lookup vr_config_tdc_currentlimit[] = { { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, - { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) }, - { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) }, - { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 89) }, - { PCI_DID_INTEL_ADL_S_ID_1, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(56, 56) }, - { PCI_DID_INTEL_ADL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(109, 109) }, - { PCI_DID_INTEL_ADL_S_ID_3, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(77, 77) }, - { PCI_DID_INTEL_ADL_S_ID_3, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(49, 49) }, - { PCI_DID_INTEL_ADL_S_ID_8, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(96, 96) }, - { PCI_DID_INTEL_ADL_S_ID_10, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(66, 66) }, - { PCI_DID_INTEL_ADL_S_ID_10, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(44, 44) }, - { PCI_DID_INTEL_ADL_S_ID_11, 60, VR_CFG_ALL_DOMAINS_TDC_CURRENT(56, 56) }, - { PCI_DID_INTEL_ADL_S_ID_11, 58, VR_CFG_ALL_DOMAINS_TDC_CURRENT(59, 59) }, - { PCI_DID_INTEL_ADL_S_ID_11, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) }, - { PCI_DID_INTEL_ADL_S_ID_12, 46, VR_CFG_ALL_DOMAINS_TDC_CURRENT(39, 39) }, - { PCI_DID_INTEL_ADL_S_ID_12, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(30, 30) }, + { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 22) }, + { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 22) }, + { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, + { PCI_DID_INTEL_ADL_S_ID_1, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(56, 20) }, + { PCI_DID_INTEL_ADL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(109, 22) }, + { PCI_DID_INTEL_ADL_S_ID_3, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(77, 22) }, + { PCI_DID_INTEL_ADL_S_ID_3, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(49, 20) }, + { PCI_DID_INTEL_ADL_S_ID_8, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(96, 22) }, + { PCI_DID_INTEL_ADL_S_ID_10, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(66, 22) }, + { PCI_DID_INTEL_ADL_S_ID_10, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(44, 20) }, + { PCI_DID_INTEL_ADL_S_ID_11, 60, VR_CFG_ALL_DOMAINS_TDC_CURRENT(56, 22) }, + { PCI_DID_INTEL_ADL_S_ID_11, 58, VR_CFG_ALL_DOMAINS_TDC_CURRENT(59, 22) }, + { PCI_DID_INTEL_ADL_S_ID_11, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 20) }, + { PCI_DID_INTEL_ADL_S_ID_12, 46, VR_CFG_ALL_DOMAINS_TDC_CURRENT(39, 20) }, + { PCI_DID_INTEL_ADL_S_ID_12, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(30, 20) }, }; static void fill_vr_fast_vmode(FSP_S_CONFIG *s_cfg, |