diff options
| author | Jan Dabros <jsd@semihalf.com> | 2022-09-15 07:36:43 +0000 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-09-19 09:52:25 +0000 |
| commit | 2d9e96a5ab175e126929e8d2314227cdd441857f (patch) | |
| tree | 6451f40a77ce036e88061f35996b59805d7808ef /src/soc | |
| parent | e8097f7a283228e3bbb8ddc525e4f8c861a5bcb8 (diff) | |
soc/amd/mendocino/acpi: Add support for shared TPM_I2C controller
There are platforms equipped with AMD SoC where I2C3 controller
connected to TPM device is shared between X86 and PSP. In order to
handle this, PSP acts as an I2C-arbitrator, where x86 (kernel) sends
acquire and release requests to be accepted by PSP.
Introduce new CONFIG for Mendocino SoCs similar to what we have for
Cezanne.
BUG=b:241878652
BRANCH=none
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I015a24715271d2b26c0bd3c9425e20fb2987a954
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/mendocino/acpi/mmio.asl | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/amd/mendocino/acpi/mmio.asl b/src/soc/amd/mendocino/acpi/mmio.asl index 48ae1d2773..5544016666 100644 --- a/src/soc/amd/mendocino/acpi/mmio.asl +++ b/src/soc/amd/mendocino/acpi/mmio.asl @@ -327,7 +327,11 @@ Device (I2C2) { Device (I2C3) { +#if CONFIG(SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP) + Name (_HID, "AMDI0019") +#else Name (_HID, "AMDI0010") +#endif Name (_UID, 0x3) Method (_CRS, 0) { Local0 = ResourceTemplate() { @@ -358,7 +362,10 @@ Device (I2C3) Return (0x0F) } +/* If this device is shared with PSP, then PSP takes care of power management */ +#if !CONFIG(SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP) AOAC_DEVICE(FCH_AOAC_DEV_I2C3, 0) +#endif } Device (MISC) |