diff options
| author | Chris Wang <chris.wang@amd.corp-partner.google.com> | 2021-03-02 22:33:00 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-03-10 23:03:59 +0000 |
| commit | 216d69d459ba685c2aeb42b00c1cef7be2482864 (patch) | |
| tree | 79ed3d1552be87429cf42af59043abf430cd9124 /src/soc | |
| parent | 9a6bc07cc26a93c434bc8dac86cf13c0edef09a8 (diff) | |
mb/google/zork: add UPDM updating function before runing FSP-M
Add the UPD updating hook in early stage for customization.
BUG=b:117719313
BRANCH=zork
TEST=build,check the hook function been executed.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I4954a438a51b29b086015624127e651fd06f971b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51181
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/romstage.h | 10 | ||||
| -rw-r--r-- | src/soc/amd/picasso/romstage.c | 4 |
2 files changed, 14 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/include/soc/romstage.h b/src/soc/amd/picasso/include/soc/romstage.h new file mode 100644 index 0000000000..0af374f437 --- /dev/null +++ b/src/soc/amd/picasso/include/soc/romstage.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ROMSTAGE_H_ +#define _SOC_ROMSTAGE_H_ + +#include <fsp/api.h> + +void mainboard_updm_update(FSP_M_CONFIG *mcfg); + +#endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index ecee4d3fe9..daf2280346 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -16,10 +16,12 @@ #include <elog.h> #include <soc/acpi.h> #include <soc/pci_devs.h> +#include <soc/romstage.h> #include <types.h> #include "chip.h" #include <fsp/api.h> +void __weak mainboard_updm_update(FSP_M_CONFIG *mupd) {} static struct chipset_power_state chipset_state; static void fill_chipset_state(void) @@ -139,6 +141,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mcfg->telemetry_vddcr_soc_offset = config->telemetry_vddcr_soc_offset; mcfg->hd_audio_enable = devtree_hda_dev_enabled(); mcfg->sata_enable = devtree_sata_dev_enabled(); + + mainboard_updm_update(mcfg); } asmlinkage void car_stage_entry(void) |