diff options
author | Wenbin Mei <wenbin.mei@mediatek.com> | 2021-11-05 10:05:11 +0800 |
---|---|---|
committer | Hung-Te Lin <hungte@chromium.org> | 2021-11-16 08:01:27 +0000 |
commit | 1cbcfc13eb95dbd39c85f4c7b366b1369d1f73e8 (patch) | |
tree | 0cab28e12bb992e8dd4399717dba2f2656fa19c6 /src/soc | |
parent | f3b2c157f561d8311f47474444166859df08d282 (diff) |
soc/mediatek/mt8186: Configure eMMC and SD Card
The Corsola reference design has both eMMC and SD Card interfaces
so we have to configure both in RAM stage.
TEST=build pass
BUG=b:202871018
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Change-Id: I2f26a8a11edd29a80a7195e3a324151d66ecb293
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r-- | src/soc/mediatek/common/include/soc/msdc.h | 8 | ||||
-rw-r--r-- | src/soc/mediatek/mt8186/Makefile.inc | 1 | ||||
-rw-r--r-- | src/soc/mediatek/mt8186/msdc.c | 104 |
3 files changed, 110 insertions, 3 deletions
diff --git a/src/soc/mediatek/common/include/soc/msdc.h b/src/soc/mediatek/common/include/soc/msdc.h index 6208b72f6e..f25c3d0276 100644 --- a/src/soc/mediatek/common/include/soc/msdc.h +++ b/src/soc/mediatek/common/include/soc/msdc.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __MSDC_H_ -#define __MSDC_H_ +#ifndef SOC_MEDIATEK_COMMON_MSDC_H +#define SOC_MEDIATEK_COMMON_MSDC_H #include <commonlib/sd_mmc_ctrlr.h> @@ -165,5 +165,7 @@ struct msdc_ctrlr { #define msdc_error(format...) printk(BIOS_ERR, "ERROR: " format) int mtk_emmc_early_init(void *base, void *top_base); +void mtk_msdc_configure_emmc(void); +void mtk_msdc_configure_sdcard(void); -#endif // MTK_MMC_H_ +#endif /* SOC_MEDIATEK_COMMON_MSDC_H */ diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index 7d6d2ffd69..cb472cee2f 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -38,6 +38,7 @@ ramstage-y += emi.c ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += soc.c ramstage-y += ../common/timer.c timer.c diff --git a/src/soc/mediatek/mt8186/msdc.c b/src/soc/mediatek/mt8186/msdc.c new file mode 100644 index 0000000000..f1c2004d09 --- /dev/null +++ b/src/soc/mediatek/mt8186/msdc.c @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.7 + */ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/gpio.h> +#include <soc/regulator.h> +#include <soc/msdc.h> + +DEFINE_BITFIELD(MSDC0_DRV, 29, 0) +DEFINE_BITFIELD(MSDC1_DRV, 23, 6) +DEFINE_BITFIELD(MSDC1_GPIO_MODE0_0, 18, 16) +DEFINE_BITFIELD(MSDC1_GPIO_MODE0_1, 22, 20) +DEFINE_BITFIELD(MSDC1_GPIO_MODE0_2, 26, 24) +DEFINE_BITFIELD(MSDC1_GPIO_MODE0_3, 30, 28) +DEFINE_BITFIELD(MSDC1_GPIO_MODE1_0, 2, 0) +DEFINE_BITFIELD(MSDC1_GPIO_MODE1_1, 6, 4) + +#define MSDC0_BASE 0x11230000 +#define MSDC0_TOP_BASE 0x11cd0000 + +#define MSDC0_DRV_VALUE 0x1b6db6db +#define MSDC1_DRV_VALUE 0x1b6db +#define MSDC1_GPIO_MODE0_VALUE 0x1 +#define MSDC1_GPIO_MODE1_VALUE 0x1 + +enum { + MSDC1_GPIO_MODE0_BASE = 0x100053a0, + MSDC1_GPIO_MODE1_BASE = 0x100053b0, +}; + +void mtk_msdc_configure_emmc(void) +{ + void *gpio_base = (void *)IOCFG_LT_BASE; + int i; + + const gpio_t emmc_pu_pin[] = { + GPIO(MSDC0_DAT0), GPIO(MSDC0_DAT1), + GPIO(MSDC0_DAT2), GPIO(MSDC0_DAT3), + GPIO(MSDC0_DAT4), GPIO(MSDC0_DAT5), + GPIO(MSDC0_DAT6), GPIO(MSDC0_DAT7), + GPIO(MSDC0_CMD), GPIO(MSDC0_RSTB), + }; + + const gpio_t emmc_pd_pin[] = { + GPIO(MSDC0_DSL), GPIO(MSDC0_CLK), + }; + + for (i = 0; i < ARRAY_SIZE(emmc_pu_pin); i++) + gpio_set_pull(emmc_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); + + for (i = 0; i < ARRAY_SIZE(emmc_pd_pin); i++) + gpio_set_pull(emmc_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + + /* set eMMC cmd/dat/clk pins driving to 8mA */ + SET32_BITFIELDS(gpio_base, MSDC0_DRV, MSDC0_DRV_VALUE); +} + +void mtk_msdc_configure_sdcard(void) +{ + void *gpio_base = (void *)IOCFG_LB_BASE; + void *gpio_mode0_base = (void *)MSDC1_GPIO_MODE0_BASE; + void *gpio_mode1_base = (void *)MSDC1_GPIO_MODE1_BASE; + int i; + + const gpio_t sdcard_pu_pin[] = { + GPIO(MSDC1_DAT0), GPIO(MSDC1_DAT1), + GPIO(MSDC1_DAT2), GPIO(MSDC1_DAT3), + GPIO(MSDC1_CMD), + }; + + const gpio_t sdcard_pd_pin[] = { + GPIO(MSDC1_CLK), + }; + + for (i = 0; i < ARRAY_SIZE(sdcard_pu_pin); i++) + gpio_set_pull(sdcard_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); + + for (i = 0; i < ARRAY_SIZE(sdcard_pd_pin); i++) + gpio_set_pull(sdcard_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + + /* set sdcard cmd/dat/clk pins driving to 8mA */ + SET32_BITFIELDS(gpio_base, MSDC1_DRV, MSDC1_DRV_VALUE); + + /* set sdcard dat2/dat0/dat3/cmd/clk pins to msdc1 mode */ + SET32_BITFIELDS(gpio_mode0_base, + MSDC1_GPIO_MODE0_0, MSDC1_GPIO_MODE0_VALUE, + MSDC1_GPIO_MODE0_1, MSDC1_GPIO_MODE0_VALUE, + MSDC1_GPIO_MODE0_2, MSDC1_GPIO_MODE0_VALUE, + MSDC1_GPIO_MODE0_3, MSDC1_GPIO_MODE0_VALUE); + + /* set sdcard dat1 pin to msdc1 mode */ + SET32_BITFIELDS(gpio_mode1_base, + MSDC1_GPIO_MODE1_0, MSDC1_GPIO_MODE1_VALUE, + MSDC1_GPIO_MODE1_1, MSDC1_GPIO_MODE1_VALUE); + + /* enable SDCard power */ + mainboard_set_regulator_vol(MTK_REGULATOR_VMCH, 3300000); + mainboard_set_regulator_vol(MTK_REGULATOR_VMC, 3300000); +} |