diff options
| author | Jonathan Zhang <jonzhang@fb.com> | 2020-09-21 17:14:44 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-28 09:39:02 +0000 |
| commit | 1ba42a9ca26b4ecba0164d88e02069a80942c167 (patch) | |
| tree | 53f94e4538fa191e5920fb6e7f62bfdb5106f1ac /src/soc | |
| parent | db202bad099d5d64ba4ebc763e55ed8a48d7fbf1 (diff) | |
soc/intel/xeon_sp/cpx: add ACPI name for CSTACK
Add ACPI name for CSTACK. The name is PC00 to match with ACPI table
generated.
The PCIe domain has multiple PCIe stacks. devicetree.cb at the moment
does not support multiple PCIe stacks, eg. IIO stacks. For now, assign
the name to PCIe domain. In future, the name needs to be assigned to
CSTACK.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I24a6f29734452426218419cdcf66702edde96f46
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/chip.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 2c445f90be..5ee7f6c0a4 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -492,11 +492,23 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) /* not implemented yet */ } +#if CONFIG(HAVE_ACPI_TABLES) +static const char *soc_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PC00"; + return NULL; +} +#endif + static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &xeonsp_cpx_pci_domain_set_resources, .scan_bus = &xeonsp_cpx_pci_domain_scan_bus, +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = &northbridge_write_acpi_tables, + .acpi_name = soc_acpi_name +#endif }; static struct device_operations cpu_bus_ops = { |