summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorSean Rhodes <sean@starlabs.systems>2024-07-18 20:08:26 +0100
committerSean Rhodes <sean@starlabs.systems>2024-10-11 08:31:37 +0000
commit12abfb43dc0a9cbabdb60f04254fff04bf14a8ce (patch)
tree6417fd1d7c6d84b865f055aa77c4d4ec05760606 /src/soc
parent6e546cc695e7babb809d9555383d7c835bf045b8 (diff)
soc/intel/cnvi: Add CNVW OpRegion
The CNVi driver is relatively basic in coreboot and most noticeably, recent Linux kernels flag that lack of a _PRR method, which is used to reset WiFi and Bluetooth. This patch series adds methods recommended by Intel in document #559910. This patch defines an OpRegion for CNVi, for both integrated and dedicated solutions. Change-Id: Idd2ff93fb65c40f656804d96966e1881202ccb56 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/common/block/cnvi/cnvi.c61
-rw-r--r--src/soc/intel/common/block/include/intelblocks/cnvi.h34
2 files changed, 94 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index cf46fdb206..4c434b2260 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -6,12 +6,71 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <intelblocks/cnvi.h>
static const char *cnvi_wifi_acpi_name(const struct device *dev)
{
return "CNVW";
}
+static void cnvw_fill_ssdt(const struct device *dev)
+{
+ const char *scope = acpi_device_path(dev);
+
+ acpi_device_write_pci_dev(dev);
+
+ acpigen_write_scope(scope);
+/*
+ * OperationRegion(CWAR, SystemMemory, Add(\_SB.PCI0.GPCB(), 0xa3000), 0x100)
+ * Field(CWAR, WordAcc, NoLock, Preserve) {
+ * VDID, 32, // 0x00, VID DID
+ * Offset(CNVI_DEV_CAP),
+ * , 28,
+ * WFLR, 1, // Function Level Reset Capable
+ * Offset(CNVI_DEV_CONTROL),
+ * , 15,
+ * WIFR, 1, // Init Function Level Reset
+ * Offset(CNVI_POWER_STATUS),
+ * WPMS, 32,
+ * }
+ */
+
+ /* RegionOffset stored in Local0 */
+ /* Local0 = \_SB_.PCI0.GPCB() + 0xa3000 */
+ acpigen_emit_byte(ADD_OP);
+ acpigen_write_integer(0xa3000);
+ acpigen_emit_namestring("\\_SB_.PCI0.GPCB()");
+ acpigen_emit_byte(LOCAL0_OP);
+
+ /* OperationRegion */
+ acpigen_emit_ext_op(OPREGION_OP);
+ /* NameString 4 chars only */
+ acpigen_emit_namestring("CWAR");
+ /* RegionSpace */
+ acpigen_emit_byte(SYSTEMMEMORY);
+ /* RegionOffset */
+ acpigen_emit_byte(LOCAL0_OP);
+ /* RegionLen */
+ acpigen_write_integer(0x100);
+
+ struct fieldlist fields[] = {
+ FIELDLIST_OFFSET(0),
+ FIELDLIST_NAMESTR("VDID", 32),
+ FIELDLIST_OFFSET(CNVI_DEV_CAP),
+ FIELDLIST_RESERVED(28),
+ FIELDLIST_NAMESTR("WFLR", 1),
+ FIELDLIST_OFFSET(CNVI_DEV_CONTROL),
+ FIELDLIST_RESERVED(15),
+ FIELDLIST_NAMESTR("WIFR", 1),
+ FIELDLIST_OFFSET(CNVI_POWER_STATUS),
+ FIELDLIST_NAMESTR("WPMS", 32),
+ };
+ acpigen_write_field("CWAR", fields, ARRAY_SIZE(fields),
+ FIELD_WORDACC | FIELD_NOLOCK | FIELD_PRESERVE);
+
+ acpigen_write_scope_end();
+}
+
static struct device_operations cnvi_wifi_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
@@ -19,7 +78,7 @@ static struct device_operations cnvi_wifi_ops = {
.ops_pci = &pci_dev_ops_pci,
.scan_bus = scan_static_bus,
.acpi_name = cnvi_wifi_acpi_name,
- .acpi_fill_ssdt = acpi_device_write_pci_dev,
+ .acpi_fill_ssdt = cnvw_fill_ssdt,
};
static const unsigned short wifi_pci_device_ids[] = {
diff --git a/src/soc/intel/common/block/include/intelblocks/cnvi.h b/src/soc/intel/common/block/include/intelblocks/cnvi.h
new file mode 100644
index 0000000000..fa96fdd37d
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/cnvi.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_INTEL_COMMON_CNVI_H_
+#define _SOC_INTEL_COMMON_CNVI_H_
+
+/* CNVi WiFi Register */
+#define CNVI_DEV_CAP 0x44
+#define CNVI_DEV_CONTROL 0x48
+#define CNVI_POWER_STATUS 0xcc
+
+/* CNVi PLDR Results */
+#define CNVI_PLDR_COMPLETE 0x02
+#define CNVI_PLDR_NOT_COMPLETE 0x03
+#define CNVI_PLDR_TIMEOUT 0x04
+
+/* CNVi PLDR Control */
+#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
+#define CNVI_ABORT_PLDR 0x80
+#else
+#define CNVI_ABORT_PLDR 0x44
+#endif
+
+#define CNVI_ABORT_ENABLE BIT(0)
+#define CNVI_ABORT_REQUEST BIT(1)
+#define CNVI_READY BIT(2)
+
+/* CNVi Sideband Port ID */
+#if CONFIG(SOC_INTEL_METEORLAKE)
+#define CNVI_SIDEBAND_ID 0x29
+#else
+#define CNVI_SIDEBAND_ID 0x73
+#endif
+
+#endif // _SOC_INTEL_COMMON_CNVI_H_