soc/intel/quark: Add FSP 2.0 boot block support

Add the pieces necessary to successfully build and run bootblock using
the FSP 2.0 build.

TEST=Build and run bootblock on Galileo Gen2

Change-Id: I2377f0b0147196f100396b8cd7eaca8f92d6932f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15865
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

12 files changed, 128 insertions, 10 deletions

diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index 244cc30681..4924b86372 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -127,11 +127,13 @@ config ENABLE_DEBUG_LED_TEMPRAMINIT
 
 config DCACHE_RAM_BASE
 	hex
-	default 0x80070000
+	default 0x80070000 if PLATFORM_USES_FSP1_1
+	default 0x80000000
 
 config DCACHE_RAM_SIZE
 	hex
-	default 0x00008000
+	default 0x8000 if PLATFORM_USES_FSP1_1
+	default 0x40000
 
 #####
 # Flash layout
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
index 4740ec77a7..a6454d9a1c 100644
--- a/src/soc/intel/quark/Makefile.inc
+++ b/src/soc/intel/quark/Makefile.inc
@@ -35,18 +35,21 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 ramstage-y += chip.c
 ramstage-y += ehci.c
 ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c
+ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c
 ramstage-y += gpio_i2c.c
 ramstage-y += i2c.c
 ramstage-y += lpc.c
 ramstage-y += memmap.c
 ramstage-y += northcluster.c
 ramstage-y += reg_access.c
+ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
 ramstage-y += tsc_freq.c
 ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
 ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
 
 CPPFLAGS_common += -I$(src)/soc/intel/quark
 CPPFLAGS_common += -I$(src)/soc/intel/quark/include
+CPPFLAGS_common += -I$(src)/soc/intel/quark/include/soc/fsp
 
 # Chipset microcode path
 CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark
diff --git a/src/soc/intel/quark/fsp2_0.c b/src/soc/intel/quark/fsp2_0.c
new file mode 100644
index 0000000000..dccd28ef85
--- /dev/null
+++ b/src/soc/intel/quark/fsp2_0.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <console/console.h>
+#include <fsp/util.h>
+#include <soc/ramstage.h>
+
+void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
+{
+}
diff --git a/src/soc/intel/quark/include/soc/car.h b/src/soc/intel/quark/include/soc/car.h
new file mode 100644
index 0000000000..23c6a24fbf
--- /dev/null
+++ b/src/soc/intel/quark/include/soc/car.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_CAR_H_
+#define _SOC_CAR_H_
+
+#include <fsp/util.h>
+
+/* Mainboard and SoC initialization prior to console. */
+void car_mainboard_pre_console_init(void);
+void car_soc_pre_console_init(void);
+
+/* Mainboard and SoC initialization post console initialization. */
+void car_mainboard_post_console_init(void);
+void car_soc_post_console_init(void);
+
+#endif /* _SOC_CAR_H_ */
diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h
index 9f201a0d20..d97db747c3 100644
--- a/src/soc/intel/quark/include/soc/ramstage.h
+++ b/src/soc/intel/quark/include/soc/ramstage.h
@@ -19,10 +19,14 @@
 
 #include <chip.h>
 #include <device/device.h>
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
 #include <fsp/ramstage.h>
+#endif
 #include <soc/QuarkNcSocId.h>
 
 void mainboard_gpio_i2c_init(device_t dev);
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
 void fsp_silicon_init(void);
+#endif
 
 #endif /* _SOC_RAMSTAGE_H_ */
diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h
index fcac3e20aa..d6f9186754 100644
--- a/src/soc/intel/quark/include/soc/romstage.h
+++ b/src/soc/intel/quark/include/soc/romstage.h
@@ -22,7 +22,11 @@
 #error "Don't include romstage.h from a ramstage compilation unit!"
 #endif
 
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
 #include <fsp/romstage.h>
+#else
+#include <soc/car.h>
+#endif
 #include <soc/reg_access.h>
 
 asmlinkage void *car_stage_c_entry(void);
diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c
index f880443e1f..53a1b24094 100644
--- a/src/soc/intel/quark/memmap.c
+++ b/src/soc/intel/quark/memmap.c
@@ -14,16 +14,8 @@
  */
 
 #include <cbmem.h>
-#include <fsp/memmap.h>
-#include <soc/QuarkNcSocId.h>
 #include <soc/reg_access.h>
 
-size_t mmap_region_granularity(void)
-{
-	/* Align to 8 MiB by default */
-	return 8 << 20;
-}
-
 void *cbmem_top(void)
 {
 	uint32_t top_of_memory;
diff --git a/src/soc/intel/quark/reset.c b/src/soc/intel/quark/reset.c
new file mode 100644
index 0000000000..e3d3fac79b
--- /dev/null
+++ b/src/soc/intel/quark/reset.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <fsp/util.h>
+#include <reset.h>
+
+void chipset_handle_reset(enum fsp_status status)
+{
+	/* Do a hard reset if Quark FSP ever requests a reset */
+	printk(BIOS_ERR, "Unknown reset type %x\n", status);
+	hard_reset();
+}
diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc
index 635da83c64..329138b3be 100644
--- a/src/soc/intel/quark/romstage/Makefile.inc
+++ b/src/soc/intel/quark/romstage/Makefile.inc
@@ -16,7 +16,10 @@
 romstage-y += car.c
 romstage-y += car_stage_entry.S
 romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c
+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c
 romstage-y += mtrr.c
 romstage-y += pcie.c
 romstage-y += report_platform.c
 romstage-y += romstage.c
+
+postcar-y += mtrr.c
diff --git a/src/soc/intel/quark/romstage/car_stage_entry.S b/src/soc/intel/quark/romstage/car_stage_entry.S
index d0a0db0f5d..b8207117fa 100644
--- a/src/soc/intel/quark/romstage/car_stage_entry.S
+++ b/src/soc/intel/quark/romstage/car_stage_entry.S
@@ -29,9 +29,11 @@ car_stage_entry:
 	/* Enter the C code */
 	call	car_stage_c_entry
 
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
 #if !ENV_VERSTAGE
 #include "src/drivers/intel/fsp1_1/after_raminit.S"
 #endif
+#endif
 
 	/* The code should never reach this point */
 	movb	$0x69, %ah
diff --git a/src/soc/intel/quark/romstage/fsp1_1.c b/src/soc/intel/quark/romstage/fsp1_1.c
index 73910a0775..16d1d063c3 100644
--- a/src/soc/intel/quark/romstage/fsp1_1.c
+++ b/src/soc/intel/quark/romstage/fsp1_1.c
@@ -19,9 +19,11 @@
 #include <console/console.h>
 #include <cbfs.h>
 #include "../chip.h"
+#include <fsp/memmap.h>
 #include <fsp/util.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
+#include <soc/QuarkNcSocId.h>
 #include <soc/romstage.h>
 #include <string.h>
 
@@ -65,6 +67,12 @@ struct chipset_power_state *fill_power_state(void)
 	return ps;
 }
 
+size_t mmap_region_granularity(void)
+{
+	/* Align to 8 MiB by default */
+	return 8 << 20;
+}
+
 /* Initialize the UPD parameters for MemoryInit */
 void soc_memory_init_params(struct romstage_params *params,
 			    MEMORY_INIT_UPD *upd)
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c
new file mode 100644
index 0000000000..a77349897d
--- /dev/null
+++ b/src/soc/intel/quark/romstage/fsp2_0.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <fsp/util.h>
+#include <soc/romstage.h>
+
+asmlinkage void *car_stage_c_entry(void)
+{
+	post_code(0x20);
+	console_init();
+	return NULL;
+}