diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-11-21 12:43:04 +0100 |
|---|---|---|
| committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2023-06-15 13:57:29 +0000 |
| commit | 0d28b978e51b5c4c7b3a5a9fc8b20f1fd06690c7 (patch) | |
| tree | ce0c0eace407f4a8de3a2d95aa4cb39d7f03a2ff /src/soc | |
| parent | 12a448224f512deba57221c0757f148e626240e0 (diff) | |
intel/cmn/smm: Introduce PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B
Certain chipsets/SoCs like Apollo Lake use GEN_PMCON_B for periodic SMI
rate selection unlike other chipsets which use GEN_PMCON_A. Introduce new Kconfig option PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B to
indicate the register difference.
Based on Apollo Lake datasheet Vol. 3 Revision 005:
https://cdrdv2.intel.com/v1/dl/getContent/334819
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I11241836ecc9066d323977b030686567c87ed256
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/common/block/smm/Kconfig | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/smm/Kconfig b/src/soc/intel/common/block/smm/Kconfig index 2d960d6b47..4944ade5db 100644 --- a/src/soc/intel/common/block/smm/Kconfig +++ b/src/soc/intel/common/block/smm/Kconfig @@ -44,3 +44,12 @@ config HECI_DISABLE_USING_SMM help HECI disable using SMM. Select this option to make HECI disable using SMM mode, independent of dedicated UPD to perform HECI disable. + +config PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B + bool + depends on SOC_INTEL_COMMON_BLOCK_SMM + default n + help + Intel Core processors select the periodic SMI rate via GEN_PMCON_A. + On Intel Atom processors the register is different and they use + GEN_PMCON_B/GEN_PMCON2 with different address. |