diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2022-01-27 07:55:34 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-28 15:10:46 +0000 |
| commit | 0bc5d9dfff8ecd380fa914a6e0885aef04467f8d (patch) | |
| tree | fa1fc19c9f19b8e315b8d8e8fd152bd541c5a62d /src/soc | |
| parent | f711bf03a694bc594a610a70251716d425fbe101 (diff) | |
src/{drivers,soc}: Fix some code indents
Change-Id: I55682de4a1bc74f170e2044de35b0d8d53ef51ff
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/baytrail/sata.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/braswell/ramstage.c | 4 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/dramc_pi_basic_api.c | 2 | ||||
| -rw-r--r-- | src/soc/samsung/exynos5420/dp.c | 10 |
4 files changed, 9 insertions, 9 deletions
diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c index 24c805ac81..5e5215b249 100644 --- a/src/soc/intel/baytrail/sata.c +++ b/src/soc/intel/baytrail/sata.c @@ -71,7 +71,7 @@ static void sata_init(struct device *dev) pci_write_config16(dev, 0x92, reg16); if (config->sata_ahci) { - u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); /* Enable CR memory space decoding */ reg16 = pci_read_config16(dev, 0x04); diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 48f2193e47..42d1f9f080 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -68,11 +68,11 @@ static void fill_in_pattrs(void) dev = pcidev_on_root(LPC_DEV, LPC_FUNC); attrs->revid = pci_read_config8(dev, REVID); /* The revision to stepping IDs have two values per metal stepping. */ - if (attrs->revid >= RID_D_STEPPING_START) { + if (attrs->revid >= RID_D_STEPPING_START) { attrs->stepping = (attrs->revid - RID_D_STEPPING_START) / 2; attrs->stepping += STEP_D1; - } else if (attrs->revid >= RID_C_STEPPING_START) { + } else if (attrs->revid >= RID_C_STEPPING_START) { attrs->stepping = (attrs->revid - RID_C_STEPPING_START) / 2; attrs->stepping += STEP_C0; diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index 23a9403acf..10d03e0c8e 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -828,7 +828,7 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2, /* 4. enable read/write test */ if (wr == TE_OP_READ_CHECK) { - if ((testaudpat == 1) || (testaudpat == 2)) { + if ((testaudpat == 1) || (testaudpat == 2)) { /* if audio pattern, enable read only */ /* (disable write after read), */ /* AUDMODE=0x48[15]=0 */ diff --git a/src/soc/samsung/exynos5420/dp.c b/src/soc/samsung/exynos5420/dp.c index 758e09b05d..13a8feff41 100644 --- a/src/soc/samsung/exynos5420/dp.c +++ b/src/soc/samsung/exynos5420/dp.c @@ -336,8 +336,8 @@ static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable) ret = exynos_dp_write_byte_to_dpcd(DPCD_LANE_COUNT_SET, data); if (ret != EXYNOS_DP_SUCCESS) { - printk(BIOS_ERR, "DP write_to_dpcd failed\n"); - return -1; + printk(BIOS_ERR, "DP write_to_dpcd failed\n"); + return -1; } @@ -467,9 +467,9 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat); if (ret != EXYNOS_DP_SUCCESS) { - printk(BIOS_ERR, "DP read lane status failed\n"); - edp_info->lt_info.lt_status = DP_LT_FAIL; - return ret; + printk(BIOS_ERR, "DP read lane status failed\n"); + edp_info->lt_info.lt_status = DP_LT_FAIL; + return ret; } if (lane_stat & DP_LANE_STAT_CR_DONE) { |