diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-02-27 23:56:39 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-02-28 23:45:04 +0000 |
| commit | 0a466040e0dc3351ac819ba00146f284e5f70f05 (patch) | |
| tree | ac3ce1a7d8f14775d323acd05999d417f56d53ff /src/soc | |
| parent | 54c80e1df16d356dc73030903daece5fcb50e7bc (diff) | |
soc/amd: introduce and use PSTATE_MSR macro
Instead of adding the P-state number to the PSTATE_0_MSR number to get
the P-state MSR number for the rdmsr call, provide a macro that directly
calculates the MSR number for a given power state. Also drop the unused
PSTATE_[1..4]_MSR definitions which also didn't cover all P-state MSRs
available in the hardware.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If85acf556efe82c209e1608e56c05f7a2a748403
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/cezanne/acpi.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/common/block/cpu/tsc/tsc_freq.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/glinda/acpi.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/mendocino/acpi.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/phoenix/acpi.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/picasso/acpi.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/tsc_freq.c | 2 |
7 files changed, 7 insertions, 7 deletions
diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 631f388fdf..46eaadca57 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -200,7 +200,7 @@ static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values, max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT; for (pstate = 0; pstate <= max_pstate; pstate++) { - pstate_def = rdmsr(PSTATE_0_MSR + pstate); + pstate_def = rdmsr(PSTATE_MSR(pstate)); pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK) >> PSTATE_DEF_HI_ENABLE_SHIFT; diff --git a/src/soc/amd/common/block/cpu/tsc/tsc_freq.c b/src/soc/amd/common/block/cpu/tsc/tsc_freq.c index 55c86653ce..fbbf399731 100644 --- a/src/soc/amd/common/block/cpu/tsc/tsc_freq.c +++ b/src/soc/amd/common/block/cpu/tsc/tsc_freq.c @@ -22,7 +22,7 @@ unsigned long tsc_freq_mhz(void) return mhz; high_state = rdmsr(PS_LIM_REG).lo & 0x7; - msr = rdmsr(PSTATE_0_MSR + high_state); + msr = rdmsr(PSTATE_MSR(high_state)); if (!(msr.hi & 0x80000000)) die("Unknown error: cannot determine P-state 0\n"); diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index 31723b1b4f..675ab20f12 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -203,7 +203,7 @@ static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values, max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT; for (pstate = 0; pstate <= max_pstate; pstate++) { - pstate_def = rdmsr(PSTATE_0_MSR + pstate); + pstate_def = rdmsr(PSTATE_MSR(pstate)); pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK) >> PSTATE_DEF_HI_ENABLE_SHIFT; diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 044b345df1..fb4d103aee 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -202,7 +202,7 @@ static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values, max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT; for (pstate = 0; pstate <= max_pstate; pstate++) { - pstate_def = rdmsr(PSTATE_0_MSR + pstate); + pstate_def = rdmsr(PSTATE_MSR(pstate)); pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK) >> PSTATE_DEF_HI_ENABLE_SHIFT; diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index 09c4a15401..25ebc66afd 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -203,7 +203,7 @@ static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values, max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT; for (pstate = 0; pstate <= max_pstate; pstate++) { - pstate_def = rdmsr(PSTATE_0_MSR + pstate); + pstate_def = rdmsr(PSTATE_MSR(pstate)); pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK) >> PSTATE_DEF_HI_ENABLE_SHIFT; diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index f6fb9f259d..138e743d0c 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -202,7 +202,7 @@ static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values, max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT; for (pstate = 0; pstate <= max_pstate; pstate++) { - pstate_def = rdmsr(PSTATE_0_MSR + pstate); + pstate_def = rdmsr(PSTATE_MSR(pstate)); pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK) >> PSTATE_DEF_HI_ENABLE_SHIFT; diff --git a/src/soc/amd/stoneyridge/tsc_freq.c b/src/soc/amd/stoneyridge/tsc_freq.c index 01f2321f8c..0be93aa571 100644 --- a/src/soc/amd/stoneyridge/tsc_freq.c +++ b/src/soc/amd/stoneyridge/tsc_freq.c @@ -23,7 +23,7 @@ unsigned long tsc_freq_mhz(void) boost_states = (pci_read_config32(SOC_PM_DEV, CORE_PERF_BOOST_CTRL) >> 2) & 0x7; - msr = rdmsr(PSTATE_0_MSR + boost_states); + msr = rdmsr(PSTATE_MSR(boost_states)); if (!(msr.hi & 0x80000000)) die("Unknown error: cannot determine P-state 0\n"); |