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| author | Raul E Rangel <rrangel@chromium.org> | 2020-05-07 15:19:53 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-13 08:36:25 +0000 |
| commit | e44651b496a2f88fd1212ab4228323a5eee1b80c (patch) | |
| tree | 0fe6437acd41ac9c00924731f5c677d46f769b01 /src/soc | |
| parent | b1ffca30576770999199fc8b691cfdd1185a30d5 (diff) | |
soc/amd/picasso: Add data fabric register definitions
These are used to setup the data fabric.
Definitions came from 55570-B1 Rev 3.14 - PPR for AMD Family 17h Model 18h
BUG=b:147042464
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib51f6e2fd304da9948d6625608af71f25b974854
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41266
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/data_fabric.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h new file mode 100644 index 0000000000..af9c200ce2 --- /dev/null +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_PICASSO_DATAFABRIC_H__ +#define __SOC_PICASSO_DATAFABRIC_H__ + +#include <types.h> + +/* D18F0 - Fabric Configuration registers */ +#define IOMS0_FABRIC_ID 9 + +#define D18F0_VGAEN 0x80 +#define VGA_ADDR_ENABLE BIT(0) + +#define D18F0_MMIO_BASE0 0x200 +#define D18F0_MMIO_LIMIT0 0x204 +#define D18F0_MMIO_SHIFT 16 +#define D18F0_MMIO_CTRL0 0x208 +#define MMIO_NP BIT(12) +#define MMIO_DST_FABRIC_ID_SHIFT 4 +#define MMIO_WE BIT(1) +#define MMIO_RE BIT(0) +#define NUM_NB_MMIO_REGS 8 +#define NB_MMIO_BASE(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_BASE0) +#define NB_MMIO_LIMIT(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_LIMIT0) +#define NB_MMIO_CONTROL(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_CTRL0) + +#endif /* __SOC_PICASSO_DATAFABRIC_H__ */ |