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authorKarthikeyan Ramasubramanian <kramasub@google.com>2020-04-20 13:43:29 -0600
committerPatrick Georgi <pgeorgi@google.com>2020-05-01 06:10:04 +0000
commite0b7a88f586d746c72da1fedfbeda3156faf4d73 (patch)
tree28cb7ab20ca3e04f48b24febb2b5ca665a76b066 /src/soc
parent3b9d995ecb99063adc2c79bb3c2e73de72499e01 (diff)
soc/intel/jasperlake: Add support to generate ACPI GPIO operations
Add support to generate ACPI operations to get/set/clear RX/TX GPIOs. BUG=b:152936541 TEST=Build and boot the mainboard. Ensure that there are no errors in the coreboot logs regarding unsupported ACPI GPIO operations. Change-Id: Ibc4846fbd9baf4f22c48c82acefed960669ed7d4 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/jasperlake/acpi.c37
1 files changed, 37 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c
index 4acd8a6131..b390968708 100644
--- a/src/soc/intel/jasperlake/acpi.c
+++ b/src/soc/intel/jasperlake/acpi.c
@@ -330,3 +330,40 @@ int soc_madt_sci_irq_polarity(int sci)
{
return MP_IRQ_POLARITY_HIGH;
}
+
+static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num)
+{
+ /* op (gpio_num) */
+ acpigen_emit_namestring(op);
+ acpigen_write_integer(gpio_num);
+ return 0;
+}
+
+static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num)
+{
+ /* Store (op (gpio_num), Local0) */
+ acpigen_write_store();
+ acpigen_soc_gpio_op(op, gpio_num);
+ acpigen_emit_byte(LOCAL0_OP);
+ return 0;
+}
+
+int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
+{
+ return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num);
+}
+
+int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
+{
+ return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num);
+}
+
+int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
+{
+ return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num);
+}
+
+int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
+{
+ return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num);
+}