diff options
| author | Moritz Fischer <moritzf@google.com> | 2021-02-17 21:34:53 -0800 |
|---|---|---|
| committer | ron minnich <rminnich@gmail.com> | 2021-02-19 19:06:35 +0000 |
| commit | d8f352b4fd0e260494fdb14d04b73b11607bee9d (patch) | |
| tree | 89099f460d311e05f4503d94245903f83c98f51a /src/soc | |
| parent | d8fcd42089f109fffeb6cdcf1745013b91d7513e (diff) | |
soc/rockchip/rk3399/sdram: Clear PI_175 IRQs in data training
Clear PI_175 interrupts before attempting training in all relevant
calls.
Ported from u-boot.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: Ib73f58265db62494282dbec42ec4bf2950617e12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50886
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/rockchip/rk3399/sdram.c | 26 |
1 files changed, 21 insertions, 5 deletions
diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 132759aa20..89463aa174 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -618,6 +618,9 @@ static int data_training_ca(u32 channel, const struct rk3399_sdram_params *param u32 obs_0, obs_1, obs_2, obs_err = 0; u32 rank = params->ch[channel].rank; + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ + write32(&denali_pi[175], 0x00003f7c); + for (i = 0; i < rank; i++) { select_per_cs_training_index(channel, i); /* PI_100 PI_CALVL_EN:RW:8:2 */ @@ -647,7 +650,7 @@ static int data_training_ca(u32 channel, const struct rk3399_sdram_params *param return -1; } /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ - write32((&denali_pi[175]), 0x00003f7c); + write32(&denali_pi[175], 0x00003f7c); } clrbits32(&denali_pi[100], 0x3 << 8); @@ -662,6 +665,9 @@ static int data_training_wl(u32 channel, const struct rk3399_sdram_params *param u32 rank = params->ch[channel].rank; u32 i, tmp; + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ + write32(&denali_pi[175], 0x00003f7c); + for (i = 0; i < rank; i++) { select_per_cs_training_index(channel, i); /* PI_60 PI_WRLVL_EN:RW:8:2 */ @@ -692,7 +698,7 @@ static int data_training_wl(u32 channel, const struct rk3399_sdram_params *param return -1; } /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ - write32((&denali_pi[175]), 0x00003f7c); + write32(&denali_pi[175], 0x00003f7c); } override_write_leveling_value(channel); @@ -731,6 +737,10 @@ static int data_training_rg(u32 channel, const struct rk3399_sdram_params *param clrbits32(&denali_phy[262], 0x7 << 24); clrbits32(&denali_phy[390], 0x7 << 24); } + + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ + write32(&denali_pi[175], 0x00003f7c); + for (i = 0; i < rank; i++) { select_per_cs_training_index(channel, i); /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */ @@ -765,7 +775,7 @@ static int data_training_rg(u32 channel, const struct rk3399_sdram_params *param return -1; } /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ - write32((&denali_pi[175]), 0x00003f7c); + write32(&denali_pi[175], 0x00003f7c); } clrbits32(&denali_pi[80], 0x3 << 24); @@ -790,6 +800,9 @@ static int data_training_rl(u32 channel, const struct rk3399_sdram_params *param u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi; + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ + write32(&denali_pi[175], 0x00003f7c); + for (i = 0; i < rank; i++) { select_per_cs_training_index(channel, i); /* PI_80 PI_RDLVL_EN:RW:16:2 */ @@ -813,7 +826,7 @@ static int data_training_rl(u32 channel, const struct rk3399_sdram_params *param return -1; } /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ - write32((&denali_pi[175]), 0x00003f7c); + write32(&denali_pi[175], 0x00003f7c); } clrbits32(&denali_pi[80], 0x3 << 16); @@ -826,6 +839,9 @@ static int data_training_wdql(u32 channel, const struct rk3399_sdram_params *par u32 rank = params->ch[channel].rank; u32 i, tmp; + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ + write32(&denali_pi[175], 0x00003f7c); + for (i = 0; i < rank; i++) { select_per_cs_training_index(channel, i); /* @@ -848,7 +864,7 @@ static int data_training_wdql(u32 channel, const struct rk3399_sdram_params *par return -1; } /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ - write32((&denali_pi[175]), 0x00003f7c); + write32(&denali_pi[175], 0x00003f7c); } clrbits32(&denali_pi[124], 0x3 << 16); |